[Qemu-devel] [PATCH] hw/sh4: Add dtb support

New SH kernel use dtb. This patch add dtb support for R2D board emulation. Signed-off-by: Yoshinori Sato --- hw/sh4/r2d.c | 52 +++- 1 file changed, 43 insertions(+), 9 deletions(-) diff --git a/hw/sh4/r2d.c b/hw/sh4/r2d.c index f2547ed..203c117

Re: [PATCH] target/sh4: Honor QEMU_LOG_FILENAME with QEMU_LOG=cpu

se if (env->flags & DELAY_SLOT_CONDITIONAL) { > -qemu_printf("in conditional delay slot (delayed_pc=0x%08x)\n", > - env->delayed_pc); > +qemu_fprintf(f, "in conditional delay slot (delayed_pc=0x%08x)\n", > + env->delayed_pc); > } else if (env->flags & DELAY_SLOT_RTE) { > qemu_fprintf(f, "in rte delay slot (delayed_pc=0x%08x)\n", > env->delayed_pc); > -- > 2.35.3 > Reviewd-by: Yoshinori Sato -- Yosinori Sato

Re: [PATCH v1 07/21] sh4: correct typos

ion-related registers > */ > > /* Immediate data for TRAPA instruction - TRA */ > -- > γαῖα πυρί μιχθήτω > Reviewed-by: Yoshinori Sato -- Yosinori Sato

Re: [PATCH v3 02/11] hw/rx/rx62n: Reduce inclusion of 'qemu/units.h'

; +++ b/hw/rx/rx62n.c > @@ -23,6 +23,7 @@ > #include "qemu/osdep.h" > #include "qapi/error.h" > #include "qemu/error-report.h" > +#include "qemu/units.h" > #include "hw/rx/rx62n.h" > #include "hw/loader.h" > #include "hw/sysbus.h" > -- > 2.41.0 > Reviewed-by: Yoshinori Sato -- Yosinori Sato

Re: [PATCH v3 03/11] hw/rx/rx62n: Only call qdev_get_gpio_in() when necessary

{ > - sysbus_connect_irq(sci, i, s->irq[irqbase + i]); > +sysbus_connect_irq(sci, i, > + qdev_get_gpio_in(DEVICE(&s->icu), irqbase + i)); > } > sysbus_mmio_map(sci, 0, RX62N_SCI_BASE + unit * 0x08); > } > -- > 2.41.0 > Reviewed-by: Yoshinori Sato -- Yosinori Sato

Re: [PATCH v3 07/11] hw/sh4/r2d: Realize IDE controller before accessing it

sysbus_mmio_map(busdev, 1, 0x1400080c); > mmio_ide_init_drives(dev, dinfo, NULL); > -- > 2.41.0 > Reviewed-by: Yoshinori Sato -- Yosinori Sato

Re: [PATCH] sh4: mac.w: memory accesses are 16-bit words

sas.com/us/en/document/mas/sh-4-software-manual > This instruction performs signed multiplication of the 16-bit operands > whose addresses are the contents of general registers Rm and Rn, > adds the 32-bit result to the MAC register contents, and stores the > result in the MAC register. Operands Rm and Rn are each incremented > by 2 each time they are read. Reviewed-by: Yoshinori Sato -- Yosinori Sato

Re: [PATCH v2] sh4: mac.w: implement saturation arithmetic logic

* If there is no overflow, the result is already inside > + * the saturation bounds. > + * > + * If there was no overflow, MACH is unchanged. > + */ > +env->macl = result; > } > +} else { > +/* In non-saturation arithmetic mode, the accumulator is 64-bit */ > +int64_t mac = (((uint64_t)env->mach) << 32) | env->macl; > + > +/* The carry bit of the 64-bit addition is discarded */ > +int64_t result = mac + (int64_t)mul; > +env->macl = result; > +env->mach = result >> 32; > } > } > > -- > 2.41.0 > Reviewd-by: Yoshinori Sato -- Yosinori Sato

Re: [PATCH 30/32] target/rx: Use translator_ld*

On Fri, 05 Apr 2024 19:24:57 +0900, Richard Henderson wrote: > > Cc: Yoshinori Sato > Signed-off-by: Richard Henderson > --- > target/rx/translate.c | 27 ++- > 1 file changed, 14 insertions(+), 13 deletions(-) > > diff --git a/target/rx

Re: [PATCH] target/sh4: add missing CHECK_NOT_DELAY_SLOT

4 + B7_0 * 4) & ~3); > return; > -- > 2.41.0 > That's what the documentation said. > If a PC-relative load instruction is executed in a delay slot, > an illegal slot instruction exception will be generated. Reviewed-by: Yoshinori Sato -- Yosinori Sato

Re: [PATCH v4 2/4] target/sh4: Fix SUBV opcode

subv(INT_MAX, 1, INT_MAX - 1, 0); > +subv(0, 1, -1, 0); > +subv(-1, -1, 0, 0); > + > +return 0; > +} > diff --git a/tests/tcg/sh4/Makefile.target b/tests/tcg/sh4/Makefile.target > index 521b8b0a76..7852fa62d8 100644 > --- a/tests/tcg/sh4/Makefile.target > +++ b/tests/tcg/sh4/Makefile.target > @@ -20,3 +20,6 @@ TESTS += test-macw > > test-addv: CFLAGS += -O -g > TESTS += test-addv > + > +test-subv: CFLAGS += -O -g > +TESTS += test-subv > -- > 2.41.0 > Reviewed-by: Yoshinori Sato -- Yosinori Sato

Re: [PATCH v4 1/4] target/sh4: Fix ADDV opcode

; +{ > +addv(INT_MAX, 1, INT_MIN, 1); > +addv(INT_MAX - 1, 1, INT_MAX, 0); > + > +return 0; > +} > diff --git a/tests/tcg/sh4/Makefile.target b/tests/tcg/sh4/Makefile.target > index 4d09291c0c..521b8b0a76 100644 > --- a/tests/tcg/sh4/Makefile.target > +++ b/tests/tcg/sh4/Makefile.target > @@ -17,3 +17,6 @@ TESTS += test-macl > > test-macw: CFLAGS += -O -g > TESTS += test-macw > + > +test-addv: CFLAGS += -O -g > +TESTS += test-addv > -- > 2.41.0 > Reviewed-by: Yoshinori Sato -- Yosinori Sato

Re: [PATCH v4 3/4] target/sh4: Rename TCGv variables as manual for ADDV opcode

tcg_gen_xor_i32(t2, Rm, Rn); > tcg_gen_andc_i32(cpu_sr_t, t1, t2); > tcg_gen_shri_i32(cpu_sr_t, cpu_sr_t, 31); > -tcg_gen_mov_i32(REG(B11_8), t0); > + tcg_gen_mov_i32(Rn, result); > } > return; > case 0x2009: /* and Rm,Rn */ > -- > 2.41.0 > Reviewed-by: Yoshinori Sato -- Yosinori Sato

Re: [PATCH v4 4/4] target/sh4: Rename TCGv variables as manual for SUBV opcode

, Rn, Rm); > tcg_gen_and_i32(t1, t1, t2); > tcg_gen_shri_i32(cpu_sr_t, t1, 31); > -tcg_gen_mov_i32(REG(B11_8), t0); > + tcg_gen_mov_i32(Rn, result); > } > return; > case 0x2008: /* tst Rm,Rn */ > -- > 2.41.0 > Reviewed-by: Yoshinori Sato -- Yosinori Sato

Re: [PATCH for-9.0 v3 0/4] target/sh4: Fix mac.[lw]

On Sat, 04 May 2024 17:25:52 +0900, Michael Tokarev wrote: > > 06.04.2024 08:37, Richard Henderson wrote: > > Zack's recent patches, tidied a little bit, and with > > test cases added. > > These fixes ended up in stable-8.2, but not in stable-7.2. > This is because in 7.2, the context is a bit di

Re: [PATCH] target/sh4: Update DisasContextBase.insn_start

@@ static void decode_gusa(DisasContext *ctx, CPUSH4State > *env) > */ > for (i = 1; i < max_insns; ++i) { > tcg_gen_insn_start(pc + i * 2, ctx->envflags); > +ctx->base.insn_start = tcg_last_op(); > } > } > #endif > -- > 2.34.1 > Reviewed-by: Yoshinori Sato -- Yosinori Sato

[Qemu-devel] [PATCH RFC v8 03/12] target/rx: CPU definition

Signed-off-by: Yoshinori Sato --- target/rx/cpu-qom.h | 52 target/rx/cpu.h | 196 ++ target/rx/cpu.c | 222 3 files changed, 470 insertions(+) create mode 100644 target/rx/cpu

[Qemu-devel] [PATCH RFC v8 07/12] hw/timer: RX62N internal timer modules

renesas_tmr: 8bit timer modules. renesas_cmt: 16bit compare match timer modules. This part use many renesas's CPU. Hardware manual. https://www.renesas.com/us/en/doc/products/mpumcu/doc/rx_family/r01uh0033ej0140_rx62n.pdf Signed-off-by: Yoshinori Sato --- include/hw/timer/renesas_cmt.h

[Qemu-devel] [PATCH RFC v8 10/12] Add rx-softmmu

Signed-off-by: Yoshinori Sato --- configure | 8 default-configs/rx-softmmu.mak | 7 +++ include/sysemu/arch_init.h | 1 + arch_init.c| 2 ++ hw/Kconfig | 1 + 5 files changed, 19 insertions(+) create mode 100644

[Qemu-devel] [PATCH RFC v8 05/12] target/rx: Miscellaneous files

Signed-off-by: Yoshinori Sato --- target/rx/gdbstub.c | 112 target/rx/monitor.c | 38 target/rx/Makefile.objs | 11 + 3 files changed, 161 insertions(+) create mode 100644 target/rx/gdbstub.c create mode 100644

[Qemu-devel] [PATCH RFC v8 12/12] hw/registerfields.h: Add 8bit and 16bit register macros.

Some RX peripheral using 8bit and 16bit registers. Added 8bit and 16bit APIs. Signed-off-by: Yoshinori Sato --- include/hw/registerfields.h | 28 +++- 1 file changed, 27 insertions(+), 1 deletion(-) diff --git a/include/hw/registerfields.h b/include/hw/registerfields.h

[Qemu-devel] [PATCH RFC v8 00/12] Add RX archtecture support

-kernel zImage -dtb rx-qemu.dtb -append "earlycon" Changes for v7. Fix bra.l and bsr.l instructions. Following the fix of the master branch. Yoshinori Sato (12): target/rx: TCG translation target/rx: TCG helper target/rx: CPU definition target/rx: RX disassembler target/rx: Miscellan

[Qemu-devel] [PATCH RFC v8 11/12] MAINTAINERS: Add RX

Signed-off-by: Yoshinori Sato --- MAINTAINERS | 19 +++ 1 file changed, 19 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 7dd71e0a2d..e9430b6c0b 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -272,6 +272,13 @@ F: include/hw/riscv/ F: linux-user/host/riscv32/ F

[Qemu-devel] [PATCH RFC v8 09/12] hw/rx: RX Target hardware definition

rx62n - RX62N cpu. rxqemu - QEMU virtual target. Signed-off-by: Yoshinori Sato --- include/hw/rx/rx.h| 7 ++ include/hw/rx/rx62n.h | 54 hw/rx/rx62n.c | 226 ++ hw/rx/rxqemu.c| 100 ++ hw/rx

[Qemu-devel] [PATCH RFC v8 06/12] hw/intc: RX62N interrupt controller (ICUa)

This implementation supported only ICUa. Hardware manual. https://www.renesas.com/us/en/doc/products/mpumcu/doc/rx_family/r01uh0033ej0140_rx62n.pdf Signed-off-by: Yoshinori Sato --- include/hw/intc/rx_icu.h | 49 +++ hw/intc/rx_icu.c | 373

[Qemu-devel] [PATCH RFC v8 08/12] hw/char: RX62N serical communication interface (SCI)

This module supported only non FIFO type. Hardware manual. https://www.renesas.com/us/en/doc/products/mpumcu/doc/rx_family/r01uh0033ej0140_rx62n.pdf Signed-off-by: Yoshinori Sato --- include/hw/char/renesas_sci.h | 45 ++ hw/char/renesas_sci.c | 341

[Qemu-devel] [PATCH RFC v8 04/12] target/rx: RX disassembler

Signed-off-by: Yoshinori Sato --- include/disas/dis-asm.h |5 + target/rx/disas.c | 1481 +++ 2 files changed, 1486 insertions(+) create mode 100644 target/rx/disas.c diff --git a/include/disas/dis-asm.h b/include/disas/dis-asm.h index

[Qemu-devel] [PATCH RFC v8 02/12] target/rx: TCG helper

Signed-off-by: Yoshinori Sato --- target/rx/helper.h| 31 target/rx/helper.c| 148 target/rx/op_helper.c | 481 ++ 3 files changed, 660 insertions(+) create mode 100644 target/rx/helper.h create mode 100644 target

[Qemu-devel] [PATCH RFC v8 01/12] target/rx: TCG translation

This part only supported RXv1 instructions. Instruction manual. https://www.renesas.com/us/en/doc/products/mpumcu/doc/rx_family/r01us0032ej0120_rxsm.pdf Signed-off-by: Yoshinori Sato --- target/rx/translate.c | 2433 target/rx/insns.decode

Re: [Qemu-devel] [PATCH RFC v8 07/12] hw/timer: RX62N internal timer modules

On Sat, 04 May 2019 00:20:47 +0900, Alex Bennée wrote: > > > Yoshinori Sato writes: > > > renesas_tmr: 8bit timer modules. > > renesas_cmt: 16bit compare match timer modules. > > This part use many renesas's CPU. > > Hardware manual. > > https:

Re: [Qemu-devel] [PATCH RFC v8 09/12] hw/rx: RX Target hardware definition

On Sat, 04 May 2019 00:38:38 +0900, Alex Bennée wrote: > > > Yoshinori Sato writes: > > > rx62n - RX62N cpu. > > rxqemu - QEMU virtual target. > > > > Signed-off-by: Yoshinori Sato > > --- > > include/hw/rx/rx.h| 7 ++ > > inclu

Re: [Qemu-devel] [PATCH RFC v8 05/12] target/rx: Miscellaneous files

On Sat, 04 May 2019 01:06:44 +0900, Alex Bennée wrote: > > > Yoshinori Sato writes: > > > Signed-off-by: Yoshinori Sato > > --- > > target/rx/gdbstub.c | 112 > > > > target/rx/monitor.c

Re: [Qemu-devel] [PATCH RFC v8 01/12] target/rx: TCG translation

On Sat, 04 May 2019 03:43:23 +0900, Richard Henderson wrote: > > On 5/2/19 7:33 AM, Yoshinori Sato wrote: > > +/* conditional branch helper */ > > +static void rx_bcnd_main(DisasContext *ctx, int cd, int dst) > > +{ > > +DisasCompare dc; > > +TCGLabel

Re: [Qemu-devel] [PATCH RFC v8 12/12] hw/registerfields.h: Add 8bit and 16bit register macros.

On Sat, 04 May 2019 00:27:29 +0900, Alex Bennée wrote: > > > Yoshinori Sato writes: > > > Some RX peripheral using 8bit and 16bit registers. > > Added 8bit and 16bit APIs. > > Doesn't this mean the build breaks at some point? Features used by other > pat

Re: [Qemu-devel] [PATCH RFC v8 00/12] Add RX archtecture support

On Sat, 04 May 2019 01:11:48 +0900, Alex Bennée wrote: > > > Yoshinori Sato writes: > > > Hello. > > This patch series is added Renesas RX target emulation. > > I think the series is almost there - it's mostly just nits and clean > build fixes to sort out

Re: [Qemu-devel] [PATCH RFC v8 08/12] hw/char: RX62N serical communication interface (SCI)

On Sat, 04 May 2019 00:22:44 +0900, Alex Bennée wrote: > > > Yoshinori Sato writes: > > > nit: typo in subject (serical->serial) > > > This module supported only non FIFO type. > > Hardware manual. > > https://www.renesas.com/us/en/doc/products/mpum

[Qemu-devel] [PATCH v9 00/13] Add RX archtecture support

FIELD_EX16. - Add extract8 and extract16. Yoshinori Sato (13): target/rx: TCG translation target/rx: TCG helper target/rx: CPU definition target/rx: RX disassembler target/rx: Miscellaneous files hw/intc: RX62N interrupt controller (ICUa) hw/timer: RX62N internal timer modules hw/c

[Qemu-devel] [PATCH v9 05/13] target/rx: Miscellaneous files

Signed-off-by: Yoshinori Sato --- target/rx/gdbstub.c | 112 target/rx/monitor.c | 38 target/rx/Makefile.objs | 12 ++ 3 files changed, 162 insertions(+) create mode 100644 target/rx/gdbstub.c create mode 100644

[Qemu-devel] [PATCH v9 12/13] hw/registerfields.h: Add 8bit and 16bit register macros.

Some RX peripheral using 8bit and 16bit registers. Added 8bit and 16bit APIs. Signed-off-by: Yoshinori Sato --- include/hw/registerfields.h | 32 +++- 1 file changed, 31 insertions(+), 1 deletion(-) diff --git a/include/hw/registerfields.h b/include/hw

[Qemu-devel] [PATCH v9 08/13] hw/char: RX62N serial communication interface (SCI)

This module supported only non FIFO type. Hardware manual. https://www.renesas.com/us/en/doc/products/mpumcu/doc/rx_family/r01uh0033ej0140_rx62n.pdf Signed-off-by: Yoshinori Sato --- include/hw/char/renesas_sci.h | 45 ++ hw/char/renesas_sci.c | 340

[Qemu-devel] [PATCH v9 13/13] qemu/bitops.h: Add extract8 and extract16

Signed-off-by: Yoshinori Sato --- include/qemu/bitops.h | 38 ++ 1 file changed, 38 insertions(+) diff --git a/include/qemu/bitops.h b/include/qemu/bitops.h index 3f0926cf40..0dfd81efb2 100644 --- a/include/qemu/bitops.h +++ b/include/qemu/bitops.h @@ -301,6

[Qemu-devel] [PATCH v9 10/13] Add rx-softmmu

Signed-off-by: Yoshinori Sato --- configure | 8 default-configs/rx-softmmu.mak | 7 +++ include/sysemu/arch_init.h | 1 + arch_init.c| 2 ++ hw/Kconfig | 1 + 5 files changed, 19 insertions(+) create mode 100644

[Qemu-devel] [PATCH v9 06/13] hw/intc: RX62N interrupt controller (ICUa)

This implementation supported only ICUa. Hardware manual. https://www.renesas.com/us/en/doc/products/mpumcu/doc/rx_family/r01uh0033ej0140_rx62n.pdf Signed-off-by: Yoshinori Sato --- include/hw/intc/rx_icu.h | 49 +++ hw/intc/rx_icu.c | 375

[Qemu-devel] [PATCH v9 02/13] target/rx: TCG helper

Signed-off-by: Yoshinori Sato --- target/rx/helper.h| 31 target/rx/helper.c| 148 target/rx/op_helper.c | 481 ++ 3 files changed, 660 insertions(+) create mode 100644 target/rx/helper.h create mode 100644 target

[Qemu-devel] [PATCH v9 07/13] hw/timer: RX62N internal timer modules

renesas_tmr: 8bit timer modules. renesas_cmt: 16bit compare match timer modules. This part use many renesas's CPU. Hardware manual. https://www.renesas.com/us/en/doc/products/mpumcu/doc/rx_family/r01uh0033ej0140_rx62n.pdf Signed-off-by: Yoshinori Sato --- include/hw/timer/renesas_cmt.h

[Qemu-devel] [PATCH v9 03/13] target/rx: CPU definition

Signed-off-by: Yoshinori Sato --- target/rx/cpu-qom.h | 52 target/rx/cpu.h | 196 ++ target/rx/cpu.c | 222 3 files changed, 470 insertions(+) create mode 100644 target/rx/cpu

[Qemu-devel] [PATCH v9 04/13] target/rx: RX disassembler

Signed-off-by: Yoshinori Sato --- include/disas/dis-asm.h |5 + target/rx/disas.c | 1480 +++ 2 files changed, 1485 insertions(+) create mode 100644 target/rx/disas.c diff --git a/include/disas/dis-asm.h b/include/disas/dis-asm.h index

[Qemu-devel] [PATCH v9 11/13] MAINTAINERS: Add RX

Signed-off-by: Yoshinori Sato --- MAINTAINERS | 19 +++ 1 file changed, 19 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 7dd71e0a2d..e9430b6c0b 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -272,6 +272,13 @@ F: include/hw/riscv/ F: linux-user/host/riscv32/ F

[Qemu-devel] [PATCH v9 01/13] target/rx: TCG translation

This part only supported RXv1 instructions. Instruction manual. https://www.renesas.com/us/en/doc/products/mpumcu/doc/rx_family/r01us0032ej0120_rxsm.pdf Signed-off-by: Yoshinori Sato --- target/rx/translate.c | 2432 target/rx/insns.decode

[Qemu-devel] [PATCH v9 09/13] hw/rx: RX Target hardware definition

rx62n - RX62N cpu. rxqemu - QEMU virtual target. Signed-off-by: Yoshinori Sato --- include/hw/rx/rx.h| 7 ++ include/hw/rx/rx62n.h | 54 hw/rx/rx62n.c | 240 ++ hw/rx/rxqemu.c| 100 + hw/rx

[Qemu-devel] [PATCH v10 05/13] target/rx: Miscellaneous files

Signed-off-by: Yoshinori Sato --- target/rx/gdbstub.c | 112 target/rx/monitor.c | 38 target/rx/Makefile.objs | 12 ++ 3 files changed, 162 insertions(+) create mode 100644 target/rx/gdbstub.c create mode 100644

[Qemu-devel] [PATCH v10 11/13] MAINTAINERS: Add RX

Signed-off-by: Yoshinori Sato --- MAINTAINERS | 19 +++ 1 file changed, 19 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 66ddbda9c9..1599eb6a72 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -272,6 +272,13 @@ F: include/hw/riscv/ F: linux-user/host/riscv32/ F

[Qemu-devel] [PATCH v10 10/13] Add rx-softmmu

Signed-off-by: Yoshinori Sato --- configure | 8 default-configs/rx-softmmu.mak | 7 +++ include/sysemu/arch_init.h | 1 + arch_init.c| 2 ++ hw/Kconfig | 1 + 5 files changed, 19 insertions(+) create mode 100644

[Qemu-devel] [PATCH v10 03/13] target/rx: CPU definition

Signed-off-by: Yoshinori Sato --- target/rx/cpu-qom.h | 52 target/rx/cpu.h | 196 ++ target/rx/cpu.c | 222 3 files changed, 470 insertions(+) create mode 100644 target/rx/cpu

[Qemu-devel] [PATCH v10 12/13] hw/registerfields.h: Add 8bit and 16bit register macros.

Some RX peripheral using 8bit and 16bit registers. Added 8bit and 16bit APIs. Signed-off-by: Yoshinori Sato --- include/hw/registerfields.h | 32 +++- 1 file changed, 31 insertions(+), 1 deletion(-) diff --git a/include/hw/registerfields.h b/include/hw

[Qemu-devel] [PATCH v10 00/13] Add RX archtecture support

/dl/rx-qemu.dtb (DeviceTree) starting $ qemu-system-rx -kernel zImage -dtb rx-qemu.dtb -append "earlycon" Changes for v9. - Fix "mov.l dsp5[rs],rd". Yoshinori Sato (13): target/rx: TCG translation target/rx: TCG helper target/rx: CPU definition target/rx: RX disa

[Qemu-devel] [PATCH v10 06/13] hw/intc: RX62N interrupt controller (ICUa)

This implementation supported only ICUa. Hardware manual. https://www.renesas.com/us/en/doc/products/mpumcu/doc/rx_family/r01uh0033ej0140_rx62n.pdf Signed-off-by: Yoshinori Sato --- include/hw/intc/rx_icu.h | 49 +++ hw/intc/rx_icu.c | 375

[Qemu-devel] [PATCH v10 08/13] hw/char: RX62N serial communication interface (SCI)

This module supported only non FIFO type. Hardware manual. https://www.renesas.com/us/en/doc/products/mpumcu/doc/rx_family/r01uh0033ej0140_rx62n.pdf Signed-off-by: Yoshinori Sato --- include/hw/char/renesas_sci.h | 45 ++ hw/char/renesas_sci.c | 340

[Qemu-devel] [PATCH v10 02/13] target/rx: TCG helper

Signed-off-by: Yoshinori Sato --- target/rx/helper.h| 31 target/rx/helper.c| 148 target/rx/op_helper.c | 481 ++ 3 files changed, 660 insertions(+) create mode 100644 target/rx/helper.h create mode 100644 target

[Qemu-devel] [PATCH v10 13/13] qemu/bitops.h: Add extract8 and extract16

Signed-off-by: Yoshinori Sato --- include/qemu/bitops.h | 38 ++ 1 file changed, 38 insertions(+) diff --git a/include/qemu/bitops.h b/include/qemu/bitops.h index 3f0926cf40..0dfd81efb2 100644 --- a/include/qemu/bitops.h +++ b/include/qemu/bitops.h @@ -301,6

[Qemu-devel] [PATCH v10 07/13] hw/timer: RX62N internal timer modules

renesas_tmr: 8bit timer modules. renesas_cmt: 16bit compare match timer modules. This part use many renesas's CPU. Hardware manual. https://www.renesas.com/us/en/doc/products/mpumcu/doc/rx_family/r01uh0033ej0140_rx62n.pdf Signed-off-by: Yoshinori Sato --- include/hw/timer/renesas_cmt.h

[Qemu-devel] [PATCH v10 09/13] hw/rx: RX Target hardware definition

rx62n - RX62N cpu. rxqemu - QEMU virtual target. Signed-off-by: Yoshinori Sato --- include/hw/rx/rx.h| 7 ++ include/hw/rx/rx62n.h | 54 hw/rx/rx62n.c | 240 ++ hw/rx/rxqemu.c| 100 + hw/rx

[Qemu-devel] [PATCH v10 04/13] target/rx: RX disassembler

Signed-off-by: Yoshinori Sato --- include/disas/dis-asm.h |5 + target/rx/disas.c | 1480 +++ 2 files changed, 1485 insertions(+) create mode 100644 target/rx/disas.c diff --git a/include/disas/dis-asm.h b/include/disas/dis-asm.h index

[Qemu-devel] [PATCH v10 01/13] target/rx: TCG translation

This part only supported RXv1 instructions. Instruction manual. https://www.renesas.com/us/en/doc/products/mpumcu/doc/rx_family/r01us0032ej0120_rxsm.pdf Signed-off-by: Yoshinori Sato --- target/rx/translate.c | 2432 target/rx/insns.decode

Re: [Qemu-devel] [PATCH v10 08/13] hw/char: RX62N serial communication interface (SCI)

On Thu, 09 May 2019 01:16:58 +0900, Philippe Mathieu-Daudé wrote: > > On 5/8/19 4:56 PM, Yoshinori Sato wrote: > > This module supported only non FIFO type. > > Hardware manual. > > https://www.renesas.com/us/en/doc/products/mpumcu/doc/rx_family/r01uh0033ej0140_rx62n.pd

Re: [Qemu-devel] [PATCH v10 06/13] hw/intc: RX62N interrupt controller (ICUa)

On Thu, 09 May 2019 01:27:40 +0900, Philippe Mathieu-Daudé wrote: > > On 5/8/19 4:56 PM, Yoshinori Sato wrote: > > This implementation supported only ICUa. > > Hardware manual. > > https://www.renesas.com/us/en/doc/products/mpumcu/doc/rx_family/r01uh0033ej0140_rx62n.pd

[Qemu-devel] [PATCH v11 12/12] MAINTAINERS: Add RX

From: Yoshinori Sato Signed-off-by: Yoshinori Sato Signed-off-by: Yoshinori Sato --- MAINTAINERS | 19 +++ 1 file changed, 19 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 66ddbda9c9..1599eb6a72 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -272,6 +272,13 @@ F

[Qemu-devel] [PATCH v11 00/12] Add RX archtecture support

-qemu.dtb -append "earlycon" Changes for v10. - Fix build error for 32bit system. - Use "object_initialize_child" in create device instance. - Remove unused headers. - Avoid some magic number. - Clean up Kconfig symbols. Yoshinori Sato (12): target/rx: TCG translation t

[Qemu-devel] [PATCH v11 04/12] target/rx: RX disassembler

From: Yoshinori Sato Signed-off-by: Yoshinori Sato Signed-off-by: Yoshinori Sato --- include/disas/dis-asm.h |5 + target/rx/disas.c | 1480 +++ 2 files changed, 1485 insertions(+) create mode 100644 target/rx/disas.c diff --git a

[Qemu-devel] [PATCH v11 09/12] hw/registerfields.h: Add 8bit and 16bit register macros.

From: Yoshinori Sato Some RX peripheral using 8bit and 16bit registers. Added 8bit and 16bit APIs. Signed-off-by: Yoshinori Sato Signed-off-by: Yoshinori Sato --- include/hw/registerfields.h | 32 +++- 1 file changed, 31 insertions(+), 1 deletion(-) diff --git a

[Qemu-devel] [PATCH v11 08/12] hw/rx: RX Target hardware definition

From: Yoshinori Sato rx62n - RX62N cpu. rx-virt - RX QEMU virtual target. Signed-off-by: Yoshinori Sato Signed-off-by: Yoshinori Sato --- hw/rx/Kconfig | 14 +++ hw/rx/Makefile.objs | 2 + hw/rx/rx-virt.c | 105 ++ hw/rx/rx62n.c | 238

[Qemu-devel] [PATCH v11 11/12] Add rx-softmmu

From: Yoshinori Sato Signed-off-by: Yoshinori Sato Signed-off-by: Yoshinori Sato --- arch_init.c| 2 ++ configure | 8 default-configs/rx-softmmu.mak | 3 +++ hw/Kconfig | 1 + include/sysemu/arch_init.h | 1 + 5 files

[Qemu-devel] [PATCH v11 10/12] qemu/bitops.h: Add extract8 and extract16

From: Yoshinori Sato Signed-off-by: Yoshinori Sato Signed-off-by: Yoshinori Sato --- include/qemu/bitops.h | 38 ++ 1 file changed, 38 insertions(+) diff --git a/include/qemu/bitops.h b/include/qemu/bitops.h index 3f0926cf40..764f9d1ea0 100644 --- a

[Qemu-devel] [PATCH v11 05/12] hw/intc: RX62N interrupt controller (ICUa)

From: Yoshinori Sato This implementation supported only ICUa. Hardware manual. https://www.renesas.com/us/en/doc/products/mpumcu/doc/rx_family/r01uh0033ej0140_rx62n.pdf Signed-off-by: Yoshinori Sato Signed-off-by: Yoshinori Sato --- hw/intc/Kconfig | 3 + hw/intc/Makefile.objs

[Qemu-devel] [PATCH v11 03/12] target/rx: CPU definition

From: Yoshinori Sato Signed-off-by: Yoshinori Sato Signed-off-by: Yoshinori Sato --- target/rx/cpu.c | 222 ++ target/rx/cpu.h | 227 target/rx/gdbstub.c | 112

[Qemu-devel] [PATCH v11 07/12] hw/char: RX62N serial communication interface (SCI)

From: Yoshinori Sato This module supported only non FIFO type. Hardware manual. https://www.renesas.com/us/en/doc/products/mpumcu/doc/rx_family/r01uh0033ej0140_rx62n.pdf Signed-off-by: Yoshinori Sato Signed-off-by: Yoshinori Sato --- hw/char/Kconfig | 3 + hw/char

[Qemu-devel] [PATCH v11 06/12] hw/timer: RX62N internal timer modules

From: Yoshinori Sato renesas_tmr: 8bit timer modules. renesas_cmt: 16bit compare match timer modules. This part use many renesas's CPU. Hardware manual. https://www.renesas.com/us/en/doc/products/mpumcu/doc/rx_family/r01uh0033ej0140_rx62n.pdf Signed-off-by: Yoshinori Sato Signed-o

[Qemu-devel] [PATCH v11 02/12] target/rx: TCG helper

From: Yoshinori Sato Signed-off-by: Yoshinori Sato Signed-off-by: Yoshinori Sato --- target/rx/helper.c| 148 target/rx/helper.h| 31 target/rx/op_helper.c | 481 ++ 3 files changed, 660 insertions(+) create mode

[Qemu-devel] [PATCH v11 01/12] target/rx: TCG translation

From: Yoshinori Sato This part only supported RXv1 instructions. Instruction manual. https://www.renesas.com/us/en/doc/products/mpumcu/doc/rx_family/r01us0032ej0120_rxsm.pdf Signed-off-by: Yoshinori Sato Signed-off-by: Yoshinori Sato --- target/rx/Makefile.objs | 12 + target/rx

Re: [Qemu-devel] [PATCH v11 00/12] Add RX archtecture support

Oh. Sorry. I fount one other problem. I will fix it and re-send later. 2019年5月14日(火) 2:26 Philippe Mathieu-Daudé : > > Hi Yoshinori, > > On 5/13/19 7:25 AM, Yoshinori Sato wrote: > > Hello. > > This patch series is added Renesas RX target emulation. > > > > F

[Qemu-devel] [PATCH v12 10/12] hw/registerfields.h: Add 8bit and 16bit register macros.

Some RX peripheral using 8bit and 16bit registers. Added 8bit and 16bit APIs. Signed-off-by: Yoshinori Sato --- include/hw/registerfields.h | 32 +++- 1 file changed, 31 insertions(+), 1 deletion(-) diff --git a/include/hw/registerfields.h b/include/hw

[Qemu-devel] [PATCH v12 12/12] MAINTAINERS: Add RX

Signed-off-by: Yoshinori Sato --- MAINTAINERS | 19 +++ 1 file changed, 19 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index a73a61a546..ef6a02702e 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -272,6 +272,13 @@ F: include/hw/riscv/ F: linux-user/host/riscv32/ F

[Qemu-devel] [PATCH v12 06/12] hw/timer: RX62N internal timer modules

renesas_tmr: 8bit timer modules. renesas_cmt: 16bit compare match timer modules. This part use many renesas's CPU. Hardware manual. https://www.renesas.com/us/en/doc/products/mpumcu/doc/rx_family/r01uh0033ej0140_rx62n.pdf Signed-off-by: Yoshinori Sato --- include/hw/timer/renesas_cmt.h

[Qemu-devel] [PATCH v12 09/12] Add rx-softmmu

Signed-off-by: Yoshinori Sato --- configure | 8 default-configs/rx-softmmu.mak | 3 +++ include/sysemu/arch_init.h | 1 + arch_init.c| 2 ++ hw/Kconfig | 1 + 5 files changed, 15 insertions(+) create mode 100644 default

[Qemu-devel] [PATCH v12 00/12] Add RX archtecture support

-dtb rx-qemu.dtb -append "earlycon" Changes for v11. - Fix ROM address. Yoshinori Sato (12): target/rx: TCG translation target/rx: TCG helper target/rx: CPU definition target/rx: RX disassembler hw/intc: RX62N interrupt controller (ICUa) hw/timer: RX62N internal timer modules

[Qemu-devel] [PATCH v12 03/12] target/rx: CPU definition

Signed-off-by: Yoshinori Sato --- target/rx/cpu.h | 227 target/rx/cpu.c | 222 ++ target/rx/gdbstub.c | 112 ++ target/rx/monitor.c | 38 + 4 files

[Qemu-devel] [PATCH v12 01/12] target/rx: TCG translation

This part only supported RXv1 instructions. Instruction manual. https://www.renesas.com/us/en/doc/products/mpumcu/doc/rx_family/r01us0032ej0120_rxsm.pdf Signed-off-by: Yoshinori Sato --- target/rx/translate.c | 2432 +++ target/rx/Makefile.objs

[Qemu-devel] [PATCH v12 05/12] hw/intc: RX62N interrupt controller (ICUa)

This implementation supported only ICUa. Hardware manual. https://www.renesas.com/us/en/doc/products/mpumcu/doc/rx_family/r01uh0033ej0140_rx62n.pdf Signed-off-by: Yoshinori Sato --- include/hw/intc/rx_icu.h | 57 +++ hw/intc/rx_icu.c | 376

[Qemu-devel] [PATCH v12 11/12] qemu/bitops.h: Add extract8 and extract16

Signed-off-by: Yoshinori Sato --- include/qemu/bitops.h | 38 ++ 1 file changed, 38 insertions(+) diff --git a/include/qemu/bitops.h b/include/qemu/bitops.h index 3f0926cf40..764f9d1ea0 100644 --- a/include/qemu/bitops.h +++ b/include/qemu/bitops.h @@ -301,6

[Qemu-devel] [PATCH v12 07/12] hw/char: RX62N serial communication interface (SCI)

This module supported only non FIFO type. Hardware manual. https://www.renesas.com/us/en/doc/products/mpumcu/doc/rx_family/r01uh0033ej0140_rx62n.pdf Signed-off-by: Yoshinori Sato --- include/hw/char/renesas_sci.h | 45 ++ hw/char/renesas_sci.c | 340

[Qemu-devel] [PATCH v12 02/12] target/rx: TCG helper

Signed-off-by: Yoshinori Sato --- target/rx/helper.h| 31 target/rx/helper.c| 148 target/rx/op_helper.c | 481 ++ 3 files changed, 660 insertions(+) create mode 100644 target/rx/helper.h create mode 100644 target

[Qemu-devel] [PATCH v17 12/24] target/rx: Add RX to SysEmuTarget

From: Richard Henderson Fixes check-qtest-rx: tests/qmp-cmd-test Signed-off-by: Richard Henderson Signed-off-by: Yoshinori Sato --- qapi/common.json | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/qapi/common.json b/qapi/common.json index 99d313ef3b..d0fc931159 100644

[Qemu-devel] [PATCH v17 20/24] target/rx: Use prt_ldmi for XCHG_mr disassembly

From: Richard Henderson Note that the ld == 3 case handled by prt_ldmi is decoded as XCHG_rr and cannot appear here. Reviewed-by: Yoshinori Sato Signed-off-by: Richard Henderson Signed-off-by: Yoshinori Sato --- target/rx/disas.c | 8 +--- 1 file changed, 1 insertion(+), 7 deletions

[Qemu-devel] [PATCH v17 14/24] tests: Add rx to machine-none-test.c

From: Richard Henderson Fixes check-qtest-rx: tests/machine-none-test. Signed-off-by: Richard Henderson Signed-off-by: Yoshinori Sato --- tests/machine-none-test.c | 1 + 1 file changed, 1 insertion(+) diff --git a/tests/machine-none-test.c b/tests/machine-none-test.c index 4c6d470798

[Qemu-devel] [PATCH v17 13/24] target/rx: Fix cpu types and names

e. Rename the base class to "rx-cpu" and make it abstract. This matches what we do for most other targets. Create a new concrete cpu with the name "rx62n-rx-cpu". Signed-off-by: Richard Henderson Signed-off-by: Yoshinori Sato --- target/rx/cpu.h | 12 ++-- hw/rx/rx

[Qemu-devel] [PATCH v17 23/24] target/rx: Dump bytes for each insn during disassembly

From: Richard Henderson There are so many different forms of each RX instruction that it will be very useful to be able to look at the bytes to see on which path a bug may lie. Reviewed-by: Yoshinori Sato Signed-off-by: Richard Henderson Signed-off-by: Yoshinori Sato --- target/rx/disas.c

[Qemu-devel] [PATCH v17 02/24] target/rx: TCG helper

Signed-off-by: Yoshinori Sato Reviewed-by: Richard Henderson Message-Id: <20190516055244.95559-3-ys...@users.sourceforge.jp> Signed-off-by: Richard Henderson --- target/rx/helper.h| 31 target/rx/helper.c| 148 target/rx/op_helper.c

[Qemu-devel] [PATCH v17 11/24] target/rx: Convert to CPUClass::tlb_fill

From: Richard Henderson The interface for tlb_fill has changed very recently. Move the function into cpu.c so that it may be static while assigning to the CPUClass methods. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson Signed-off-by: Yoshinori Sato --- target/rx/cpu.c

[Qemu-devel] [PATCH v17 09/24] qemu/bitops.h: Add extract8 and extract16

Signed-off-by: Yoshinori Sato Reviewed-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daudé Message-Id: <20190516055244.95559-12-ys...@users.sourceforge.jp> Signed-off-by: Richard Henderson --- include/qemu/bitops.h | 38 ++ 1 file chang

[Qemu-devel] [PATCH v17 17/24] MAINTAINERS: Add RX

Signed-off-by: Yoshinori Sato Reviewed-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daudé Message-Id: <20190516055244.95559-13-ys...@users.sourceforge.jp> Signed-off-by: Richard Henderson --- MAINTAINERS | 19 +++ 1 file changed, 19 insertions(+) diff -

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