A parenthesis placed inappropriately caused displaying
wrong memory size bigger than 4GB.
Signed-off-by: Yongbok Kim
---
hw/mips/mips_malta.c |2 +-
hw/mips/mips_r4k.c|2 +-
hw/ppc/mac_oldworld.c |2 +-
3 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/hw/mips
of 256MiB memory to a kernel.
This allows kernels which do not support such access to boot on systems
with more than 256MiB of RAM. It is also the behaviour assumed by Linux.
QEMUs small generated bootloader is modified to provide this behaviour.
Signed-off-by: Paul Burton
Signed-off-by: Yong
dreas Färber
Cc: Yongbok Kim; qemu-devel@nongnu.org; Leon Alrae; aurel...@aurel32.net;
critian.c...@imgtec.com
Subject: Re: [Qemu-devel] [PATCH] hw: fix to display correct memory size
On 23.08.2013, at 17:20, Andreas Färber wrote:
> Am 23.08.2013 16:57, schrieb Yongbok Kim:
>> A pare
5 has type ‘hwaddr’ [-Werror=format]
Fix the *physical (hwaddr) formatting by using "%"HWADDR_PRIx instead of
TARGET_FMT_lx.
Signed-off-by: James Hogan
Cc: Aurelien Jarno
Signed-off-by: Yongbok Kim
---
target-mips/helper.c |2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
There is a block of code that modifies CP0_Status_rw_bitmask.CP0St_FR
bit to read-writable in the same function.
So effectively in case of MIPS64 R6 the bit is now R/W which shouldn't be.
You need to modify or merge the code.
# if defined(TARGET_MIPS64)
/* For MIPS64, init FR bit to 1 if FPU u
Correction: it is not updating the bit but checking the bit.
Reviewed-by: Yongbok Kim
On 02/10/14 11:21, Yongbok Kim wrote:
> There is a block of code that modifies CP0_Status_rw_bitmask.CP0St_FR
> bit to read-writable in the same function.
> So effectively in case of MIPS64 R6 the b
Hi,
Overall looking good but has issues with not freeing tcg_temps and some
style problem which
failed with the checkpatch.pl script.
Otherwise
Reviewed-by: Yongbok Kim
Regards,
Yongbok
On 27/06/2014 16:22, Leon Alrae wrote:
In terms of encoding MIPS32R6 MIN.fmt, MAX.fmt, MINA.fmt
34Kf core does support DSP ASE.
CP0_Config3 configuration for 34Kf and description are wrong.
Please refer to MIPS32(R) 34Kf(TM) Processor Core Datasheet
Signed-off-by: Yongbok Kim
---
target-mips/translate_init.c |5 ++---
1 files changed, 2 insertions(+), 3 deletions(-)
diff --git a
34Kf core does support DSP ASE.
CP0_Config3 configuration for 34Kf and description are wrong.
Please refer to MIPS32(R) 34Kf(TM) Processor Core Datasheet
Signed-off-by: Yongbok Kim
---
changes from v1:
make status.MX writeable
target-mips/translate_init.c |7 +++
1 files changed, 3
I have just few minor comments.
Reviewed-by: Yongbok Kim
regards,
Yongbok
On 08/10/2014 11:55, Leon Alrae wrote:
Signed-off-by: Leon Alrae
---
v3:
* use sextract32 instead of open coding the bit field extraction
* replace _i64 with _tl in DAHI, DATI and DAUI
* fix misleading LDPC comment
As this point all new R6 instructions is available,
this patch should be good enough to make it able to test especially for
R6 Linux user mode binaries.
Reviewed-by: Yongbok Kim
Regards,
Yongbok
On 08/10/2014 11:55, Leon Alrae wrote:
Signed-off-by: Leon Alrae
---
v3:
* add comment to
Not related code changes are included.
See the comment below.
Other than,
Reviewed-by: Yongbok Kim
Regards,
Yongbok
On 08/07/2014 08:57, Leon Alrae wrote:
KScratch Registers (CP0 Register 31, Selects 2 to 7)
The KScratch registers are read/write registers available for scratch pad
storage
Reviewed-by: Yongbok Kim
On 08/07/2014 08:57, Leon Alrae wrote:
Signed-off-by: Leon Alrae
---
target-mips/helper.c | 21 ++---
1 files changed, 10 insertions(+), 11 deletions(-)
diff --git a/target-mips/helper.c b/target-mips/helper.c
index 8a997e4..9871273 100644
--- a
On 08/07/2014 08:57, Leon Alrae wrote:
In Revision 3 of the architecture, the RI and XI bits were added to the TLB
to enable more secure access of memory pages. These bits (along with the Dirty
bit) allow the implementation of read-only, write-only, no-execute access
policies for mapped pages.
dm{t,f}c0_entrylo{0,1} is also added.
Please reflect it in the title.
I have other minor comments below.
Reviewed-by: Yongbok Kim
Regards,
Yongbok
On 08/07/2014 08:57, Leon Alrae wrote:
PageGrain needs rw bitmask which differs between MIPS architectures.
In pre-R6 if RIXI is supported
Reviewed-by: Yongbok Kim
Regards,
Yongbok
On 08/07/2014 08:57, Leon Alrae wrote:
An Execute-Inhibit exception occurs when the virtual address of an instruction
fetch matches a TLB entry whose XI bit is set. This exception type can only
occur if the XI bit is implemented within the TLB and is
Hi Leon,
As the issues below are all corrected in the PRPL already,
Reviewed-by: Yongbok Kim
Regards,
Yongbok
On 08/07/2014 08:57, Leon Alrae wrote:
For Standard TLB configuration (Config.MT=1):
TLBINV invalidates a set of TLB entries based on ASID. The virtual address is
ignored in the
EHINV bit from TLB also required to be saved/ restored.
Regards,
Yongbok
On 08/07/2014 08:57, Leon Alrae wrote:
Signed-off-by: Leon Alrae
---
target-mips/cpu.h |2 +-
target-mips/machine.c | 14 ++
2 files changed, 15 insertions(+), 1 deletions(-)
diff --git a/targe
Please update message body as it also adds dm{f,t}c0 for config{4,5}.
See the comment below.
Reviewed-by: Yongbok Kim
Regards,
Yongbok
On 14/07/2014 17:19, Leon Alrae wrote:
SDBBP instruction Reserved Instruction control. The purpose of this field is
to restrict availability of SDBBP to
Reviewed-by: Yongbok Kim
Regards,
Yongbok
On 14/07/2014 17:19, Leon Alrae wrote:
Signed-off-by: Leon Alrae
---
target-mips/cpu.h |3 ++-
1 files changed, 2 insertions(+), 1 deletions(-)
diff --git a/target-mips/cpu.h b/target-mips/cpu.h
index a35ab9d..b981ec7 100644
--- a/target-mips
On 14/07/2014 17:19, Leon Alrae wrote:
In Release 6 not all the values are allowed to be written to a register.
If the value is not valid or unsupported then it should stay unchanged.
For pre-R6 the existing behaviour has been changed only for CP0_Index register
as the current implementation doe
On 14/07/2014 17:19, Leon Alrae wrote:
Release 6 limits the number of cases where software can cause UNDEFINED or
UNPREDICTABLE behaviour. In this case, when accessing reserved / unimplemented
CP0 register, writes are ignored and reads return 0.
In pre-R6 the behaviour is not specified, but gene
FLAG_BMASK;
if (!(ctx.hflags & MIPS_HFLAG_M16)) {
ctx.opcode = cpu_ldl_code(env, ctx.pc);
insn_bytes = 4;
@@ -17729,7 +17760,7 @@ gen_intermediate_code_internal(MIPSCPU *cpu,
TranslationBlock *tb,
break;
}
-if (is_delay) {
+if (is_slot) {
gen_branch(&ctx, insn_bytes);
}
ctx.pc += insn_bytes;
Comments on 4155 , 7839 and 15616 are also required changes to indicate
it might be delay or forbidden slot.
Otherwise,
Reviewed-by: Yongbok Kim
Regards,
Yongbok
0PG_RIE),
+.CP0_PageGrain_rw_bitmask = 0,
.CP1_fcr0 = (1 << FCR0_F64) | (1 << FCR0_L) | (1 << FCR0_W) |
(1 << FCR0_D) | (1 << FCR0_S) | (0x00 << FCR0_PRID) |
(0x0 << FCR0_REV),
Reviewed-by: Yongbok Kim
Regards,
Yongbok
Hi,
On 22/10/2014 12:35, James Hogan wrote:
+union wr_t {
+int8_t b[MSA_WRLEN/8];
+int16_t h[MSA_WRLEN/16];
+int32_t w[MSA_WRLEN/32];
+int64_t d[MSA_WRLEN/64];
This is incorrect on a big endian host. The least significant bits of
the lowest indexed element should always alias.
On 24/10/2014 15:16, Leon Alrae wrote:
On 15/10/2014 13:24, Yongbok Kim wrote:
On 08/07/2014 08:57, Leon Alrae wrote:
In Revision 3 of the architecture, the RI and XI bits were added to
the TLB
to enable more secure access of memory pages. These bits (along with
the Dirty
bit) allow the
(tlb->C0 << 3) | (tlb->PFN[0] >> 6);
env->CP0_EntryLo1 = tlb->G | (tlb->V1 << 1) | (tlb->D1 << 2) |
+((target_ulong)tlb->RI1 << CP0EnLo_RI) |
+((target_ulong)tlb->XI1 << CP0EnLo_XI) |
(tlb->C1 << 3) | (tlb->PFN[1] >> 6);
}
Reviewed-by: Yongbok Kim
Regards,
Yongbok
Signed-off-by: Yongbok Kim
---
target-mips/op_helper.c |7 +++
1 files changed, 3 insertions(+), 4 deletions(-)
diff --git a/target-mips/op_helper.c b/target-mips/op_helper.c
index 7cbf4cf..e878442 100644
--- a/target-mips/op_helper.c
+++ b/target-mips/op_helper.c
@@ -90,10 +90,10
.
v2:
* fixes for Leon's and James' comments
* rebased top of R6 patchset
* Code refactored mainly for msa_helper.c
Yongbok Kim (20):
target-mips: add MSA defines and data structure
target-mips: add MSA exceptions
target-mips: remove duplicated mips/ieee mapping function
target-mi
add MSA exceptions
Signed-off-by: Yongbok Kim
---
target-mips/helper.c | 10 ++
1 files changed, 10 insertions(+), 0 deletions(-)
diff --git a/target-mips/helper.c b/target-mips/helper.c
index c92b25c..3a93c20 100644
--- a/target-mips/helper.c
+++ b/target-mips/helper.c
@@ -426,6
add MSA BIT format instructions
Signed-off-by: Yongbok Kim
---
target-mips/helper.h | 13 +++
target-mips/msa_helper.c | 197 ++
target-mips/translate.c | 85
3 files changed, 295 insertions(+), 0 deletions(-)
diff
add MSA opcode enum
Reviewed-by: James Hogan
Reviewed-by: Leon Alrae
Signed-off-by: Yongbok Kim
---
target-mips/translate.c | 245 +++
1 files changed, 245 insertions(+), 0 deletions(-)
diff --git a/target-mips/translate.c b/target-mips
add defines and data structure for MIPS SIMD Architecture
Signed-off-by: Yongbok Kim
---
target-mips/cpu.h | 52 +-
target-mips/mips-defs.h |1 +
target-mips/op_helper.c |1 +
3 files changed, 52 insertions(+), 2 deletions(-)
diff
Signed-off-by: Yongbok Kim
---
target-mips/cpu.h |4
target-mips/gdbstub.c |7 ---
target-mips/op_helper.c |4 ++--
3 files changed, 6 insertions(+), 9 deletions(-)
diff --git a/target-mips/cpu.h b/target-mips/cpu.h
index fb5abda..6d3db79 100644
--- a/target-mips
add MSA 3RF format instructions
Signed-off-by: Yongbok Kim
---
target-mips/helper.h | 42 ++
target-mips/msa_helper.c | 1497 ++
target-mips/translate.c | 162 +
3 files changed, 1701 insertions(+), 0 deletions(-)
diff --git a/target-mips
add msa_reset() and global msa register (d type only)
Signed-off-by: Yongbok Kim
---
target-mips/translate.c | 56 ++
target-mips/translate_init.c | 35 ++
2 files changed, 91 insertions(+), 0 deletions(-)
diff --git a
add MSA branch instructions
Signed-off-by: Yongbok Kim
---
target-mips/translate.c | 333 +++
1 files changed, 219 insertions(+), 114 deletions(-)
diff --git a/target-mips/translate.c b/target-mips/translate.c
index f1160aa..0df86cc 100644
--- a
stop translation as ctc1 instruction can change hflags
Signed-off-by: Yongbok Kim
---
target-mips/translate.c |6 ++
1 files changed, 6 insertions(+), 0 deletions(-)
diff --git a/target-mips/translate.c b/target-mips/translate.c
index 9a8f5c9..b388ba5 100644
--- a/target-mips
disassemble MIPS SIMD Architecture instructions
Signed-off-by: Yongbok Kim
---
disas/mips.c | 716 +-
1 files changed, 714 insertions(+), 2 deletions(-)
diff --git a/disas/mips.c b/disas/mips.c
index 4974bc0..2614c52 100644
--- a/disas
add MSA 3R format instructions
Signed-off-by: Yongbok Kim
---
target-mips/helper.h | 64 +
target-mips/msa_helper.c | 628 ++
target-mips/translate.c | 244 ++
3 files changed, 936 insertions(+), 0 deletions(-)
diff --git
add msa_helper.c
Signed-off-by: Yongbok Kim
---
target-mips/Makefile.objs |2 +-
target-mips/msa_helper.c | 49 +
2 files changed, 50 insertions(+), 1 deletions(-)
create mode 100644 target-mips/msa_helper.c
diff --git a/target-mips
add MSA I8 format instructions
Reviewed-by: James Hogan
Signed-off-by: Yongbok Kim
---
target-mips/helper.h | 10 +
target-mips/msa_helper.c | 67 +++
target-mips/translate.c | 86 -
3 files changed, 161
add MSA VEC/2R format instructions
Signed-off-by: Yongbok Kim
---
target-mips/helper.h | 12
target-mips/msa_helper.c | 140 ++
target-mips/translate.c | 113 +
3 files changed, 265 insertions(+), 0
add MSA I5 format instructions
Signed-off-by: Yongbok Kim
---
target-mips/helper.h | 13
target-mips/msa_helper.c | 142 ++
target-mips/translate.c | 79 +
3 files changed, 234 insertions(+), 0 deletions(-)
diff
add MSA ELM format instructions
Signed-off-by: Yongbok Kim
---
target-mips/helper.h | 10 +++
target-mips/msa_helper.c | 162 ++
target-mips/translate.c | 118 +
3 files changed, 290 insertions(+), 0 deletions
add MSA 2RF format instructions
Signed-off-by: Yongbok Kim
---
target-mips/helper.h | 17 ++
target-mips/msa_helper.c | 579 ++
target-mips/translate.c | 76 ++
3 files changed, 672 insertions(+), 0 deletions(-)
diff --git a/target-mips
add MSA MI10 format instructions
update LSA and DLSA for MSA
Signed-off-by: Yongbok Kim
---
target-mips/helper.h|3 ++
target-mips/op_helper.c | 77 +++
target-mips/translate.c | 50 ++-
3 files changed, 129
add MSA support to mips32r5-generic core definition
Signed-off-by: Yongbok Kim
---
target-mips/translate_init.c |4 ++--
1 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/target-mips/translate_init.c b/target-mips/translate_init.c
index 8fb8bf8..0b4b597 100644
--- a/target-mips
lt; 22);
break;
case 31:
-if (arg1 & 0x007c)
-return;
-env->active_fpu.fcr31 = arg1;
+if (env->insn_flags & ISA_MIPS32R6) {
+uint32_t mask = 0xfefc;
+env->active_fpu.fcr31 = (arg1 & ~mask) |
+(env->active_fpu.fcr31 & mask);
+} else if (!(arg1 & 0x007c)) {
+env->active_fpu.fcr31 = arg1;
+}
break;
default:
return;
Reviewed-by: Yongbok Kim
Regards,
Yongbok
ediate_code_internal(MIPSCPU *cpu, TranslationBlock *tb,
ctx.kscrexist = (env->CP0_Config4 >> CP0C4_KScrExist) & 0xff;
ctx.rxi = (env->CP0_Config3 >> CP0C3_RXI) & 1;
ctx.ie = (env->CP0_Config4 >> CP0C4_IE) & 3;
+ctx.bi = (env->CP0_Config3 >> CP0C3_BI) & 1;
+ctx.bp = (env->CP0_Config3 >> CP0C3_BP) & 1;
/* Restore delay slot state from the tb context. */
ctx.hflags = (uint32_t)tb->flags; /* FIXME: maybe use 64 bits here? */
ctx.ulri = env->CP0_Config3 & (1 << CP0C3_ULRI);
otherwise,
Reviewed-by: Yongbok Kim
Regards,
Yongbok
amp;env->tlb->mmu.r4k.tlb[i].PFN[1]);
}
@@ -301,6 +318,13 @@ int cpu_load(QEMUFile *f, void *opaque, int version_id)
qemu_get_sbe32s(f, &env->CP0_DataHi);
qemu_get_betls(f, &env->CP0_ErrorEPC);
qemu_get_sbe32s(f, &env->CP0_DESAVE);
+if (version_id >= 5) {
+qemu_get_be32s(f, &env->CP0_BadInstr);
+qemu_get_be32s(f, &env->CP0_BadInstrP);
+for (i = 0; i < MIPS_KSCRATCH_NUM; i++) {
+qemu_get_betls(f, &env->CP0_KScratch[i]);
+}
+}
/* Load inactive TC state */
for (i = 0; i < MIPS_SHADOW_SET_MAX; i++) {
Reviewed-by: Yongbok Kim
Regards,
Yongbok
been updated yet.
v3:
* fixes for mixed declarations and code
* remove duplicated code
* change data format for immediate values
v2:
* fixes for Leon's and James' comments
* rebased top of R6 patchset
* Code refactored mainly for msa_helper.c
Yongbok Kim (19):
target-mips: add MSA d
Remove the duplicated ieee_rm in gdbstub.c.
Make the other ieee_rm and ieee_ex_to_mips available to other files.
Reviewed-by: James Hogan
Reviewed-by: Leon Alrae
Signed-off-by: Yongbok Kim
---
target-mips/cpu.h |4
target-mips/gdbstub.c |7 ---
target-mips/op_helper.c
add MSA exceptions
Reviewed-by: James Hogan
Signed-off-by: Yongbok Kim
---
target-mips/helper.c | 10 ++
1 files changed, 10 insertions(+), 0 deletions(-)
diff --git a/target-mips/helper.c b/target-mips/helper.c
index c92b25c..3a93c20 100644
--- a/target-mips/helper.c
+++ b/target
add msa_helper.c
Reviewed-by: James Hogan
Reviewed-by: Leon Alrae
Signed-off-by: Yongbok Kim
---
target-mips/Makefile.objs |2 +-
target-mips/msa_helper.c | 49 +
2 files changed, 50 insertions(+), 1 deletions(-)
create mode 100644 target
add defines and data structure for MIPS SIMD Architecture
Reviewed-by: James Hogan
Signed-off-by: Yongbok Kim
---
target-mips/cpu.h | 52 +-
target-mips/mips-defs.h |1 +
target-mips/op_helper.c |1 +
3 files changed, 52 insertions
add msa_reset() and global msa register (d type only)
Reviewed-by: James Hogan
Signed-off-by: Yongbok Kim
---
target-mips/translate.c | 56 ++
target-mips/translate_init.c | 35 ++
2 files changed, 91 insertions(+), 0
stop translation as ctc1 instruction can change hflags
Reviewed-by: James Hogan
Signed-off-by: Yongbok Kim
---
target-mips/translate.c |6 ++
1 files changed, 6 insertions(+), 0 deletions(-)
diff --git a/target-mips/translate.c b/target-mips/translate.c
index 9a8f5c9..b388ba5 100644
add MSA branch instructions
Reviewed-by: James Hogan
Signed-off-by: Yongbok Kim
---
target-mips/translate.c | 334 +++
1 files changed, 220 insertions(+), 114 deletions(-)
diff --git a/target-mips/translate.c b/target-mips/translate.c
index baa1826
add MSA opcode enum
Reviewed-by: James Hogan
Reviewed-by: Leon Alrae
Signed-off-by: Yongbok Kim
---
target-mips/translate.c | 245 +++
1 files changed, 245 insertions(+), 0 deletions(-)
diff --git a/target-mips/translate.c b/target-mips
add MSA I5 format instructions
Signed-off-by: Yongbok Kim
---
target-mips/helper.h | 14 +
target-mips/msa_helper.c | 141 ++
target-mips/translate.c | 77 +
3 files changed, 232 insertions(+), 0 deletions
add MSA 3RF format instructions
Signed-off-by: Yongbok Kim
---
target-mips/helper.h | 42 ++
target-mips/msa_helper.c | 1497 ++
target-mips/translate.c | 163 +
3 files changed, 1702 insertions(+), 0 deletions(-)
diff --git a/target-mips
add MSA MI10 format instructions
update LSA and DLSA for MSA
add 16, 64 bit load and store
Signed-off-by: Yongbok Kim
---
target-mips/helper.h|4 ++
target-mips/op_helper.c | 84 --
target-mips/translate.c | 49
add MSA I8 format instructions
Reviewed-by: James Hogan
Signed-off-by: Yongbok Kim
---
target-mips/helper.h | 10 ++
target-mips/msa_helper.c | 67 +
target-mips/translate.c | 82 -
3 files changed
add MSA BIT format instructions
Reviewed-by: Leon Alrae
Signed-off-by: Yongbok Kim
---
target-mips/helper.h | 13 +++
target-mips/msa_helper.c | 197 ++
target-mips/translate.c | 88
3 files changed, 298 insertions
add MSA support to mips32r5-generic core definition
Signed-off-by: Yongbok Kim
---
target-mips/translate_init.c |4 ++--
1 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/target-mips/translate_init.c b/target-mips/translate_init.c
index 8fb8bf8..0b4b597 100644
--- a/target-mips
add MSA 3R format instructions
Signed-off-by: Yongbok Kim
---
target-mips/helper.h | 64 +
target-mips/msa_helper.c | 656 ++
target-mips/translate.c | 242 +
3 files changed, 962 insertions(+), 0 deletions(-)
diff --git
disassemble MIPS SIMD Architecture instructions
Signed-off-by: Yongbok Kim
---
disas/mips.c | 716 +-
1 files changed, 714 insertions(+), 2 deletions(-)
diff --git a/disas/mips.c b/disas/mips.c
index 4974bc0..2614c52 100644
--- a/disas
add MSA ELM format instructions
Signed-off-by: Yongbok Kim
---
target-mips/helper.h |9 +++
target-mips/msa_helper.c | 162 ++
target-mips/translate.c | 118 +
3 files changed, 289 insertions(+), 0 deletions
add MSA VEC/2R format instructions
Signed-off-by: Yongbok Kim
---
target-mips/helper.h | 12
target-mips/msa_helper.c | 140 ++
target-mips/translate.c | 113 +
3 files changed, 265 insertions(+), 0
add MSA 2RF format instructions
Signed-off-by: Yongbok Kim
---
target-mips/helper.h | 17 ++
target-mips/msa_helper.c | 528 ++
target-mips/translate.c | 74 +++
3 files changed, 619 insertions(+), 0 deletions(-)
diff --git a/target
Reviewed-by: Yongbok Kim
Note that there is a microMIPS version of SYNCI, it would be even better if you
could update it as well.
Best Regards,
Yongbok Kim
-Original Message-
From: qemu-devel-bounces+yongbok.kim=imgtec@nongnu.org
[mailto:qemu-devel-bounces+yongbok.kim=imgtec
Tested-by: Yongbok Kim
-Original Message-
From: qemu-devel-bounces+yongbok.kim=imgtec@nongnu.org
[mailto:qemu-devel-bounces+yongbok.kim=imgtec@nongnu.org] On Behalf Of
Dongxue Zhang
Sent: Tuesday, July 29, 2014 2:48 PM
To: qemu-devel@nongnu.org
Cc: peter.mayd...@linaro.org
add defines and data structure for MIPS SIMD Architecture
Signed-off-by: Yongbok Kim
---
target-mips/cpu.h | 79 +--
target-mips/mips-defs.h |1 +
target-mips/op_helper.c |1 +
3 files changed, 78 insertions(+), 3 deletions(-)
diff
move commonly used functions to cpu.h
Signed-off-by: Yongbok Kim
---
target-mips/cpu.h | 72 +++
target-mips/gdbstub.c |7
target-mips/op_helper.c | 60 +-
3 files changed, 74 insertions(+), 65
/366146/
The MSA floating-point is compliant with the IEEE Standard for Floating-Point
Arithmetic 754TM-2008. However this patchset is not set up with the IEEE-2008
option as QEMU softfloat for MIPS has not been updated yet.
Yongbok Kim (20):
target-mips: add MSA defines and data structure
disassemble MIPS SIMD Architecture instructions
Signed-off-by: Yongbok Kim
---
disas/mips.c | 721 +-
1 files changed, 719 insertions(+), 2 deletions(-)
diff --git a/disas/mips.c b/disas/mips.c
index 2106b57..65781f7 100644
--- a/disas
stop translation as ctc1 instruction can change hflags
Signed-off-by: Yongbok Kim
---
target-mips/translate.c |6 ++
1 files changed, 6 insertions(+), 0 deletions(-)
diff --git a/target-mips/translate.c b/target-mips/translate.c
index 994e85d..cccbc44 100644
--- a/target-mips
add 8, 16, 32, 64 bits load and store
Signed-off-by: Yongbok Kim
---
target-mips/cpu.h |8
1 files changed, 8 insertions(+), 0 deletions(-)
diff --git a/target-mips/cpu.h b/target-mips/cpu.h
index 68ce383..51d1c88 100644
--- a/target-mips/cpu.h
+++ b/target-mips/cpu.h
@@ -896,6
add MSA I8 format instructions
Signed-off-by: Yongbok Kim
---
target-mips/helper.h | 11
target-mips/msa_helper.c | 140 ++
target-mips/translate.c | 94 ++-
3 files changed, 243 insertions(+), 2 deletions
add MSA exceptions
Signed-off-by: Yongbok Kim
---
target-mips/helper.c |8
1 files changed, 8 insertions(+), 0 deletions(-)
diff --git a/target-mips/helper.c b/target-mips/helper.c
index 8a997e4..ed796ff 100644
--- a/target-mips/helper.c
+++ b/target-mips/helper.c
@@ -396,6 +396,8
add msa_helper.c
Signed-off-by: Yongbok Kim
---
target-mips/Makefile.objs |2 +-
target-mips/msa_helper.c | 196 +
2 files changed, 197 insertions(+), 1 deletions(-)
create mode 100644 target-mips/msa_helper.c
diff --git a/target-mips
add MSA I5 format instructions:
Signed-off-by: Yongbok Kim
---
target-mips/helper.h | 12 ++
target-mips/msa_helper.c | 273 ++
target-mips/translate.c | 91 +++
3 files changed, 376 insertions(+), 0 deletions(-)
diff --git a
add MSA support to mips32r5-generic core definition
Signed-off-by: Yongbok Kim
---
target-mips/translate_init.c |4 ++--
1 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/target-mips/translate_init.c b/target-mips/translate_init.c
index 9e0f67b..034a3f8 100644
--- a/target-mips
add msa_reset() and global msa register (d type only)
Signed-off-by: Yongbok Kim
---
target-mips/translate.c | 74 ++
target-mips/translate_init.c | 45 +
2 files changed, 119 insertions(+), 0 deletions(-)
diff --git a
add MSA BIT format instructions
Signed-off-by: Yongbok Kim
---
target-mips/helper.h | 12 ++
target-mips/msa_helper.c | 292 ++
target-mips/translate.c | 100
3 files changed, 404 insertions(+), 0 deletions(-)
diff --git a
add MSA branch instructions
Signed-off-by: Yongbok Kim
---
target-mips/translate.c | 107 ++-
1 files changed, 105 insertions(+), 2 deletions(-)
diff --git a/target-mips/translate.c b/target-mips/translate.c
index b8dbbdc..0bfbcfe 100644
--- a
add MSA ELM format instructions
Signed-off-by: Yongbok Kim
---
target-mips/helper.h |9 ++
target-mips/msa_helper.c | 239 ++
target-mips/translate.c | 136 ++
3 files changed, 384 insertions(+), 0 deletions(-)
diff
add MSA opcode enum
Signed-off-by: Yongbok Kim
---
target-mips/translate.c | 248 +++
1 files changed, 248 insertions(+), 0 deletions(-)
diff --git a/target-mips/translate.c b/target-mips/translate.c
index cccbc44..6b4a82c 100644
--- a/target-mips
add MSA VEC/2R format instructions
Signed-off-by: Yongbok Kim
---
target-mips/helper.h | 11 ++
target-mips/msa_helper.c | 244 ++
target-mips/translate.c | 98 ++
3 files changed, 353 insertions(+), 0 deletions(-)
diff
add MSA MI10 format instructions
Signed-off-by: Yongbok Kim
---
target-mips/helper.h |2 +
target-mips/msa_helper.c | 75 ++
target-mips/translate.c | 43 ++
3 files changed, 120 insertions(+), 0 deletions(-)
diff
add MSA 2RF format instructions
Signed-off-by: Yongbok Kim
---
target-mips/helper.h | 16 ++
target-mips/msa_helper.c | 656 ++
target-mips/translate.c | 76 ++
3 files changed, 748 insertions(+), 0 deletions(-)
diff --git a/target-mips
Ping!
Patch for v2.1.0
-Original Message-
From: Yongbok Kim
Sent: 01 July 2014 17:43
To: qemu-devel@nongnu.org
Cc: aurel...@aurel32.net; Leon Alrae; Cristian Cuna; Yongbok Kim
Subject: [PATCH v2] target-mips: fix broken MIPS16 and microMIPS
Commit 240ce26a broke MIPS16 and microMIPS
02x target " TARGET_FMT_lx, opn,
ctx->hflags, btarget);
ctx->btarget = btarget;
+ctx->hflags |= MIPS_HFLAG_BDS32;
out:
tcg_temp_free_i64(t0);
Reviewed-by: Yongbok Kim
Regards,
Yongbok Kim
On 05/11/2014 17:43, Richard Henderson wrote:
On 10/29/2014 02:41 AM, Yongbok Kim wrote:
+void helper_msa_shf_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
+ uint32_t ws, uint32_t imm)
+{
+wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
+wr_t *pws
Avoid to allocate different TCG registers for the FPU registers
that are mapped on the MSA vectore registers.
Signed-off-by: Yongbok Kim
---
target-mips/translate.c |8 +++-
1 files changed, 3 insertions(+), 5 deletions(-)
diff --git a/target-mips/translate.c b/target-mips/translate.c
Hi All,
I have faced a problem to run a simple 64 bit Linux user mode
application on
32 bit Linux host machines.
I did some investigation and found out that the TARGET_ELF_PAGESTART
macro in
the linux-user/elfload.c is causing the problem.
However I am not sure if this is the right solution a
TARGET_ELF_PAGESTART is required to use abi_ulong to correctly handle
addresses for different target bits width.
This patch fixes a problem when running a 64-bit user mode application
on 32-bit host machines.
Signed-off-by: Yongbok Kim
Reviewed-by: Peter Maydell
---
linux-user/elfload.c |3
Add probe_write() forces a tlb_fill if the specified guest virtual
index isn't in the TCG softmmu TLB.
Signed-off-by: Yongbok Kim
---
include/exec/exec-all.h |2 ++
softmmu_template.h | 21 +
2 files changed, 23 insertions(+), 0 deletions(-)
diff --git a/in
mips_cpu_do_unaligned_access() callback.
This is crucial to support MSA misaligned accesses in Release 5 cores.
Yongbok Kim (3):
target-mips: Misaligned memory accesses for R6
softmmu: Add probe_write()
target-mips: Misaligned memory accesses for MSA
include/exec/exec-all.h |2 +
softmmu_template.h
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