This patch set adds support for misaligned memory accesses in MIPS architecture Release 6 and MIPS SIMD Architecture.
The behaviour, semantics, and architecture specifications of misaligned memory accesses are described in: MIPS Architecture For Programmers Volume I-A: Introduction to the MIPS64 Architecture, Appendix B Misaligned Memory Accesses. Available at http://www.imgtec.com/mips/architectures/mips64.asp Regards, Yongbok v4: * Removed the work-around per the recent TCG change for misaligned accesses * Added probe_write() (Richard) * Used helper_ret_*_mmu directly (Richard) * Removed TLB checking for MSA LD (Richard) * Removed unnecessary save_cpu_state() calls v3: * Rewrote MSA patch * Work-around is using byte-to-byte accesses and endianness corrections for R5+MSA. (This replaces the misaligned flag from v2.) (Leon) * Bug fixes (Leon) * Separate helper functions for each data formats v2: * Removed re-translation in the mips_cpu_do_unaligned_access() (Peter) * Checks validity only if an access is spanning into two pages in MSA (Leon) * Introduced misaligned flag to indicate MSA ld/st is ongoing, is used to allow misaligned accesses in the mips_cpu_do_unaligned_access() callback. This is crucial to support MSA misaligned accesses in Release 5 cores. Yongbok Kim (3): target-mips: Misaligned memory accesses for R6 softmmu: Add probe_write() target-mips: Misaligned memory accesses for MSA include/exec/exec-all.h | 2 + softmmu_template.h | 21 ++++++ target-mips/helper.h | 10 +++- target-mips/op_helper.c | 144 +++++++++++++++++++++++------------------ target-mips/translate.c | 21 ++++-- target-mips/translate_init.c | 2 +- 6 files changed, 127 insertions(+), 73 deletions(-) -- 1.7.5.4
