f->nmsrs' failed.
Signed-off-by: Yang Zhong
---
target/i386/kvm.c | 8
1 file changed, 8 insertions(+)
diff --git a/target/i386/kvm.c b/target/i386/kvm.c
index bf1655645b..e8841dcdb9 100644
--- a/target/i386/kvm.c
+++ b/target/i386/kvm.c
@@ -2572,6 +2572,14 @@ static void kvm_msr_entr
previous patch wrongly replaced FEAT_XSAVE_XCR0_{LO|HI} with
> > > > FEAT_XSAVE_XSS_{LO|HI} in CPUID(EAX=12,ECX=1):{ECX,EDX}, which made
> > > > SGX enclave only supported SSE and x87 feature(xfrm=0x3).
> > > >
> > > > Fixes: 301e90675c3f ("target
The previous patch wrongly replaced FEAT_XSAVE_XCR0_{LO|HI} with
FEAT_XSAVE_XSS_{LO|HI} in CPUID(EAX=12,ECX=1):{ECX,EDX}, which made
SGX enclave only supported SSE and x87 feature(xfrm=0x3).
Fixes: 301e90675c3f ("target/i386: Enable support for XSAVES based features")
Signed-off-by:
On Thu, Apr 06, 2023 at 02:05:06PM +0200, Paolo Bonzini wrote:
> Queued, thanks.
>
Paolo, thanks!
Yang
> Paolo
>
>
On Sun, Apr 09, 2023 at 04:40:50PM +0300, Michael Tokarev wrote:
> 06.04.2023 09:40, Yang Zhong wrote:
> > The previous patch wrongly replaced FEAT_XSAVE_XCR0_{LO|HI} with
> > FEAT_XSAVE_XSS_{LO|HI} in CPUID(EAX=12,ECX=1):{ECX,EDX}, which made
> > SGX enclave only supporte
On Wed, Nov 10, 2021 at 10:55:40AM -0600, Eric Blake wrote:
> On Mon, Nov 01, 2021 at 12:20:07PM -0400, Yang Zhong wrote:
> > Add the SGXEPCSection list into SGXInfo to show the multiple
> > SGX EPC sections detailed info, not the total size like before.
> > This patch can en
On Wed, Nov 10, 2021 at 05:07:40PM +0100, Paolo Bonzini wrote:
> On 11/10/21 13:56, Yang Zhong wrote:
> > Paolo, thanks!
> >
> > No other maintainers to review numa patches, so i will send the numa
> > patches again? thanks!
>
> The patch look good, but th
On Thu, Nov 11, 2021 at 08:55:35AM +0100, Philippe Mathieu-Daudé wrote:
> On 11/11/21 07:18, Yang Zhong wrote:
> > On Wed, Nov 10, 2021 at 10:55:40AM -0600, Eric Blake wrote:
> >> On Mon, Nov 01, 2021 at 12:20:07PM -0400, Yang Zhong wrote:
> >>> Add the SGXEPCSection
Hello Paolo,
Our customer used the Libvirt XML to start a SGX VM, but failed.
libvirt.libvirtError: internal error: unable to execute QEMU command 'qom-get':
Property 'sgx-epc.unavailable-features' not found
The XML file,
The new compound property command shou
Paolo, please help add below queued sgx fix into this PULL request, which was
missed from last time, thanks a lot!
https://lists.nongnu.org/archive/html/qemu-devel/2023-04/msg00841.html
https://lists.nongnu.org/archive/html/qemu-devel/2023-04/msg00896.html
Regards,
Yang
On Fri, May 19, 2023 at 10:29:47AM +0200, Paolo Bonzini wrote:
> On 5/19/23 05:06, Yang Zhong wrote:
> >
> > Paolo, please help add below queued sgx fix into this PULL request, which
> > was
> > missed from last time, thanks a lot!
> > https://lists.nongnu.or
Hello Alex and Paolo,
There is one instance_finalize callback definition in hw/vfio/pci.c, but
i find this callback(vfio_instance_finalize()) never be called during the
VM shutdown with close VM or "init 0" command in guest.
The Qemu related command:
..
-device vfio-pci,host=d9:00.0
On Tue, Mar 21, 2023 at 06:30:14PM +0100, Cédric Le Goater wrote:
> On 3/20/23 10:31, Yang Zhong wrote:
> > Hello Alex and Paolo,
> >
> > There is one instance_finalize callback definition in hw/vfio/pci.c, but
> > i find this callback(vfio_instance_finalize()) never
On Tue, Mar 21, 2023 at 09:44:18PM +0100, Paolo Bonzini wrote:
> Il mar 21 mar 2023, 18:30 Cédric Le Goater ha scritto:
>
> > I would have thought that user_creatable_cleanup would have taken care
> > of it. But it's not. This needs some digging.
> >
>
> user_creatable_cleanup is only for -objec
On Wed, Mar 22, 2023 at 01:56:13PM +0100, Cédric Le Goater wrote:
> On 3/22/23 13:28, Yang Zhong wrote:
> > On Tue, Mar 21, 2023 at 06:30:14PM +0100, Cédric Le Goater wrote:
> > > On 3/20/23 10:31, Yang Zhong wrote:
> > > > Hello Alex and Paolo,
> > > &g
On Wed, Mar 22, 2023 at 12:22:27PM -0600, Alex Williamson wrote:
> On Wed, 22 Mar 2023 09:10:20 -0400
> Yang Zhong wrote:
>
> > On Wed, Mar 22, 2023 at 01:56:13PM +0100, Cédric Le Goater wrote:
> > > On 3/22/23 13:28, Yang Zhong wrote:
> > > > On Tue, Mar
On Mon, Feb 21, 2022 at 01:00:41PM +, David Edmondson wrote:
> On Wednesday, 2022-02-16 at 22:04:30 -08, Yang Zhong wrote:
>
> > From: Jing Liu
> >
> > Intel introduces XFD faulting mechanism for extended
> > XSAVE features to dynamically enable the features in
On Mon, Feb 21, 2022 at 01:25:53PM +, David Edmondson wrote:
> On Wednesday, 2022-02-16 at 22:04:32 -08, Yang Zhong wrote:
>
> > From: Jing Liu
> >
> > When dynamic xfeatures (e.g. AMX) are used by the guest, the xsave
> > area would be larger than 4KB. KV
On Thu, Feb 17, 2022 at 02:44:10PM +0100, Paolo Bonzini wrote:
> On 2/17/22 06:58, Yang Zhong wrote:
> >>+
> >>+if ((mask & XSTATE_XTILE_DATA_MASK) == XSTATE_XTILE_DATA_MASK) {
> >>+bitmask = kvm_arch_get_supported_cpuid(s, 0xd, 0,
From: Jing Liu
Intel introduces XFD faulting mechanism for extended
XSAVE features to dynamically enable the features in
runtime. If CPUID (EAX=0Dh, ECX=n, n>1).ECX[2] is set
as 1, it indicates support for XFD faulting of this
state component.
Signed-off-by: Jing Liu
Signed-off-by: Yang Zh
to
get host side supported_xcr0 and Qemu can decide if it can request
dynamically enabled XSAVE features permission.
https://lore.kernel.org/all/20220126152210.3044876-1-pbonz...@redhat.com/
Suggested-by: Paolo Bonzini
Signed-off-by: Yang Zhong
Signed-off-by: Jing Liu
---
target/i386/cpu.h
(5):
x86: Fix the 64-byte boundary enumeration for extended state
x86: Add AMX XTILECFG and XTILEDATA components
x86: Add XFD faulting bit for state components
x86: Add AMX CPUIDs enumeration
x86: Add support for KVM_CAP_XSAVE2 and AMX state migration
Yang Zhong (2):
x86: Grant AMX permissio
no supported component
needed the bit to be set, but the upcoming AMX feature will
use it. Fix the subleaves value according to KVM's supported
cpuid.
Signed-off-by: Jing Liu
Signed-off-by: Yang Zhong
Reviewed-by: David Edmondson
---
target/i386/cpu.h | 6 ++
target/i386/cpu.c
of
AMX XSAVE areas and use QEMU_BUILD_BUG_ON to validate the
structs sizes.
Signed-off-by: Jing Liu
Signed-off-by: Yang Zhong
Reviewed-by: David Edmondson
---
target/i386/cpu.h | 18 +-
target/i386/cpu.c | 8
2 files changed, 25 insertions(+), 1 deletion(-)
diff
: Jing Liu
Signed-off-by: Zeng Guang
Signed-off-by: Wei Wang
Signed-off-by: Yang Zhong
---
target/i386/cpu.h | 4
target/i386/kvm/kvm.c | 42 --
target/i386/xsave_helper.c | 33 ++
3 files changed, 64 insertions
From: Jing Liu
Add AMX primary feature bits XFD and AMX_TILE to
enumerate the CPU's AMX capability. Meanwhile, add
AMX TILE and TMUL CPUID leaf and subleaves which
exist when AMX TILE is present to provide the maximum
capability of TILE and TMUL.
Signed-off-by: Jing Liu
Signed-off-by:
This patch will be dropped once Qemu sync linux 5.17 header.
Making all linux-headers changes here are only for maintainers
to easily remove those changes once those patches are queued.
Signed-off-by: Yang Zhong
---
linux-headers/asm-x86/kvm.h | 3 +++
linux-headers/linux/kvm.h | 1 +
2 files
.
Signed-off-by: Zeng Guang
Signed-off-by: Wei Wang
Signed-off-by: Yang Zhong
Reviewed-by: David Edmondson
---
target/i386/cpu.h | 9 +
target/i386/kvm/kvm.c | 18 ++
target/i386/machine.c | 42 ++
3 files changed, 69 insertions
On Fri, Sep 24, 2021 at 08:56:40AM -0500, Eric Blake wrote:
> On Fri, Sep 24, 2021 at 01:24:47PM +0200, Paolo Bonzini wrote:
> > From: Yang Zhong
> >
> > Add the new 'memory-backend-epc' user creatable QOM object in
> > the ObjectOptions to support SGX sinc
On Mon, Jan 17, 2022 at 04:53:45AM +0200, Jarkko Sakkinen wrote:
> On Tue, Nov 30, 2021 at 08:15:36PM +0800, Yang Zhong wrote:
> > On Thu, Nov 25, 2021 at 08:47:22PM +0800, Yang Zhong wrote:
> > > Hello Paolo,
> > >
> > > Our customer used the Libvi
On Thu, Jan 13, 2022 at 04:15:10PM +, Daniel P. Berrangé wrote:
> On Wed, Dec 15, 2021 at 09:25:13PM +0100, Paolo Bonzini wrote:
> > From: Yang Zhong
> >
> > Add the SGXEPCSection list into SGXInfo to show the multiple
> > SGX EPC sections detailed info, not
On Mon, Jan 17, 2022 at 01:48:46PM +, Daniel P. Berrangé wrote:
> On Mon, Jan 17, 2022 at 12:53:30AM +0100, Philippe Mathieu-Daudé via wrote:
> > Avoid having CPUs objects dangling as unattached QOM ones,
> > directly attach them to the machine.
>
> Lets be more explicit here
>
> [quote]
>
On Mon, Jan 17, 2022 at 12:48:10PM +0100, Paolo Bonzini wrote:
> On 1/17/22 00:53, Philippe Mathieu-Daudé via wrote:
> >We have one SGX-EPC address/size/node per memory backend,
> >make it child of the backend in the QOM composition tree.
> >
> >Cc: Yang Zhong
> &g
The SGX NUMA patches were merged into Qemu 7.0 release, we need
clarify detailed version history information and also change
some related comments, which make SGX related comments clearer.
Signed-off-by: Yang Zhong
---
qapi/machine.json | 4 ++--
qapi/misc-target.json | 14
On Wed, Jan 19, 2022 at 09:16:46AM +, Daniel P. Berrangé wrote:
> On Wed, Jan 19, 2022 at 07:00:14AM -0500, Yang Zhong wrote:
> > The SGX NUMA patches were merged into Qemu 7.0 release, we need
> > clarify detailed version history information and also change
> > some re
-size", which can avoid incompatible
API breakage. The "@section-size" will be deprecated in 7.2 version.
Suggested-by: Daniel P. Berrangé
Signed-off-by: Yang Zhong
Reviewed-by: Daniel P. Berrangé
---
qapi/machine.json | 4 ++--
qapi/misc-target.json | 17
On Thu, Jan 20, 2022 at 09:10:34AM +, Daniel P. Berrangé wrote:
> On Wed, Jan 19, 2022 at 06:57:20PM -0500, Yang Zhong wrote:
> > The SGX NUMA patches were merged into Qemu 7.0 release, we need
> > clarify detailed version history information and also change
> > some re
On Thu, Jan 20, 2022 at 09:44:34AM +, Daniel P. Berrangé wrote:
> On Thu, Jan 20, 2022 at 05:16:01PM +0800, Yang Zhong wrote:
> > On Thu, Jan 20, 2022 at 09:10:34AM +, Daniel P. Berrangé wrote:
> > > On Wed, Jan 19, 2022 at 06:57:20PM -0500, Yang Zhong wrote:
> >
-size", which can avoid incompatible
API breakage. The "@section-size" will be deprecated in 7.2 version.
Suggested-by: Daniel P. Berrangé
Signed-off-by: Yang Zhong
Reviewed-by: Daniel P. Berrangé
---
docs/about/deprecated.rst | 13 +
qapi/machine.json
On Tue, Jan 18, 2022 at 01:37:20PM +0100, Paolo Bonzini wrote:
> On 1/11/22 03:22, Yang Zhong wrote:
> > Thanks Kevin, I will update this in next version.
>
> Also:
>
> The extended state subleaves (EAX=0Dh, ECX=n, n>1).ECX[1]
> indicate whether the exten
On Tue, Jan 18, 2022 at 01:39:59PM +0100, Paolo Bonzini wrote:
> On 1/10/22 09:23, Tian, Kevin wrote:
> >>
> >>AMX XTILECFG and XTILEDATA are managed by XSAVE feature
> >>set. State component 17 is used for 64-byte TILECFG register
> >>(XTILECFG state) and component 18 is used for 8192 bytes
> >>of
On Tue, Jan 18, 2022 at 01:52:51PM +0100, Paolo Bonzini wrote:
> On 1/7/22 10:31, Yang Zhong wrote:
> >-uint32_t need_align;
> >+uint32_t need_align, support_xfd;
>
> These can be replaced by a single field "uint32_t ecx".
>
> You
On Tue, Jan 18, 2022 at 02:06:55PM +0100, Paolo Bonzini wrote:
> Sorry, hit send on the wrong window. This is the only patch that
> will require a bit more work.
>
> On 1/18/22 13:52, Paolo Bonzini wrote:
> >>@@ -124,6 +150,8 @@ void x86_cpus_init(X86MachineState *x86ms,
> >>int default_cpu_versi
On Mon, Jan 17, 2022 at 12:48:10PM +0100, Paolo Bonzini wrote:
> On 1/17/22 00:53, Philippe Mathieu-Daudé via wrote:
> >We have one SGX-EPC address/size/node per memory backend,
> >make it child of the backend in the QOM composition tree.
> >
> >Cc: Yang Zhong
> &g
dd support for KVM_CAP_XSAVE2 and AMX state migration
Yang Zhong (1):
x86: Grant AMX permission for guest
Zeng Guang (1):
x86: Support XFD and AMX xsave data migration
linux-headers/asm-x86/kvm.h | 14 ++
linux-headers/linux/kvm.h | 2 +
target/i386/cpu.h | 46 +
xfeatures).
There are separate permissions for native tasks and guests.
Qemu should request the guest permissions for dynamic xfeatures
which will be exposed to the guest. This only needs to be done
once before the first vcpu is created.
Suggested-by: Paolo Bonzini
Signed-off-by: Yang Zhong
Signed
no supported component
needed the bit to be set, but the upcoming AMX feature will
use it. Fix the subleaves value according to KVM's supported
cpuid.
Signed-off-by: Jing Liu
Signed-off-by: Yang Zhong
---
target/i386/cpu.h | 6 ++
target/i386/cpu.c | 1 +
target/i386/kvm/kvm-c
of
AMX XSAVE areas and use QEMU_BUILD_BUG_ON to validate the
structs sizes.
Signed-off-by: Jing Liu
Signed-off-by: Yang Zhong
---
target/i386/cpu.h | 18 +-
target/i386/cpu.c | 8
2 files changed, 25 insertions(+), 1 deletion(-)
diff --git a/target/i386/cpu.h b/target
From: Jing Liu
Intel introduces XFD faulting mechanism for extended
XSAVE features to dynamically enable the features in
runtime. If CPUID (EAX=0Dh, ECX=n, n>1).ECX[2] is set
as 1, it indicates support for XFD faulting of this
state component.
Signed-off-by: Jing Liu
Signed-off-by: Yang Zh
: Jing Liu
Signed-off-by: Zeng Guang
Signed-off-by: Wei Wang
Signed-off-by: Yang Zhong
---
linux-headers/asm-x86/kvm.h | 14 +
linux-headers/linux/kvm.h | 2 ++
target/i386/cpu.h | 4
target/i386/kvm/kvm.c | 42 -
target/i386
From: Jing Liu
Add AMX primary feature bits XFD and AMX_TILE to
enumerate the CPU's AMX capability. Meanwhile, add
AMX TILE and TMUL CPUID leaf and subleaves which
exist when AMX TILE is present to provide the maximum
capability of TILE and TMUL.
Signed-off-by: Jing Liu
Signed-off-by:
.
Signed-off-by: Zeng Guang
Signed-off-by: Wei Wang
Signed-off-by: Yang Zhong
---
target/i386/cpu.h | 9 +
target/i386/kvm/kvm.c | 18 ++
target/i386/machine.c | 42 ++
3 files changed, 69 insertions(+)
diff --git a/target/i386
On Mon, Jan 24, 2022 at 11:16:36AM +0100, Paolo Bonzini wrote:
> On 1/24/22 08:55, Yang Zhong wrote:
> >Kernel allocates 4K xstate buffer by default. For XSAVE features
> >which require large state component (e.g. AMX), Linux kernel
> >dynamically expands the xstate buffer o
On Mon, Jan 24, 2022 at 11:13:07AM +0100, Paolo Bonzini wrote:
> On 1/24/22 08:55, Yang Zhong wrote:
> >diff --git a/target/i386/kvm/kvm.c b/target/i386/kvm/kvm.c
> >index caf1388d8b..25d26a15f8 100644
> >--- a/target/i386/kvm/kvm.c
> >+++ b/target/i386/kvm/kvm.c
&
On Mon, Jan 24, 2022 at 11:15:25AM +0100, Paolo Bonzini wrote:
> On 1/24/22 08:55, Yang Zhong wrote:
> >
> >+if (buflen > sizeof(struct kvm_xsave)) {
> >+e = &x86_ext_save_areas[XSTATE_XTILE_DATA_BIT];
> >+
> >+if (e->size &&
Add the MEMORY_DEVICE_INFO_KIND_SGX_EPC case for SGX numa info
with 'info numa' command in the monitor.
Signed-off-by: Yang Zhong
---
hw/core/numa.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/hw/core/numa.c b/hw/core/numa.c
index 510d096a88..1aa05dcf42 100644
--- a/hw/c
d the previous patch 4 and patch 5 into patch 3.(Paolo)
- added reset patch(patch 5) into this version.
Yang Zhong (5):
numa: Enable numa for SGX EPC sections
monitor: Support 'info numa' command
numa: Support SGX numa in the monitor and Libvirt interfaces
doc: Add the SGX numa des
,id=mem1,size=28M,prealloc=on,host-nodes=1,policy=bind \
-numa node,nodeid=1,cpus=2-3,memdev=node1 \
-M
sgx-epc.0.memdev=mem0,sgx-epc.0.node=0,sgx-epc.1.memdev=mem1,sgx-epc.1.node=1 \
..
Signed-off-by: Yang Zhong
---
qapi/machine.json | 10 -
include/hw/i386/sgx-epc.h | 3
quot;return": {"sgx": true, "sgx2": true, "sgx1": true, "sections": \
[{"node": 0, "size": 17070817280}, {"node": 1, "size": 17079205888}], "flc":
true}}
Signed-off-by: Yang Zhong
---
qapi/misc-target.json |
Add the SGX numa reference command and how to check if
SGX numa is support or not with multiple EPC sections.
Signed-off-by: Yang Zhong
---
docs/system/i386/sgx.rst | 31 +++
1 file changed, 27 insertions(+), 4 deletions(-)
diff --git a/docs/system/i386/sgx.rst b
returns the number of EREMOVE failures,
telling Qemu to try the ioctl again after it's done with all vEPC regions.
The related kernel patches:
Link: https://lkml.kernel.org/r/20211021201155.1523989-3-pbonz...@redhat.com
Signed-off-by: Yang Zhong
---
include/hw/i386/x86.h | 1 +
linux-he
On Tue, Nov 09, 2021 at 06:48:59PM +0100, Paolo Bonzini wrote:
> On 11/9/21 15:25, Thomas Huth wrote:
> >Our device-crash-test script reports that this new device can be
> >used to crash QEMU:
> >
> >$ ./qemu-system-x86_64 -M none -device sgx-epc
> >/home/thuth/devel/qemu/include/hw/i386/pc.h:128:P
On Wed, Nov 10, 2021 at 01:52:09PM +0100, Paolo Bonzini wrote:
> On 11/1/21 17:20, Yang Zhong wrote:
> >The basic SGX patches were merged into Qemu release, the left NUMA
> >function for SGX should be enabled. The patch1 implemented the SGX NUMA
> >ACPI to enable NUMA in
On Mon, Oct 11, 2021 at 11:32:39AM -0500, Eric Blake wrote:
> On Mon, Oct 11, 2021 at 07:15:49PM +0800, Yang Zhong wrote:
> > The basic SGX did not enable numa for SGX EPC sections, which
> > result in all EPC sections located in numa node 0. This patch
> > enable SGX numa
On Tue, Oct 12, 2021 at 12:59:17PM +0200, Paolo Bonzini wrote:
> On 11/10/21 13:15, Yang Zhong wrote:
> >This patch can enable numa support for 'info sgx' command
> >in the monitor, which can show detailed SGX EPC sections
> >info.
> >
> >(qemu) info sgx
On Mon, Oct 11, 2021 at 12:03:24PM -0500, Eric Blake wrote:
> On Mon, Oct 11, 2021 at 07:15:51PM +0800, Yang Zhong wrote:
> > The SGXEPCSection list added into SGXInfo to show the multiple
> > SGX EPC sections detailed info, not the total size like before.
> >
> >
On Tue, Oct 12, 2021 at 01:01:34PM +0200, Paolo Bonzini wrote:
> On 11/10/21 13:15, Yang Zhong wrote:
> >The SGXEPCSection list added into SGXInfo to show the multiple
> >SGX EPC sections detailed info, not the total size like before.
> >
> >Signed-off-by: Yang Z
...@redhat.com/
Thanks!
Yang
Changes from V1:
- added documents for new members.(Eric)
- changed the "index" to "node" in struct SGXEPCSection.(Eric, Paolo)
- squashed the previous patch 4 and patch 5 into patch 3.(Paolo)
- added reset patch(patch 5) into this version.
Ya
Add the SGX numa reference command and how to check if
SGX numa is support or not with multiple EPC sections.
Signed-off-by: Yang Zhong
---
docs/system/i386/sgx.rst | 31 +++
1 file changed, 27 insertions(+), 4 deletions(-)
diff --git a/docs/system/i386/sgx.rst b
Add the MEMORY_DEVICE_INFO_KIND_SGX_EPC case for SGX numa info
with 'info numa' command in the monitor.
Signed-off-by: Yang Zhong
---
hw/core/numa.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/hw/core/numa.c b/hw/core/numa.c
index 510d096a88..1aa05dcf42 100644
--- a/hw/c
,id=mem1,size=28M,prealloc=on,host-nodes=1,policy=bind \
-numa node,nodeid=1,cpus=2-3,memdev=node1 \
-M
sgx-epc.0.memdev=mem0,sgx-epc.0.node=0,sgx-epc.1.memdev=mem1,sgx-epc.1.node=1 \
..
Signed-off-by: Yang Zhong
---
qapi/machine.json | 10 -
include/hw/i386/sgx-epc.h | 3
quot;return": {"sgx": true, "sgx2": true, "sgx1": true, "sections": \
[{"node": 0, "size": 17070817280}, {"node": 1, "size": 17079205888}], "flc":
true}}
Signed-off-by: Yang Zhong
---
qapi/misc-target.json |
erged, the kernel commit ids will be updated
here.
Signed-off-by: Yang Zhong
---
include/hw/i386/x86.h | 1 +
linux-headers/linux/kvm.h | 6 +
hw/i386/sgx.c | 53 +++
hw/i386/x86.c | 4 +++
4 files changed, 64 insertions(+)
On Fri, Oct 22, 2021 at 11:46:30PM +0200, Paolo Bonzini wrote:
> On 22/10/21 21:27, Yang Zhong wrote:
> >+
> >+for (j = 0; j < num; j++) {
> >+epc = pcms->sgx_epc.sections[j];
> >+hostmem = MEMORY_BACKEND(epc->hostmem);
&
From: Jing Liu
Add AMX primary feature bits XFD and AMX_TILE to
enumerate the CPU's AMX capability. Meanwhile, add
AMX TILE and TMUL CPUID leaf and subleaves which
exist when AMX TILE is present to provide the maximum
capability of TILE and TMUL.
Signed-off-by: Jing Liu
Signed-off-by:
AVE area is
used.
Fix the subleaves value according to the host supported
cpuid. The upcoming AMX feature would be the first one
using it.
Signed-off-by: Jing Liu
Signed-off-by: Yang Zhong
---
target/i386/cpu.h | 1 +
target/i386/cpu.c | 1 +
target/i386/kvm/kvm-cpu.c | 3 +++
3 fi
ml
Thanks,
Yang
Jing Liu (5):
x86: Fix the 64-byte boundary enumeration for extended state
x86: Add AMX XTILECFG and XTILEDATA components
x86: Add XFD faulting bit for state components
x86: Add AMX CPUIDs enumeration
x86: Use new XSAVE ioctls handling
Yang Zhong (1):
x86:
guest only once
before the first vCPU is created. KVM checks the guest
permission when Qemu advertises the features, and the
advertising operation fails w/o permission.
Signed-off-by: Yang Zhong
Signed-off-by: Jing Liu
---
target/i386/cpu.h | 7 +++
hw/i386/x86.c | 28
From: Jing Liu
Intel introduces XFD faulting mechanism for extended
XSAVE features to dynamically enable the features in
runtime. If CPUID (EAX=0Dh, ECX=n, n>1).ECX[2] is set
as 1, it indicates support for XFD faulting of this
state component.
Signed-off-by: Jing Liu
Signed-off-by: Yang Zh
. Add structs that define the layout of
AMX XSAVE areas and use QEMU_BUILD_BUG_ON to validate the
structs sizes.
Signed-off-by: Jing Liu
Signed-off-by: Yang Zhong
---
target/i386/cpu.h | 16 +++-
target/i386/cpu.c | 8
2 files changed, 23 insertions(+), 1 deletion(-)
diff
From: Jing Liu
Extended feature has large state while current
kvm_xsave only allows 4KB. Use new XSAVE ioctls
if the xstate size is large than kvm_xsave.
Signed-off-by: Jing Liu
Signed-off-by: Zeng Guang
Signed-off-by: Wei Wang
Signed-off-by: Yang Zhong
---
linux-headers/asm-x86/kvm.h | 14
.
Signed-off-by: Zeng Guang
Signed-off-by: Wei Wang
Signed-off-by: Yang Zhong
---
target/i386/cpu.h | 9 +
target/i386/kvm/kvm.c | 18 ++
target/i386/machine.c | 42 ++
3 files changed, 69 insertions(+)
diff --git a/target/i386
; up AMX components. Add structs that define the layout of
> > AMX XSAVE areas and use QEMU_BUILD_BUG_ON to validate the
> > structs sizes.
> >
> > Signed-off-by: Jing Liu
> > Signed-off-by: Yang Zhong
> > ---
> > target/i386/cpu.h | 16 ++
On Mon, Jan 10, 2022 at 04:20:41PM +0800, Tian, Kevin wrote:
> > From: Zhong, Yang
> > Sent: Friday, January 7, 2022 5:31 PM
> >
> > From: Jing Liu
> >
> > The extended state subleaves (EAX=0Dh, ECX=n, n>1).ECX[1]
> > are all zero, while spec actually introduces that bit 01
> > should indicate if
features in
> > runtime. If CPUID (EAX=0Dh, ECX=n, n>1).ECX[2] is set
> > as 1, it indicates support for XFD faulting of this
> > state component.
> >
> > Signed-off-by: Jing Liu
> > Signed-off-by: Yang Zhong
> > ---
> > target/i386/cpu.h
here are separate permissions for native tasks and guests.
>
> Qemu should request the guest permissions for dynamic xfeatures
> which will be exposed to the guest. This only needs to be done
> once before the first vcpu is created."
This is clearer. Will update this in new vers
ice[0] is occupied by sgx-epc device, which
fail to get the unvailable-features from /machine/unattached/device[0].
This patch make one new /machine/sgx object to avoid this issue.
(qemu) qom-list /machine/unattached/
device[0] (child)
(qemu) qom-list /machine/sgx
device[0] (child)
Signed-off-by:
Hi Daniel,
On Wed, Jan 12, 2022 at 10:11:35AM +, Daniel P. Berrangé wrote:
> On Wed, Jan 12, 2022 at 11:55:17AM -0500, Yang Zhong wrote:
> > When Libvirt start, it get the vcpu's unavailable-features from
> > /machine/unattached/device[0] path by qom-get command, but in
this patch can move sgx virtual device from /machine/unattached/device[nn]
to /machine/sgx-epc[nn], which seems more clear. Thanks!
Yang
>
> >
> > Reported-by: Yang Zhong
> > Suggested-by: Paolo Bonzini
> > Reviewed-by: Daniel P. Berrangé
> > Signed-
where the 'nn' varies depending on what devices were already created.
> >
> > With this change the SGX-EPC objects are now at
> >
> > /machine/sgx-epc[nn]
> >
> > where the 'nn' of the first SGX-EPC object is always zero.
>
>
to
get host side supported_xcr0 and Qemu can decide if it can request
dynamically enabled XSAVE features permission.
https://lore.kernel.org/all/20220126152210.3044876-1-pbonz...@redhat.com/
Suggested-by: Paolo Bonzini
Signed-off-by: Yang Zhong
Signed-off-by: Jing Liu
---
target/i386/cpu.h
kvm_arch_init_vcpu() to
make the request permission before KVM_CAP_XSAVE2 extension check(Paolo).
- Removed RFC prefix.
Jing Liu (5):
x86: Fix the 64-byte boundary enumeration for extended state
x86: Add AMX XTILECFG and XTILEDATA components
x86: Add XFD faulting bit for state component
no supported component
needed the bit to be set, but the upcoming AMX feature will
use it. Fix the subleaves value according to KVM's supported
cpuid.
Signed-off-by: Jing Liu
Signed-off-by: Yang Zhong
---
target/i386/cpu.h | 6 ++
target/i386/cpu.c | 1 +
target/i386/kvm/kvm-c
From: Jing Liu
Intel introduces XFD faulting mechanism for extended
XSAVE features to dynamically enable the features in
runtime. If CPUID (EAX=0Dh, ECX=n, n>1).ECX[2] is set
as 1, it indicates support for XFD faulting of this
state component.
Signed-off-by: Jing Liu
Signed-off-by: Yang Zh
From: Jing Liu
Add AMX primary feature bits XFD and AMX_TILE to
enumerate the CPU's AMX capability. Meanwhile, add
AMX TILE and TMUL CPUID leaf and subleaves which
exist when AMX TILE is present to provide the maximum
capability of TILE and TMUL.
Signed-off-by: Jing Liu
Signed-off-by:
of
AMX XSAVE areas and use QEMU_BUILD_BUG_ON to validate the
structs sizes.
Signed-off-by: Jing Liu
Signed-off-by: Yang Zhong
---
target/i386/cpu.h | 18 +-
target/i386/cpu.c | 8
2 files changed, 25 insertions(+), 1 deletion(-)
diff --git a/target/i386/cpu.h b/target
: Jing Liu
Signed-off-by: Zeng Guang
Signed-off-by: Wei Wang
Signed-off-by: Yang Zhong
---
target/i386/cpu.h | 4
target/i386/kvm/kvm.c | 42 --
target/i386/xsave_helper.c | 33 ++
3 files changed, 64 insertions
.
Signed-off-by: Zeng Guang
Signed-off-by: Wei Wang
Signed-off-by: Yang Zhong
---
target/i386/cpu.h | 9 +
target/i386/kvm/kvm.c | 18 ++
target/i386/machine.c | 42 ++
3 files changed, 69 insertions(+)
diff --git a/target/i386
This patch will be dropped once Qemu sync linux 5.17 header.
Making all linux-headers changes here are only for maintainers
to easily remove those changes once those patches are queued.
Signed-off-by: Yang Zhong
---
linux-headers/asm-x86/kvm.h | 17 +
linux-headers/linux/kvm.h
On Wed, Feb 16, 2022 at 10:04:29PM -0800, Yang Zhong wrote:
> Kernel allocates 4K xstate buffer by default. For XSAVE features
> which require large state component (e.g. AMX), Linux kernel
> dynamically expands the xstate buffer only after the process has
> acquired the necessary
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