still haven't find a good way to know when
the guest OS is modifying guest page table entry.
Any idea is welcomed. Thanks.
Regards,
chenwj
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Tel:886-2-2788-3799 #1667
Homepage:
On Wed, Aug 08, 2012 at 09:05:18AM +0100, Peter Maydell wrote:
> On 8 August 2012 08:38, 陳韋任 (Wei-Ren Chen) wrote:
> > Just for research, we are studying if we can leave the guest page
> > table walk to underlying hardware rather than using software emulation
> > (like
> I propose we use gcc builtins. We get automatic architecture support,
> and tuning for newer processors if the user so chooses.
>
> http://gcc.gnu.org/onlinedocs/gcc-4.1.2/gcc/Atomic-Builtins.html
>
> In May 2031 we can switch to C11 atomics.
Maybe 2013?
--
y, I am not familiar with the memory stuff. Could
you explain a little bit about what notdirty and watch_mem does? Googleing
doesn't help much...
Thanks!
Regards,
chenwj
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Hi Peter,
On Wed, Aug 08, 2012 at 09:05:18AM +0100, Peter Maydell wrote:
> On 8 August 2012 08:38, 陳韋任 (Wei-Ren Chen) wrote:
> > Just for research, we are studying if we can leave the guest page
> > table walk to underlying hardware rather than using software emulation
&g
then you have corresponding HVA
ready to use; otherwise, it'll call qemu_ld_helpers which are actually
functions synthesized by macro in files softmmu_*.h. Note that what I am
describing above is for QEMU system mode. Good luck!
HTH,
chenwj
--
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Computer Systems Lab, Institute of In
hing like that.
Regards,
chenwj
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Tel:886-2-2788-3799 #1667
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chard_name[257];/* We must not include limits.h! */
> + /* 257 = NAME_MAX + '\0' + d_type */
> };
>
> struct target_dirent64 {
>
> --
> ldv
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Tel:886-2-2788-3799 #1667
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r you said you log the register information before disassembling
each guest code? In other words, (guest) ebx might not be the value you
saw here. This is just my opinion.
Regards,
chenwj
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Computer Systems Lab, Institute of Information Science,
Academia Sinica, Taiwan (R.O.C.)
when the fast path executed,
it "generates" code instead. Therefore, you might have to insert your
instrument code in the code cache, perhaps modifying tcg_out_tlb_load
to log value of "addrlo" (see comments above tcg_out_tlb_load).
HTH,
chenwj
[1] http://lists.gnu.org/archi
something like
float VFP_helper(float a, float b) {
...
}
But I am wrong, it acutally does this, right?
float64 VFP_HELPER(sqrt, d)(float64 a, CPUARMState *env)
{
return float64_sqrt(a, &env->vfp.fp_status);
}
And float64_sqrt is implemented in fpu/* .
Regards,
chenwj
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Wei-R
On Fri, Aug 17, 2012 at 03:57:55PM +0400, Max Filippov wrote:
> On Fri, Aug 17, 2012 at 3:14 PM, 陳韋任 (Wei-Ren Chen)
> wrote:
> >> > On Thu, Aug 16, 2012 at 7:49 PM, Steven wrote:
> >> > [...]
> >> >> I want to get the guest memory address in the ins
o problem. What I am missing here? Thanks.
Regards,
chenwj
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Homepage: http://people.cs.nctu.edu.tw/~chenwj
(or should I CC him?). However, I do not see a relevant code in
> git master.
This may be a little late, but yes, please cc to Lluís to ask him
opinion.
Regards,
chenwj
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Tel:886
pde = ldq_phys(pde_addr);
...
}
---
The address of pde and pte should be (guest) physical address, right?
If so, then target_ulong should be replaced with target_phys_addr_t.
The other clue is the type of ldq_phys's parameter is target_phys_addr_t.
Regards,
chenwj
--
Wei-Ren Chen (陳韋任)
Co
directly.
^^^
Would be better if you make it align.
Regards,
chenwj
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, which works fine now.
Another question is, I would like to know the hva corresponding to gpa (i.e.,
the guest page pointed by guest pte). Do you happen to know there is such
gpa2hva function in QEMU?
Thanks.
Regards,
chenwj
--
Wei-Ren Chen (陳韋任)
Computer Systems Lab, Institute of
e in that address into tmp. So, what "translated value" you mean
here? The guest physical address, host virtual address, or the value
of the guest virtual address?
Regards,
chenwj
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Computer Systems Lab, Institute of Information Science,
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= (env->cr[3] + 32 * 4) & env->a20_mask;
target_phys_addr_t len = 4;
void *ptr = cpu_physical_memory_map(pde_addr, &len, 0);
The only thing I am not sure about is what value of len I should use.
Regards,
chenwj
--
Wei-Ren Chen (陳韋任)
Computer Systems Lab, Institute of
On Wed, Aug 22, 2012 at 09:38:17PM -0700, Xin Tong wrote:
> On Wed, Aug 22, 2012 at 8:14 PM, 陳韋任 (Wei-Ren Chen)
> wrote:
> >> In tcg_gen_qemu_ld8s(tmp, addr, index); a TCGv addr is passed to the
> >> INDEX_op_qemu_ld8s as param and the loaded value is passed back in
>
s,
chenwj
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virtual address into a file or
something else, then insert a helper function call at the point of
TLB hit.
HTH,
chenwj
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tion "cpu_physical_memory_unmap", the comment
of it says,
Unmaps a memory region previously mapped by cpu_physical_memory_map().
That makes me not sure if I use cpu_physical_memory_map correctly,
does it do what I want to do?
Regards,
chenwj
--
Wei-Ren Chen (陳韋任)
Comput
ss. IIUC, pde_addr and pte_addr should be the
guest physical address for guest page table and guest page respectively,
right? If no one object, I'll send a patch which replaces target_ulong
with target_phys_addr_t.
Thanks.
Regards,
chenwj
--
Wei-Ren Chen (陳韋任)
Computer Systems Lab, Instit
e performance degradation. If software
tlb hit, you can get the value of guest memory in the code cache
with a few host instructions. Disabling software tlb lookup, every guest
memory access will call a helper function which takes a lot of time.
What you mean by "get rid of that piece of genera
anything.
True, the inline tlb lookup will take some space on icache, but I
believe it's not a big deal since you're on a x86 host.
Regards,
chenwj
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t;
> It may be we're deliberately (mis)using target_ulong to get the
> right behaviour on both 32 and 64 bit cores.
Need to be further investigated. :)
Regards,
chenwj
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r;
... snip ...
}
Regards,
chenwj
[1]
http://download.intel.com/products/processor/manual/253668.pdf
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dd a new guest,
tcg/xxx/ if you want to add a new host.
Regards,
chenwj
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Wei-Ren Chen (陳韋任)
Computer Systems Lab, Institute of Information Science,
Academia Sinica, Taiwan (R.O.C.)
Tel:886-2-2788-3799 #1667
Homepage: http://people.cs.nctu.edu.tw/~chenwj
On Sat, Aug 25, 2012 at 11:56:13AM +0100, Peter Maydell wrote:
> On 24 August 2012 04:14, 陳韋任 (Wei-Ren Chen) wrote:
> > I would like to know if there is a function in QEMU which converts
> > a guest physical address into corresponding host virtual address.
>
> So the que
> I want to add a new guest architecture.
>
> Is there any description of what the configuration options mean?
You mean the options list in `../${QEMU_SRC}/configure --help`?
Not sure why you need to care about that.
Regards,
chenwj
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Wei-Ren Chen (陳韋任)
Computer Systems Lab, Ins
On Sat, Aug 25, 2012 at 08:33:41AM -0700, Michael Eager wrote:
> On 08/25/2012 05:57 AM, 陳韋任 (Wei-Ren Chen) wrote:
> > On Fri, Aug 24, 2012 at 05:46:43PM -0700, Michael Eager wrote:
> >> Is there a description of how to add a new processor architecture
> >> to QEMU?
On Sat, Aug 25, 2012 at 08:50:29AM -0700, Michael Eager wrote:
> On 08/25/2012 08:38 AM, 陳韋任 (Wei-Ren Chen) wrote:
> >> I want to add a new guest architecture.
> >>
> >> Is there any description of what the configuration options mean?
> >
> >Y
> My final goal is to obtain the memory access trace for a particular
> process in the guest, so your patch really helps, except for too many
> kernel _mmu events.
How do you know guest is running which process, and log it's memory
access trace?
Regards,
chenwj
--
Wei
(much like qemu), but VirtualBox worked surprisingly well and uses the
> CPU natively (no emulation, faster than my qemu without kvm).
IIRC, VirtualBox take approach similar to kqemu does, i.e.,
translate privilege instructions only and run non-privilege
instructions on host cpu directl
Hi Yeongkyoon,
> +#if defined(CONFIG_QEMU_LDST_OPTIMIZATION) && defined(CONFIG_SOFTMMU)
> +/* check whether the give addr is in TCG generated code buffer or not */
should be given.
Cheers,
chenwj
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Wei-Ren Chen (陳韋任)
Computer Systems Lab
On Wed, Oct 24, 2012 at 12:11:23PM +0900, Yeongkyoon Lee wrote:
> On 2012년 10월 24일 00:25, 陳韋任 (Wei-Ren Chen) wrote:
> > Hi Yeongkyoon,
> >
> >> +#if defined(CONFIG_QEMU_LDST_OPTIMIZATION) && defined(CONFIG_SOFTMMU)
> >> +/* check whether the give ad
slow-down of kernel boot after this set was applied.
Would you like to try to run some benchmark after the kernel booting? Like
Yeongkyoon Lee done with his qemu_ld/qemu_st work [1], EEMBC, nbench
, or even SPEC. ;)
Regards,
chenwj
[1] http://lists.gnu.org/archive/html/qemu-devel/2012-10/ms
o send your patchset. By deafult, `git send-mail`
should thread your patch together, which means every patch in the series
will be threaded to reply the first (cover) letter.
Regards,
chenwj
[1] http://wiki.qemu.org/Contribute/SubmitAPatch
--
Wei-Ren Chen (陳韋任)
Computer Systems Lab, Institute
ageBlob {
> +char *name;
> +target_phys_addr_t addr;
ditto.
Regards,
chenwj
[1]
http://git.qemu.org/qemu.git/commit/?id=51ef67270b1d10e1fcf3de7368dccad1ba0bf9d1
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Tel:886
uint8_t **data,
> + target_phys_addr_t *loadaddr)
^^
Use hwaddr instead. I guess you need rebase to the trunk which
replace target_phys_addr_t with hwaddr everywhere.
Regards,
chenwj
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Wei-Ren Chen (陳韋任)
Computer Systems Lab, Instit
from host memory
(4) Jump to next code (6)
(5) TLB miss case: call MMU helper
(6) ... (next code)
Do you mean we directly call MMU helper ing step 2?
Regards,
chenwj
[1] http://www.mail-archive.com/qemu-devel@nongnu.org/msg91294.html
--
Wei-Ren Chen (陳韋任)
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> Yes.
> But how to do that. I can't find the upload location or someone who
> receives the image.
Perhaps someone can open a wiki account for you, so that you can upload
an image.
Regards,
chenwj
--
Wei-Ren Chen (陳韋任)
Computer Systems Lab, Institute of Information Science,
A
indenpent code. Although we can get some_field by the following way,
int some_field = &env->some_field;
but it's not very convenient if we have many field of CPUState want to access.
Is
there a better way to do so? Thanks!
Regards,
chenwj
[1]
http://stackoverflow.com/questions/9
> HPA into EPT, that's the only way HW can help.
Regards,
chenwj
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Tel:886-2-2788-3799 #1667
Homepage: http://people.cs.nctu.edu.tw/~chenwj
Hi Li Zhang,
Perhaps you miss "[PATCH v3 1/2]" in the subject?
Regards,
chenwj
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we fill TLB, we add an offset to
the GPA to get HVA, then store GVA -> HVA mapping into the TLB (IIUC). I don't
see much differences here.
Regards,
chenwj
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main_loop_wait(nonblocking);
} while (!main_loop_should_exit());
// print env->some_field1
// print env->some_field2
}
---
If we can access env in vl.c directly, it would make the task easier.
Regards,
chenwj
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Wei-Ren Chen (陳韋任)
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function 'main_loop':
/tmp/chenwj/qemu/vl.c:1568:18: error: 'first_cpu' undeclared (first use in this
function)
---
Any thought on what I am missing? Thanks.
Regards,
chenwj
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CC'ed to the mailing list.
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Tel:886-2-2788-3799 #1667
Homepage: http://people.cs.nctu.edu.tw/~chenwj
--- Begin Message ---
On 06/19/2012 11:49 AM, 陳韋任 (Wei-Ren Chen) wrote:
>
On Tue, Jun 19, 2012 at 01:08:47PM +0100, Peter Maydell wrote:
> On 19 June 2012 12:54, 陳韋任 (Wei-Ren Chen) wrote:
> >> If you only have one CPU then using first_cpu->some_field1 should be
> >> almost as easy. :)
> >
> > I am afraid first_cpu (CPUArchStat
> > Does this pass scripts/checkpatch.pl? These should become
> > if (cop != 0) {
> > goto unrecognized;
> > }
> Thanks for pointing it out, and sorry for that.
> I will correct it in next version.
You can run scripts/checkpatch.pl before you submit the patch.
> + * OpenRISC simulator for use as an ISS.
^^^
Shoudld be IIS?
Regards,
chenwj
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Tel:886-2-2788-3799 #1667
Homepage: h
exec(), too?
Regards,
chenwj
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constant already, no? Or what do you mean.
I guess Orit means,
#define THRESHOLD 50
if (t1 > THRESHOLD) { ... }
Regards,
chenwj
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e these cases.
>
> I think in this case it's more likely to be the HELPER() macro
> that is confusing it, but yes, just ignore the error.
Should this be added to http://wiki.qemu.org/Contribute/SubmitAPatch
as an example? I remember someone else had the same problem before.
Regar
ut fetching instructions from the code cache, this
> has to happen in non-nested mode ?
When guest VM (with KVM enabled) fetch instructions from its memory,
does it also have the same issue?
Regards,
chenwj
[1] http://www.mail-archive.com/qemu-devel@nongnu.org/msg117254.html
--
Wei-
erations happen.
> >
> > This can make the emulator vulnerable in the security sense. Probably
> > Unicore CPUs are not used now in an environment where the guest can
> > not be trusted (like cloud computing), but who knows the future?
> Is it proper to print such i
dn't know what to make
> of the (usually 32-bit truncated) address. Passing in g2h(address) makes the
> guest process a lot happier.
Passing g2h or h2g? From the context and code, I think h2g should make more
sense.
Regards,
chenwj
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C
label(lab3);
???
How can this be done?
Regards,
chenwj
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Tel:886-2-2788-3799 #1667
Homepage: http://people.cs.nctu.edu.tw/~chenwj
Hi Liu,
You might find this thread interesting,
http://lists.gnu.org/archive/html/qemu-devel/2012-06/msg04351.html
Regards,
chenwj
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Homepage: http
ile which Bluestacks uses to run ARM apps. Perform a binary analysis,
and you will see it is in fact Qemu.
That might give you a hint. ;)
Regards,
chenwj
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Computer Systems Lab, Institute of Information Science,
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Tel:886-2-2788-3799 #1667
> /* OpenRISC pic handler */
> static void openrisc_pic_cpu_handler(void *opaque, int irq, int level)
> {
> OpenRISCCPU *cpu = (OpenRISCCPU *)opaque;
^^
Do we need casting before assigning opaque to cpu?
Regards,
chenwj
--
Wei-Ren Chen (陳
7;t "-d" option help you?
> 2. What's the corresponding folder/file(s) in the source code where I can add
> code for profiling?
target-arm/* would be the place since you're running ARM binary, tcg/ARCH/*
could be another place depends on what machine you're runn
never see such usage before.
Should be "For example"?
Regards,
chenwj
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. :-)
Regards,
chenwj
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Tel:886-2-2788-3799 #1667
Homepage: http://people.cs.nctu.edu.tw/~chenwj
> > Also, please line wrap your commit messages.
> I didn't know the line wrap rule of commit message. Is the rule included
> in checkpatch.pl? Let me check it.
I guess it's 80 char length rule?
Regards,
chenwj
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uld be something like,
8aca521512a14c439624191bd0a891c52f91b401
Regards,
chenwj
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mware.com/download/139/
The cost is quite high, ~800 cycles.
Regards,
chenwj
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gt; since Clang supports the ?: gcc extension this patch doesn't
> move us any further in that direction.
Let's get AVOID_PASS_ARGV0 patch done. ;)
Regards,
chenwj
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Tel
e
> 0x4d18: movzbl %bpl,%ebp
> 0x4d1c: mov0x8(%r14),%ebx
I believe this reply is too late, but it's LGTM. :)
>
> > The code between (a) and (b) is (almost) what TLB lookup hit/miss looks
> > like.
> > If TLB miss, it will call something like _
ed locally, and that your
> > change to just returning bool broke this. And in this version
> > of the patch there is still exactly the same problem.
>
> why broke?
> this function just ask if breakpoint 'i' was enable,
> so we answer enabled or not? 2 simple cases, any problem?
I don't read this patch from the starting. But Peter, do you mean
the return value matters here? I see the original version compares
the return value with 0x1, do you mean we *need* this comparsion here?
Regards,
chenwj
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, it my bring a error.
Why not use `git send-mail`? See more details on
http://wiki.qemu.org/Contribute/SubmitAPatch
Regards,
chenwj
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Tel:886-2-2788-3799 #1667
[CC'ed qemu-trivial]
ping?
On Wed, Nov 21, 2012 at 07:52:48AM +0800, 陳韋任 (Wei-Ren Chen) wrote:
> When tb_remove was first commited at fd6ce8f6, there were three different
> calls pass different names to offsetof. In current codebase, the other two
> calls are replaced with
27;t above helper function be called from the code cache?
The 3rd argument of do_raise_exception means if the exception comes
from code cache or not, iiuc. Is it correct to put zero here?
Regards,
chenwj
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Computer Systems Lab, Institute of Information Science,
Academia Sini
d.h:
> > No such file or directory
> >
> > (though for some reason not as a fatal error).
>
> Bizzare.
>
> Out of curiosity, does llvm ship a cpuid.h? Or am I going to be
> better off not relying on that header at all?
I don't think LLVM ship cpuid.h.
From the discussion on the ML [1], the exception limit defined by
magic number 0x100 is actually EXCP_SC defined in cpu.h. Replace the
magic number with EXCP_SC. Remove "#if 1 .. #endif" as well.
[1] http://lists.gnu.org/archive/html/qemu-devel/2012-11/msg03080.html
Signed-off-by: Chen Wei-Ren
l still show an
> old email address. Most email addresses have a limit life time.
Well... Just let him fix his mail address (he want it in the source
code). Maybe we can discuss if we want the mail address in the code
while reviewing new coming patch next time. ;)
Regards,
chenwj
--
Wei-Re
On Thu, Dec 13, 2012 at 08:22:06PM +0800, Pan Xueshu wrote:
> Because it has been disabled to create account on the wiki page. Thanks
> very much!
From IRC, I guess kwolf already did this for you?
Regards,
chenwj
--
Wei-Ren Chen (陳韋任)
Computer Systems Lab, Institute of Information S
ping? :-)
On Tue, Dec 11, 2012 at 12:15:55AM +0800, 陳韋任 (Wei-Ren Chen) wrote:
> From the discussion on the ML [1], the exception limit defined by
> magic number 0x100 is actually EXCP_SC defined in cpu.h. Replace the
> magic number with EXCP_SC. Remove "#if 1 .. #endif" as
On Tue, Dec 18, 2012 at 05:37:53PM +0100, Stefan Hajnoczi wrote:
> On Wed, Nov 21, 2012 at 07:52:48AM +0800, 陳韋任 (Wei-Ren Chen) wrote:
> > When tb_remove was first commited at fd6ce8f6, there were three different
> > calls pass different names to offsetof. In current codebase
, env->active_tc.PC, env->CP0_EPC, name);
}
...
}
Maybe we can do this way?
---
diff --git a/target-mips/cpu.h b/target-mips/cpu.h
index 31602ac..507a213 100644
--- a/target-mips/cpu.h
+++ b/target-mips/cpu.h
@@ -616,9 +616,9 @@ enum {
EXCP_DSPDIS,
EXCP_LAST = EXCP_DSPD
When tb_remove was first commited at fd6ce8f6, there were three different
calls pass different names to offsetof. In current codebase, the other two
calls are replaced with tb_page_remove. There is no need to have a general
tb_remove. Omit passing the third parameter and using tb1->phys_hash_next
or *mon)
> int64_t qemu_time;
> int64_t dev_time;
>
> -static void do_info_profile(Monitor *mon)
> +static void do_info_profile(Monitor *mon, const QDict *qdict)
> {
> int64_t total;
> total = qemu_time;
> @@ -1816,7 +1816,7 @@ static void do_info_profile(Monito
easurement, I
guess. The problem is how you get the time spent is the code cache. I
guess you have to spot where QEMU jump into the code cache, and
when/where it leave the code cache. Then insert your profiling code
there.
HTH,
chenwj
--
Wei-Ren Chen (陳韋任)
Computer Systems Lab, Institute of Infor
r. Would you interest in contributing
this part?
Regards,
chenwj
--
Wei-Ren Chen (陳韋任)
Computer Systems Lab, Institute of Information Science,
Academia Sinica, Taiwan (R.O.C.)
Tel:886-2-2788-3799 #1667
Homepage: http://people.cs.nctu.edu.tw/~chenwj
it.
>
> You can get some instructions here:
>
> https://projects.gso.ac.upc.edu/projects/qemu-dbi/wiki
The website is down. :/ Would you like to take a look on that?
Thanks.
Regards,
chenwj
--
Wei-Ren Chen (陳韋任)
Computer Systems Lab, Institute of Information Science,
Academia S
ach is a minor patch which fix a typo (I guess).
--
Wei-Ren Chen (陳韋任)
Computer Systems Lab, Institute of Information Science,
Academia Sinica, Taiwan (R.O.C.)
Tel:886-2-2788-3799 #1667
Homepage: http://people.cs.nctu.edu.tw/~chenwj
diff --git a/docs/instrumentation.txt b/docs/instrumentation.
]
--
Wei-Ren Chen (陳韋任)
Computer Systems Lab, Institute of Information Science,
Academia Sinica, Taiwan (R.O.C.)
Tel:886-2-2788-3799 #1667
Homepage: http://people.cs.nctu.edu.tw/~chenwj
> I would like to still submit our patches .
>
> Please advise.
>
> Out port is complete and already tested to a level which would be
> difficult for someone else to do that does not have access to our AVP
> test suite.
What about Jia's patch?
Regards,
che
wiki page so that people who want to be a
maintainer know what they should do. :)
Regards,
chenwj
--
Wei-Ren Chen (陳韋任)
Computer Systems Lab, Institute of Information Science,
Academia Sinica, Taiwan (R.O.C.)
Tel:886-2-2788-3799 #1667
Homepage: http://people.cs.nctu.edu.tw/~chenwj
#hellogcc on freenode
--
Wei-Ren Chen (陳韋任)
Computer Systems Lab, Institute of Information Science,
Academia Sinica, Taiwan (R.O.C.)
Tel:886-2-2788-3799 #1667
Homepage: http://people.cs.nctu.edu.tw/~chenwj
012-08/msg05037.html
I also think multithread support in qemu user mode is buggy, not only
the issue mentioned on above thread.
Regards,
chenwj
--
Wei-Ren Chen (陳韋任)
Computer Systems Lab, Institute of Information Science,
Academia Sinica, Taiwan (R.O.C.)
Tel:886-2-2788-3799 #1667
Homepage: http://people.cs.nctu.edu.tw/~chenwj
you confirm this? I am not sure how complete AMD SVM support
in QEMU. :)
Regards,
chenwj
[1] http://wiki.qemu.org/ChangeLog/old
--
Wei-Ren Chen (陳韋任)
Computer Systems Lab, Institute of Information Science,
Academia Sinica, Taiwan (R.O.C.)
Tel:886-2-2788-3799 #1667
Homepage: h
hive/html/qemu-devel/2012-09/msg00379.html
--
Wei-Ren Chen (陳韋任)
Computer Systems Lab, Institute of Information Science,
Academia Sinica, Taiwan (R.O.C.)
Tel:886-2-2788-3799 #1667
Homepage: http://people.cs.nctu.edu.tw/~chenwj
> Excuse me for asking, does TCG-IR use static single assignment (SSA) form?
>
> I just wanna know how to translate a register-based bytecode to TCG-IR.
Sounds like you need to take a look at target-xxx/translate.c ?
Regards,
chenwj
--
Wei-Ren Chen (陳韋任)
Computer Systems Lab, Ins
ill a good default? I am just wondering if those
boards with little memory still are major user of QEMU? :)
Regards,
chenwj
--
Wei-Ren Chen (陳韋任)
Computer Systems Lab, Institute of Information Science,
Academia Sinica, Taiwan (R.O.C.)
Tel:886-2-2788-3799 #1667
Homepage: http://people.cs.nctu.edu.tw/~chenwj
df
[2] http://tima-sls.imag.fr/www/research/qemu/simd-qemu/
[3] http://lists.gnu.org/archive/html/qemu-devel/2011-03/msg02065.html
Regards,
chenwj
--
Wei-Ren Chen (陳韋任)
Computer Systems Lab, Institute of Information Science,
Academia Sinica, Taiwan (R.O.C.)
Tel:886-2-2788-3799 #1667
Homepage:
On Wed, Mar 06, 2013 at 11:47:58AM +0800, Peter Maydell wrote:
> On 6 March 2013 11:30, 陳韋任 (Wei-Ren Chen) wrote:
> > While searching for QEMU SIMD issues, I found there was a paper presented
> > in 2011 [1], and the source code is also public on [2]. However, it seems
> >
In TCG, "target" means the host architecture for which TCG generates the
code. Using "guest" rather than "target" to make the document more consistent.
Signed-off-by: Chen Wei-Ren
---
tcg/README | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/tcg/README b/tcg/README
index 9
1 - 100 of 178 matches
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