From: Xingang Wang
The idmap of smmuv3 and root complex covers the whole RID space for now,
this patch add explicit idmap info according to root bus number range.
This add smmuv3 idmap for certain bus which has enabled the iommu property.
Signed-off-by: Xingang Wang
Signed-off-by: Jiahui Cen
-
From: Xingang Wang
This helps to find max bus number of a root bus.
Signed-off-by: Xingang Wang
Signed-off-by: Jiahui Cen
---
hw/pci/pci.c | 34 ++
include/hw/pci/pci.h | 1 +
2 files changed, 35 insertions(+)
diff --git a/hw/pci/pci.c b/hw/pci/pci.c
From: Xingang Wang
This add iommu option for pci root bus, including primary bus
and pxb root bus. The option is valid only if there is a virtual
iommu device.
Signed-off-by: Xingang Wang
Signed-off-by: Jiahui Cen
---
hw/arm/virt.c | 25 +
hw/i386
From: Xingang Wang
When building amd IVRS table, only devices attached to root bus with
IOMMU flag should be scanned.
Signed-off-by: Xingang Wang
Signed-off-by: Jiahui Cen
---
hw/i386/acpi-build.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/i386/acpi-build.c b/hw/i3
From: Xingang Wang
The pci host iommu property is useful to check whether
the iommu is enabled on the pci root bus.
Signed-off-by: Xingang Wang
Signed-off-by: Jiahui Cen
---
hw/pci/pci.c | 18 +-
hw/pci/pci_host.c | 2 ++
include/hw/pci/pci.h | 1 +
From: Xingang Wang
In DMAR table, the drhd is set to cover all pci devices when intel_iommu
is on. This patch add explicit scope data, including only the pci devices
that go through iommu.
Signed-off-by: Xingang Wang
Signed-off-by: Jiahui Cen
---
hw/i386/acpi-build.c | 68
From: Xingang Wang
These patches add support for configure iommu on/off for pci root bus,
including primary bus and pxb root bus. At present, All root bus
will go through iommu when iommu is configured, which is not flexible.
So this add option to enable/disable iommu for primary bus and pxb
roo
From: Xingang Wang
This helps to find max bus number of a root bus.
Signed-off-by: Xingang Wang
Signed-off-by: Jiahui Cen
---
hw/pci/pci.c | 34 ++
include/hw/pci/pci.h | 1 +
2 files changed, 35 insertions(+)
diff --git a/hw/pci/pci.c b/hw/pci/pci.c
From: Xingang Wang
This add iommu option for pci root bus, including primary bus
and pxb root bus. The option is valid only if there is a virtual
iommu device.
Signed-off-by: Xingang Wang
Signed-off-by: Jiahui Cen
---
hw/arm/virt.c | 25 +
hw/i386
From: Xingang Wang
The pci host iommu property is useful to check whether
the iommu is enabled on the pci root bus.
Signed-off-by: Xingang Wang
Signed-off-by: Jiahui Cen
---
hw/pci/pci.c | 18 +-
hw/pci/pci_host.c | 2 ++
include/hw/pci/pci.h | 1 +
From: Xingang Wang
These patches add support for configure iommu on/off for pci root bus,
including primary bus and pxb root bus. At present, All root bus
will go through iommu when iommu is configured, which is not flexible.
So this add option to enable/disable iommu for primary bus and pxb
roo
From: Xingang Wang
The idmap of smmuv3 and root complex covers the whole RID space for now,
this patch add explicit idmap info according to root bus number range.
This add smmuv3 idmap for certain bus which has enabled the iommu property.
Signed-off-by: Xingang Wang
Signed-off-by: Jiahui Cen
-
From: Xingang Wang
When building amd IVRS table, only devices attached to root bus with
IOMMU flag should be scanned.
Signed-off-by: Xingang Wang
Signed-off-by: Jiahui Cen
---
hw/i386/acpi-build.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/i386/acpi-build.c b/hw/i3
From: Xingang Wang
In DMAR table, the drhd is set to cover all pci devices when intel_iommu
is on. This patch add explicit scope data, including only the pci devices
that go through iommu.
Signed-off-by: Xingang Wang
Signed-off-by: Jiahui Cen
---
hw/i386/acpi-build.c | 68
Hi, everyone!
Do you have any suggestions about this iommu configuration feature?
Please help review these patches, thanks very much.
On 2021/3/25 15:22, Wang Xingang wrote:
From: Xingang Wang
These patches add support for configure iommu on/off for pci root bus,
including primary bus and
Hi Eric,
On 2021/4/13 1:36, Auger Eric wrote:
Hi Wang,
On 3/25/21 8:22 AM, Wang Xingang wrote:
From: Xingang Wang
The pci host iommu property is useful to check whether
the iommu is enabled on the pci root bus.
Signed-off-by: Xingang Wang
Signed-off-by: Jiahui Cen
---
hw/pci/pci.c
Hi Eric,
On 2021/4/13 1:36, Auger Eric wrote:
Hi Wang,
On 3/25/21 8:22 AM, Wang Xingang wrote:
From: Xingang Wang
This add iommu option for pci root bus, including primary bus
and pxb root bus. The option is valid only if there is a virtual
iommu device.
Signed-off-by: Xingang Wang
Signed
Hi Eric,
On 2021/3/10 18:18, Auger Eric wrote:
Hi Xingang,
On 3/10/21 3:13 AM, Wang Xingang wrote:
Hi Eric,
On 2021/3/9 22:36, Auger Eric wrote:
Hi,
On 2/27/21 9:33 AM, Wang Xingang wrote:
From: Xingang Wang
These patches add support for configure iommu on/off for pci root bus,
including
Hi Eric,
On 2021/3/10 18:25, Auger Eric wrote:
Hi Xingang,
On 2/27/21 9:33 AM, Wang Xingang wrote:
From: Xingang Wang
This Property can be useful to check whether this bus is attached to iommu.
Strictly speaking this is not a Property (QEMU property) but a flag
Signed-off-by: Xingang
Hi Eric,
On 2021/3/10 18:24, Auger Eric wrote:
Hi Xingang,
On 2/27/21 9:33 AM, Wang Xingang wrote:
From: Xingang Wang
This add iommu option for pci root bus, including primary bus
and pxb root bus. Default option is set to true, and the option
is valid only if the iommu option for machine
From: Xingang Wang
This add a bypass_iommu property for pci_expander_bridge.
The property can be used as:
qemu -device pxb-pcie,bus_nr=0x10,addr=0x1,bypass_iommu=true
Signed-off-by: Xingang Wang
---
hw/pci-bridge/pci_expander_bridge.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/hw/p
From: Xingang Wang
This add a bypass_iommu option for arm virt machine,
the option can be used in this manner:
qemu -machine virt,iommu=smmuv3,bypass_iommu=true
Signed-off-by: Xingang Wang
---
hw/arm/virt.c | 26 ++
include/hw/arm/virt.h | 1 +
2 files changed,
From: Xingang Wang
This helps to get the bus number range of a pci bridge hierarchy.
Signed-off-by: Xingang Wang
---
hw/pci/pci.c | 15 +++
include/hw/pci/pci.h | 1 +
2 files changed, 16 insertions(+)
diff --git a/hw/pci/pci.c b/hw/pci/pci.c
index 27d588e268..7f18ea5ef5
From: Xingang Wang
When building IVRS table, only devices which go through iommu
will be scanned, and the corresponding ivhd will be inserted.
Signed-off-by: Xingang Wang
---
hw/i386/acpi-build.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/i386/acpi-build.c b/hw/i386
From: Xingang Wang
This add a bypass_iommu property for pci host, which indicates
whether devices attached to the pci root bus will bypass iommu.
In pci_device_iommu_address_space(), add a bypass_iommu check
to avoid getting iommu address space for devices bypass iommu.
Signed-off-by: Xingang Wa
From: Xingang Wang
These patches add support for configure bypass_iommu on/off for
pci root bus, including primary bus and pxb root bus. At present,
all root bus will go through iommu when iommu is configured,
which is not flexible, because in many situations the need for using
iommu and bypass i
From: Xingang Wang
Add a bypass_iommu pc machine option to bypass iommu translation
for the primary root bus.
The option can be used as manner:
qemu-system-x86_64 -machine q35,bypass_iommu=true
Signed-off-by: Xingang Wang
---
hw/i386/pc.c | 18 ++
hw/pci-host/q35.c|
From: Xingang Wang
In DMAR table, the drhd is set to cover all pci devices when intel_iommu
is on. This patch add explicit scope data, including only the pci devices
that go through iommu.
Signed-off-by: Xingang Wang
---
hw/i386/acpi-build.c | 68 ++--
1
From: Xingang Wang
This add explicit IORT idmap info according to pci root bus number
range, and only add smmu idmap for those which does not bypass iommu.
For idmap directly to ITS node, this split the whole RID mapping to
smmu idmap and its idmap. So this should cover the whole idmap for
throu
Hi, everyone! Do you have any suggestions? Please help review these
patches, thanks very much.
On 2021/2/27 16:33, Wang Xingang wrote:
From: Xingang Wang
These patches add support for configure iommu on/off for pci root bus,
including primary bus and pxb root bus. At present, All root bus
Hi Eric,
On 2021/3/9 22:36, Auger Eric wrote:
Hi,
On 2/27/21 9:33 AM, Wang Xingang wrote:
From: Xingang Wang
These patches add support for configure iommu on/off for pci root bus,
including primary bus and pxb root bus. At present, All root bus will go
through iommu when iommu is configured
From: Xingang Wang
These patches add support for configure bypass_iommu on/off for
pci root bus, including primary bus and pxb root bus. At present,
All root bus will go through iommu when iommu is configured,
which is not flexible, because in many situations the need for using
iommu and bypass i
From: Xingang Wang
This add a bypass_iommu property for pci host, which indicates
whether devices attached to the pci root bus will bypass iommu.
In pci_device_iommu_address_space(), add a bypass_iommu check
to avoid getting iommu address space for devices bypass iommu.
Signed-off-by: Xingang Wa
From: Xingang Wang
Add a bypass_iommu pc machine option to bypass iommu translation
for the primary root bus.
The option can be used as manner:
qemu-system-x86_64 -machine q35,bypass_iommu=true
Signed-off-by: Xingang Wang
Signed-off-by: Jiahui Cen
---
hw/i386/pc.c | 18 +++
From: Xingang Wang
This add a bypass_iommu option for arm virt machine,
the option can be used in this manner:
qemu -machine virt,iommu=smmuv3,bypass_iommu=true
Signed-off-by: Xingang Wang
Signed-off-by: Jiahui Cen
---
hw/arm/virt.c | 26 ++
include/hw/arm/virt
From: Xingang Wang
When building IVRS table, only devices which go through iommu
will be scanned, and the corresponding ivhd will be inserted.
Signed-off-by: Xingang Wang
Signed-off-by: Jiahui Cen
---
hw/i386/acpi-build.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/
From: Xingang Wang
In DMAR table, the drhd is set to cover all pci devices when intel_iommu
is on. This patch add explicit scope data, including only the pci devices
that go through iommu.
Signed-off-by: Xingang Wang
Signed-off-by: Jiahui Cen
---
hw/i386/acpi-build.c | 68
From: Xingang Wang
This add a bypass_iommu property for pci_expander_bridge.
The property can be used as:
qemu -device pxb-pcie,bus_nr=0x10,addr=0x1,bypass_iommu=true
Signed-off-by: Xingang Wang
Signed-off-by: Jiahui Cen
---
hw/pci-bridge/pci_expander_bridge.c | 3 +++
1 file changed, 3 inser
From: Xingang Wang
This helps to get the bus number range of a pci bridge hierarchy.
Signed-off-by: Xingang Wang
Signed-off-by: Jiahui Cen
---
hw/pci/pci.c | 15 +++
include/hw/pci/pci.h | 1 +
2 files changed, 16 insertions(+)
diff --git a/hw/pci/pci.c b/hw/pci/pci.c
in
From: Xingang Wang
This add explicit IORT idmap info according to pci root bus number
range, and only add smmu idmap for those which does not bypass iommu.
For idmap directly to ITS node, this split the whole RID mapping to
smmu idmap and its idmap. So this should cover the whole idmap for
throu
From: Xingang Wang
These patches add support for configure iommu on/off for pci root bus,
including primary bus and pxb root bus. At present, All root bus will go
through iommu when iommu is configured, which is not flexible.
So this add option to enable/disable iommu for primary bus and pxb roo
From: Xingang Wang
This property can be useful to check whether this bus is attached to iommu.
Signed-off-by: Xingang Wang
Signed-off-by: Jiahui Cen
---
include/hw/pci/pci_bus.h | 13 +
1 file changed, 13 insertions(+)
diff --git a/include/hw/pci/pci_bus.h b/include/hw/pci/pci_bu
From: Xingang Wang
This helps to find max bus number of a root bus.
Signed-off-by: Xingang Wang
Signed-off-by: Jiahui Cen
---
hw/pci/pci.c | 33 +
include/hw/pci/pci.h | 1 +
2 files changed, 34 insertions(+)
diff --git a/hw/pci/pci.c b/hw/pci/pci.c
i
From: Xingang Wang
This add iommu option for pci root bus, including primary bus
and pxb root bus. Default option is set to true, and the option
is valid only if the iommu option for machine is properly set.
Signed-off-by: Xingang Wang
Signed-off-by: Jiahui Cen
---
hw/arm/virt.c
From: Xingang Wang
The idmap of smmuv3 and root complex covers the whole RID space for now,
this patch add explicit idmap info according to root bus number range.
This add smmuv3 idmap for certain bus which has enabled the iommu property.
Signed-off-by: Xingang Wang
Signed-off-by: Jiahui Cen
-
From: Xingang Wang
This Property can be useful to check whether this bus is attached to iommu.
Signed-off-by: Xingang Wang
Signed-off-by: Jiahui Cen
---
include/hw/pci/pci_bus.h | 13 +
1 file changed, 13 insertions(+)
diff --git a/include/hw/pci/pci_bus.h b/include/hw/pci/pci_bu
From: Xingang Wang
This helps to find max bus number of a root bus.
Signed-off-by: Xingang Wang
Signed-off-by: Jiahui Cen
---
hw/pci/pci.c | 33 +
include/hw/pci/pci.h | 1 +
2 files changed, 34 insertions(+)
diff --git a/hw/pci/pci.c b/hw/pci/pci.c
i
From: Xingang Wang
The idmap of smmuv3 and root complex covers the whole RID space for now,
this patch add explicit idmap info according to root bus number range.
This add smmuv3 idmap for certain bus which has enabled the iommu property.
Signed-off-by: Xingang Wang
Signed-off-by: Jiahui Cen
-
From: Xingang Wang
These patches add support for configure iommu on/off for pci root bus,
including primary bus and pxb root bus. At present, All root bus will go
through iommu when iommu is configured, which is not flexible.
So this add option to enable/disable iommu for primary bus and pxb roo
From: Xingang Wang
This add iommu option for pci root bus, including primary bus
and pxb root bus. Default option is set to true, and the option
is valid only if the iommu option for machine is properly set.
Signed-off-by: Xingang Wang
Signed-off-by: Jiahui Cen
---
hw/arm/virt.c
From: Xingang Wang
This patch series add fix for pxb support dma
1. Add _CCA attribute for pxb DSDT, because cache coherency attribute is
needed when check dma support for pxb device.
2. Update DSDT.pxb file
Xingang Wang (3):
acpi: Allow pxb DSDT acpi table changes
acpi/gpex: Fix cca attribu
From: Xingang Wang
Signed-off-by: Jiahui Cen
Signed-off-by: Xingang Wang
---
tests/qtest/bios-tables-test-allowed-diff.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/tests/qtest/bios-tables-test-allowed-diff.h
b/tests/qtest/bios-tables-test-allowed-diff.h
index dfb8523c8b..90c53925fc 1
From: Xingang Wang
A new _CCA attribute is added.
Update expected DSDT files accordingly, and re-enable their testing.
Full diff of changed files disassembly:
*
* Disassembling to symbolic ASL+ operators
*
- * Disassembly of DSDT.pxb, Thu Feb 4 21:07:42 2021
+ * Disassembly of DSDT.pxb,
From: Xingang Wang
When check DMA support for device attached to pxb,
the cache coherency attribute need to be set.
This add _CCA attribute for pxb DSDT.
Fixes: 6f9765fbad ("acpi/gpex: Build tables for pxb")
Signed-off-by: Jiahui Cen
Signed-off-by: Xingang Wang
---
hw/pci-host/gpex-acpi.c |
From: Xingang Wang
Add a bypass_iommu property for pci_expander_bridge, the property
is used to indicate whether pxb root bus will bypass iommu. By
default the bypass_iommu is disabled, and it can be enabled with:
qemu -device pxb-pcie,bus_nr=0x10,addr=0x1,bypass_iommu=true
Signed-off-by: Xingan
From: Xingang Wang
Signed-off-by: Xingang Wang
---
docs/bypass-iommu.txt | 89 +++
1 file changed, 89 insertions(+)
create mode 100644 docs/bypass-iommu.txt
diff --git a/docs/bypass-iommu.txt b/docs/bypass-iommu.txt
new file mode 100644
index 00
From: Xingang Wang
In DMAR table, the drhd is set to cover all PCI devices when intel_iommu
is on. To support bypass iommu feature, we need to walk the PCI bus with
bypass_iommu disabled and add explicit scope data in DMAR drhd structure.
/mnt/sdb/wxg/qemu-next/qemu/build/x86_64-softmmu/qemu-sys
From: Xingang Wang
This helps to get the min and max bus number of a PCI bus hierarchy.
Signed-off-by: Xingang Wang
Reviewed-by: Eric Auger
---
hw/pci/pci.c | 16
include/hw/pci/pci.h | 1 +
2 files changed, 17 insertions(+)
diff --git a/hw/pci/pci.c b/hw/pci/pci.c
From: Xingang Wang
When we build IORT table with SMMUv3 and bypass iommu feature enabled,
we can no longer setup one map from RC to SMMUv3 covering the whole RIDs.
We need to walk the PCI bus and check whether the root bus will bypass
iommu, setup RC -> SMMUv3 -> ITS map for RC which will not byp
From: Xingang Wang
Add a new bypass_iommu property for PCI host and use it to check
whether devices attached to the PCI root bus will bypass iommu.
In pci_device_iommu_address_space(), check the property and
avoid getting iommu address space for devices bypass iommu.
Signed-off-by: Xingang Wang
From: Xingang Wang
Traditionally, there is a global switch to enable/disable vIOMMU. All
devices in the system can only support go through vIOMMU or not, which
is not flexible. We introduce this bypass iommu property to support
coexist of devices go through vIOMMU and devices not. This is useful
From: Xingang Wang
Add a default_bus_bypass_iommu machine option to enable/disable
bypass_iommu for default root bus. The option is disabled by
default and can be enabled with:
$QEMU -machine virt,iommu=smmuv3,default_bus_bypass_iommu=true
Signed-off-by: Xingang Wang
---
hw/arm/virt.c
From: Xingang Wang
Check bypass_iommu to exclude the devices which will bypass iommu.
Signed-off-by: Xingang Wang
---
hw/i386/acpi-build.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/i386/acpi-build.c b/hw/i386/acpi-build.c
index 1b972b4913..7c888f05bf 100644
--- a/h
From: Xingang Wang
Add a default_bus_bypass_iommu pc machine option to enable/disable
bypass_iommu for default root bus. The option is disabled by default
and can be enabled with:
$QEMU -machine q35,default_bus_bypass_iommu=true
Signed-off-by: Xingang Wang
---
hw/i386/pc.c | 20 +++
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