[PATCH v2 6/9] Hexagon (target/hexagon) Add v69 HVX instructions

The following instructions are added V6_vasrvuhubrndsat V6_vasrvuhubsat V6_vasrvwuhrndsat V6_vasrvwuhsat V6_vassign_tmp V6_vcombine_tmp V6_vmpyuhvs Signed-off-by: Taylor Simpson Reviewed-by: Anton Johansson --- target/hexagon/gen_tcg_hvx.h | 12

[PATCH v2 04/21] Hexagon (target/hexagon) Add overrides for allocframe/deallocframe

These instructions have implicit writes to registers, so we don't want them to be helpers when idef-parser is off. Signed-off-by: Taylor Simpson Reviewed-by: Richard Henderson --- target/hexagon/gen_tcg.h | 32 +++ target/hexagon/genptr.c

[PATCH v2 12/21] Hexagon (target/hexagon) Short-circuit packet predicate writes

rly-exit from gen_pred_writes. Signed-off-by: Taylor Simpson Reviewed-by: Richard Henderson --- target/hexagon/genptr.h| 1 + target/hexagon/genptr.c| 15 --- target/hexagon/translate.c | 14 +++--- 3 files changed, 24 insertions(+), 6 deletions(-) diff --git a/tar

[PATCH v2 13/21] Hexagon (target/hexagon) Short-circuit packet HVX writes

In certain cases, we can avoid the overhead of writing to future_VRegs and write directly to VRegs. We consider HVX reads/writes when computing ctx->need_commit. Then, we can early-exit from gen_commit_hvx. Signed-off-by: Taylor Simpson Reviewed-by: Richard Henderson --- target/hexa

[PATCH v2 17/21] Hexagon (target/hexagon) Move new_value to DisasContext

The new_value array in the CPUHexagonState is only used for bookkeeping within the translation of a packet. With recent changes that eliminate the need to free TCGv variables, these make more sense to be transient and kept in DisasContext. Suggested-by: Richard Henderson Signed-off-by: Taylor

[PATCH v2 00/21] Hexagon (target/hexagon) short-circuit and move to DisasContext

_not_i64 + tcg_gen_and_i64 to tcg_gen_andc_i64 Use full constant in gen_slotval Taylor Simpson (21): meson.build Add CONFIG_HEXAGON_IDEF_PARSER Hexagon (target/hexagon) Add DisasContext arg to gen_log_reg_write Hexagon (target/hexagon) Add overrides for loop setup instructions Hexagon (target

[PATCH v2 03/21] Hexagon (target/hexagon) Add overrides for loop setup instructions

These instructions have implicit writes to registers, so we don't want them to be helpers when idef-parser is off. Signed-off-by: Taylor Simpson Acked-by: Richard Henderson --- target/hexagon/gen_tcg.h | 21 +++ target/hexagon/genptr.c

[PATCH v2 15/21] Hexagon (target/hexagon) Add overrides for disabled idef-parser insns

cases added to tests/tcg/hexagon/read_write_overlap.c Signed-off-by: Taylor Simpson Reviewed-by: Richard Henderson --- target/hexagon/gen_tcg.h | 18 target/hexagon/genptr.c| 99 ++ tests/tcg/hexagon/read_write_overlap.c | 136

[PATCH v2 09/21] Hexagon (target/hexagon) Don't overlap dest writes with source reads

When generating TCG, make sure we have read all the operand registers before writing to the destination registers. This is a prerequesite for short-circuiting where the source and dest operands could be the same. Signed-off-by: Taylor Simpson Reviewed-by: Richard Henderson --- target/hexagon

[PATCH v2 14/21] Hexagon (target/hexagon) Short-circuit more HVX single instruction packets

ction is an HVX instruction with a generated helper. We add an override for V6_vcombine so that it can be short-circuited along with a test case in tests/tcg/hexagon/hvx_misc.c Signed-off-by: Taylor Simpson --- target/hexagon/gen_tcg_hvx.h| 23 +++ target/hexagon/transl

[PATCH v2 07/21] Hexagon (target/hexagon) Eliminate uses of log_pred_write function

These instructions have implicit writes to registers, so we don't want them to be helpers when idef-parser is off. The following instructions are overriden S2_cabacdecbin SA1_cmpeqi Remove the log_pred_write function from op_helper.c Remove references in macros.h Signed-off-by: T

[PATCH v2 21/21] Hexagon (target/hexagon) Move items to DisasContext

branch_taken this_PC Suggested-by: Richard Henderson Signed-off-by: Taylor Simpson Reviewed-by: Richard Henderson --- target/hexagon/cpu.h | 3 --- target/hexagon/helper.h| 2 +- target/hexagon/macros.h| 6 +- target/hexagon/translate.h | 5 ++--- target/hexagon/genptr.c

[PATCH v2 05/21] Hexagon (target/hexagon) Add overrides for clr[tf]new

These instructions have implicit reads from p0, so we don't want them in helpers when idef-parser is off. Signed-off-by: Taylor Simpson --- target/hexagon/gen_tcg.h | 16 target/hexagon/macros.h | 4 2 files changed, 16 insertions(+), 4 deletions(-) diff --git a/t

[PATCH v2 19/21] Hexagon (target/hexagon) Move pred_written to DisasContext

: Taylor Simpson Reviewed-by: Richard Henderson --- target/hexagon/cpu.h | 2 -- target/hexagon/helper.h| 2 +- target/hexagon/translate.h | 2 +- target/hexagon/genptr.c| 2 +- target/hexagon/op_helper.c | 5 +++-- target/hexagon/translate.c | 9 - 6 files changed, 10

[PATCH v2 08/21] Hexagon (target/hexagon) Clean up pred_written usage

later in this series, so we mark it with G_GNUC_UNUSED. Signed-off-by: Taylor Simpson Reviewed-by: Richard Henderson --- target/hexagon/genptr.c| 16 +--- target/hexagon/translate.c | 53 -- 2 files changed, 23 insertions(+), 46 deletions(-) diff

[PATCH v2 01/21] meson.build Add CONFIG_HEXAGON_IDEF_PARSER

Enable conditional compilation depending on whether idef-parser is configured Signed-off-by: Taylor Simpson --- meson.build | 1 + 1 file changed, 1 insertion(+) diff --git a/meson.build b/meson.build index c44d05a13f..d4e438b033 100644 --- a/meson.build +++ b/meson.build @@ -1859,6 +1859,7

[PATCH v2 10/21] Hexagon (target/hexagon) Mark registers as read during packet analysis

Have gen_analyze_funcs mark the registers that are read by the instruction. We also mark the implicit reads using instruction attributes. Signed-off-by: Taylor Simpson Reviewed-by: Richard Henderson --- target/hexagon/translate.h | 36 +++ target/hexagon

[PATCH v2 06/21] Hexagon (target/hexagon) Remove log_reg_write from op_helper.[ch]

With the overrides added in prior commits, this function is not used Remove references in macros.h Signed-off-by: Taylor Simpson Reviewed-by: Richard Henderson --- target/hexagon/macros.h| 14 -- target/hexagon/op_helper.h | 4 target/hexagon/op_helper.c | 17

[PATCH v2 18/21] Hexagon (target/hexagon) Move new_pred_value to DisasContext

: Taylor Simpson Reviewed-by: Richard Henderson --- target/hexagon/cpu.h| 1 - target/hexagon/gen_tcg.h| 12 ++-- target/hexagon/translate.h | 2 +- target/hexagon/genptr.c | 10 +++--- target/hexagon/idef

[PATCH v2 16/21] Hexagon (target/hexagon) Make special new_value for USR

Precursor to moving new_value from the global state to DisasContext USR will need to stay in the global state because some helpers will set it's value Signed-off-by: Taylor Simpson Reviewed-by: Richard Henderson --- target/hexagon/cpu.h| 1 + target/hexagon/genptr.h

[PATCH v2 02/21] Hexagon (target/hexagon) Add DisasContext arg to gen_log_reg_write

Add DisasContext arg to gen_log_reg_write_pair also Signed-off-by: Taylor Simpson Reviewed-by: Richard Henderson --- target/hexagon/gen_tcg.h| 2 +- target/hexagon/genptr.h | 2 +- target/hexagon/genptr.c | 10 +- target

[PATCH v2 11/21] Hexagon (target/hexagon) Short-circuit packet register writes

BEFORE: 004000b4 movi_i32 new_r0,$0x1 mov_i32 r0,new_r0 AFTER: 004000b4 movi_i32 r0,$0x1 This patch reintroduces a use of check_for_attrib, so we remove the G_GNUC_UNUSED added earlier in this series. Signed-off-by: Taylor Simpson Reviewed-by: Richard Henderson --- target/hexag

[PATCH v2 20/21] Hexagon (target/hexagon) Move pkt_has_store_s1 to DisasContext

into a single argument called slotval. Suggested-by: Richard Henderson Signed-off-by: Taylor Simpson Reviewed-by: Richard Henderson --- target/hexagon/cpu.h| 1 - target/hexagon/macros.h | 16 target/hexagon/op_helper.h | 12

RE: [PATCH] target/hexagon: fix = vs. == mishap

> -Original Message- > From: Richard Henderson > Sent: Thursday, April 27, 2023 8:33 AM > To: Paolo Bonzini ; qemu-devel@nongnu.org > Cc: Taylor Simpson > Subject: Re: [PATCH] target/hexagon: fix = vs. == mishap > > WARNING: This email originated from outsid

RE: [PATCH] target/hexagon: fix = vs. == mishap

> -Original Message- > From: Taylor Simpson > Sent: Thursday, April 27, 2023 6:05 PM > To: Richard Henderson ; Paolo Bonzini > ; qemu-devel@nongnu.org > Subject: RE: [PATCH] target/hexagon: fix = vs. == mishap > > > > > -Original Message- >

[PATCH v2] target/hexagon: fix = vs. == mishap

From: Paolo Bonzini Changes in v2 Fix yyassert's for sign and zero extends Coverity reports a parameter that is "set but never used". This is caused by an assignment operator being used instead of equality. Co-authored-by: Taylor Simpson Signed-off-by: Paolo Bonzini

RE: [PATCH v2] Hexagon (target/hexagon) Additional instructions handled by idef-parser

> -Original Message- > From: Anton Johansson > Sent: Friday, April 28, 2023 11:25 AM > To: Taylor Simpson ; qemu-devel@nongnu.org > Cc: richard.hender...@linaro.org; phi...@linaro.org; a...@rev.ng; Brian Cain > ; Matheus Bernardino (QUIC) > > Subject: Re: [P

RE: [PATCH v2] target/hexagon: fix = vs. == mishap

> -Original Message- > From: Paolo Bonzini > Sent: Saturday, April 29, 2023 7:24 AM > To: Taylor Simpson ; qemu-devel@nongnu.org > Cc: richard.hender...@linaro.org; phi...@linaro.org; a...@rev.ng; > a...@rev.ng; Brian Cain ; Matheus Bernardino (QUIC) > > Subjec

RE: [PATCH v2] target/hexagon: fix = vs. == mishap

> -Original Message- > From: Peter Maydell > Sent: Saturday, April 29, 2023 4:27 AM > To: Taylor Simpson > Cc: qemu-devel@nongnu.org; pbonz...@redhat.com; > richard.hender...@linaro.org; phi...@linaro.org; a...@rev.ng; > a...@rev.ng; Brian Cain ; Matheus Bernardin

RE: [PATCH v2 0/9] Hexagon (target/hexagon) New architecture support

> -Original Message- > From: Richard Henderson > Sent: Friday, April 28, 2023 4:45 PM > To: Taylor Simpson ; qemu-devel@nongnu.org > Cc: phi...@linaro.org; a...@rev.ng; a...@rev.ng; Brian Cain > ; Matheus Bernardino (QUIC) > > Subject: Re: [PATCH v2 0/9] Hexa

RE: [PATCH v2] Hexagon (target/hexagon) Additional instructions handled by idef-parser

> -Original Message- > From: Taylor Simpson > Sent: Friday, April 28, 2023 3:53 PM > To: a...@rev.ng; qemu-devel@nongnu.org > Cc: richard.hender...@linaro.org; phi...@linaro.org; a...@rev.ng; Brian Cain > ; Matheus Bernardino (QUIC) > > Subject: RE: [PATCH v2]

[PATCH v3] Hexagon (target/hexagon) Additional instructions handled by idef-parser

gen_rvalue_extend gen_cast_op imm_print lexer properly sets size/signedness of constants Test cases added to tests/tcg/hexagon/fpstuff.c Signed-off-by: Taylor Simpson --- target/hexagon/idef-parser/parser-helpers.h | 2 +- target/hexagon/idef-parser/parser-helpers.c | 41 +++- tests

RE: [PATCH 3/9] target/Hexagon: Finish conversion to tcg_gen_qemu_{ld,st}_*

> -Original Message- > From: Richard Henderson > Sent: Tuesday, May 2, 2023 8:58 AM > To: qemu-devel@nongnu.org > Cc: mrol...@gmail.com; edgar.igles...@gmail.com; Taylor Simpson > ; a...@rev.ng; a...@rev.ng; laur...@vivier.eu; > phi...@linaro.org; jiaxun

RE: [PATCH 9/9] tcg: Remove compatability helpers for qemu ld/st

> -Original Message- > From: Richard Henderson > Sent: Tuesday, May 2, 2023 8:58 AM > To: qemu-devel@nongnu.org > Cc: mrol...@gmail.com; edgar.igles...@gmail.com; Taylor Simpson > ; a...@rev.ng; a...@rev.ng; laur...@vivier.eu; > phi...@linaro.org; jiaxun

RE: [PATCH 3/9] target/Hexagon: Finish conversion to tcg_gen_qemu_{ld,st}_*

> -Original Message- > From: Richard Henderson > Sent: Tuesday, May 2, 2023 10:49 AM > To: Taylor Simpson ; qemu-devel@nongnu.org > Subject: Re: [PATCH 3/9] target/Hexagon: Finish conversion to > tcg_gen_qemu_{ld,st}_* > > On 5/2/23 16:

RE: [PATCH v3] Hexagon (target/hexagon) Additional instructions handled by idef-parser

> -Original Message- > From: Anton Johansson > Sent: Tuesday, May 2, 2023 6:12 AM > To: Taylor Simpson ; qemu-devel@nongnu.org > Cc: richard.hender...@linaro.org; phi...@linaro.org; a...@rev.ng; Brian Cain > ; Matheus Bernardino (QUIC) > > Subject: Re: [P

RE: [PATCH] Hexagon (target/hexagon/*.py): raise exception on reg parsing error

> -Original Message- > From: Matheus Tavares Bernardino > Sent: Thursday, May 4, 2023 11:18 AM > To: qemu-devel@nongnu.org > Cc: a...@rev.ng; Taylor Simpson ; a...@rev.ng > Subject: [PATCH] Hexagon (target/hexagon/*.py): raise exception on reg > parsing error >

RE: [PATCH] Hexagon (decode): look for pkts with multiple insns at the same slot

> -Original Message- > From: Matheus Tavares Bernardino > Sent: Thursday, May 4, 2023 1:57 PM > To: qemu-devel@nongnu.org > Cc: Taylor Simpson > Subject: [PATCH] Hexagon (decode): look for pkts with multiple insns at the > same slot > > Each slot in a p

RE: [PATCH 2/2] Hexagon: append eflags to unknown cpu model string

> -Original Message- > From: Matheus Tavares Bernardino > Sent: Thursday, May 4, 2023 1:53 PM > To: qemu-devel@nongnu.org > Cc: Brian Cain ; Taylor Simpson > ; Laurent Vivier > Subject: [PATCH 2/2] Hexagon: append eflags to unknown cpu model string > >

RE: [PATCH 1/2] Hexagon: list available CPUs with `-cpu help`

> -Original Message- > From: Matheus Tavares Bernardino > Sent: Thursday, May 4, 2023 1:53 PM > To: qemu-devel@nongnu.org > Cc: Brian Cain ; Taylor Simpson > > Subject: [PATCH 1/2] Hexagon: list available CPUs with `-cpu help` > > Currently, qemu-hexa

RE: [PATCH 0/2] Hexagon: improve output for arch version debugging

> -Original Message- > From: Matheus Tavares Bernardino > Sent: Thursday, May 4, 2023 1:53 PM > To: qemu-devel@nongnu.org > Cc: Brian Cain ; Taylor Simpson > > Subject: [PATCH 0/2] Hexagon: improve output for arch version debugging > > If we run qemu with

[PULL v2 05/44] Hexagon (tests/tcg/hexagon) Add v68 HVX tests

Signed-off-by: Taylor Simpson Reviewed-by: Anton Johansson Message-Id: <20230427224057.3766963-6-tsimp...@quicinc.com> --- tests/tcg/hexagon/v68_hvx.c | 90 + tests/tcg/hexagon/v6mpy_ref.c.inc | 161 ++ tests/tcg/hexagon/Makefile.target

[PULL v2 11/44] Hexagon (target/hexagon) Add DisasContext arg to gen_log_reg_write

Add DisasContext arg to gen_log_reg_write_pair also Signed-off-by: Taylor Simpson Reviewed-by: Richard Henderson Message-Id: <20230427230012.3800327-3-tsimp...@quicinc.com> --- target/hexagon/gen_tcg.h| 2 +- target/hexagon/genptr.h | 2 +-

[PULL v2 27/44] Hexagon (target/hexagon) Move new_pred_value to DisasContext

: Taylor Simpson Reviewed-by: Richard Henderson Message-Id: <20230427230012.3800327-19-tsimp...@quicinc.com> --- target/hexagon/cpu.h| 1 - target/hexagon/gen_tcg.h| 12 ++-- target/hexagon/translate.h | 2 +- target/h

[PULL v2 32/44] target/hexagon: fix = vs. == mishap

From: Paolo Bonzini Changes in v2 Fix yyassert's for sign and zero extends Coverity reports a parameter that is "set but never used". This is caused by an assignment operator being used instead of equality. Co-authored-by: Taylor Simpson Signed-off-by: Paolo Bonzini

[PULL v2 00/44] Hexagon update

sns at the same slot gdbstub: only send stop-reply packets when allowed to gdbstub: add test for untimely stop-reply packets Hexagon: add core gdbstub xml data for LLDB Hexagon (linux-user/hexagon): handle breakpoints Paolo Bonzini (1): target/hexagon: fix = vs. == mi

[PULL v2 06/44] Hexagon (target/hexagon) Add v69 HVX instructions

The following instructions are added V6_vasrvuhubrndsat V6_vasrvuhubsat V6_vasrvwuhrndsat V6_vasrvwuhsat V6_vassign_tmp V6_vcombine_tmp V6_vmpyuhvs Signed-off-by: Taylor Simpson Reviewed-by: Anton Johansson Message-Id: <20230427224057.3766963-7-tsimp...@quicinc.

[PULL v2 25/44] Hexagon (target/hexagon) Make special new_value for USR

Precursor to moving new_value from the global state to DisasContext USR will need to stay in the global state because some helpers will set it's value Signed-off-by: Taylor Simpson Reviewed-by: Richard Henderson Message-Id: <20230427230012.3800327-17-tsimp...@quicinc.com> --- tar

[PULL v2 02/44] Hexagon (target/hexagon) Add v68 scalar instructions

The encodings for these instructions changed some "don't care" bits L2_loadw_locked L4_loadd_locked S2_storew_locked S4_stored_locked Signed-off-by: Taylor Simpson Reviewed-by: Anton Johansson Message-Id: <20230427224057.3766963-3-tsimp...@quicinc.com> ---

[PULL v2 23/44] Hexagon (target/hexagon) Short-circuit more HVX single instruction packets

ction is an HVX instruction with a generated helper. We add an override for V6_vcombine so that it can be short-circuited along with a test case in tests/tcg/hexagon/hvx_misc.c Signed-off-by: Taylor Simpson Reviewed-by: Richard Henderson Message-Id: <20230427230012.3800327-15-tsimp...@qui

[PULL v2 30/44] Hexagon (target/hexagon) Move items to DisasContext

branch_taken this_PC Suggested-by: Richard Henderson Signed-off-by: Taylor Simpson Reviewed-by: Richard Henderson Message-Id: <20230427230012.3800327-22-tsimp...@quicinc.com> --- target/hexagon/cpu.h | 3 --- target/hexagon/helper.h| 2 +- target/hexagon/macros.h

[PULL v2 21/44] Hexagon (target/hexagon) Short-circuit packet predicate writes

rly-exit from gen_pred_writes. Signed-off-by: Taylor Simpson Reviewed-by: Richard Henderson Message-Id: <20230427230012.3800327-13-tsimp...@quicinc.com> --- target/hexagon/genptr.h| 1 + target/hexagon/genptr.c| 15 --- target/hexagon/translate.c | 14 +++---

[PULL v2 04/44] Hexagon (target/hexagon) Add v68 HVX instructions

The following instructions are added V6_v6mpyvubs10_vxx V6_v6mpyhubs10_vxx V6_v6mpyvubs10 V6_v6mpyhubs10 Signed-off-by: Taylor Simpson Reviewed-by: Anton Johansson Message-Id: <20230427224057.3766963-5-tsimp...@quicinc.com> --- target/hexagon/mmvec/macros.h

[PULL v2 38/44] Remove test_vshuff from hvx_misc tests

Reviewed-by: Taylor Simpson Tested-by: Taylor Simpson Signed-off-by: Taylor Simpson Message-Id: <20230509184231.2467626-1-quic_mlie...@quicinc.com> --- tests/tcg/hexagon/hvx_misc.c | 45 1 file changed, 45 deletions(-) diff --git a/tests/tcg/hexagon/hvx_mi

[PULL v2 16/44] Hexagon (target/hexagon) Eliminate uses of log_pred_write function

These instructions have implicit writes to registers, so we don't want them to be helpers when idef-parser is off. The following instructions are overriden S2_cabacdecbin SA1_cmpeqi Remove the log_pred_write function from op_helper.c Remove references in macros.h Signed-off-by: T

[PULL v2 03/44] Hexagon (tests/tcg/hexagon) Add v68 scalar tests

Signed-off-by: Taylor Simpson Reviewed-by: Anton Johansson Message-Id: <20230427224057.3766963-4-tsimp...@quicinc.com> --- tests/tcg/hexagon/v68_scalar.c| 186 ++ tests/tcg/hexagon/Makefile.target | 2 + 2 files changed, 188 insertions(+) create mode

[PULL v2 26/44] Hexagon (target/hexagon) Move new_value to DisasContext

The new_value array in the CPUHexagonState is only used for bookkeeping within the translation of a packet. With recent changes that eliminate the need to free TCGv variables, these make more sense to be transient and kept in DisasContext. Suggested-by: Richard Henderson Signed-off-by: Taylor

[PULL v2 18/44] Hexagon (target/hexagon) Don't overlap dest writes with source reads

When generating TCG, make sure we have read all the operand registers before writing to the destination registers. This is a prerequesite for short-circuiting where the source and dest operands could be the same. Signed-off-by: Taylor Simpson Reviewed-by: Richard Henderson Message-Id

[PULL v2 07/44] Hexagon (tests/tcg/hexagon) Add v69 HVX tests

The following instructions are tested V6_vasrvuhubrndsat V6_vasrvuhubsat V6_vasrvwuhrndsat V6_vasrvwuhsat V6_vassign_tmp V6_vcombine_tmp V6_vmpyuhvs Signed-off-by: Taylor Simpson Reviewed-by: Anton Johansson Message-Id: <20230427224057.3766963-8-tsimp...@quicinc.

[PULL v2 29/44] Hexagon (target/hexagon) Move pkt_has_store_s1 to DisasContext

into a single argument called slotval. Suggested-by: Richard Henderson Signed-off-by: Taylor Simpson Reviewed-by: Richard Henderson Message-Id: <20230427230012.3800327-21-tsimp...@quicinc.com> --- target/hexagon/cpu.h| 1 - target/hexagon/macros.h

[PULL v2 37/44] Hexagon (decode): look for pkts with multiple insns at the same slot

nts. This should also make it easier to debug possible future errors caused by missing updates to `find_iclass_slots()` rules in target/hexagon/iclass.c. Co-authored-by: Taylor Simpson Signed-off-by: Taylor Simpson Signed-off-by: Matheus Tavares Bernardino Reviewed-by: Taylor Simpson Tested-

[PULL v2 39/44] gdbstub: only send stop-reply packets when allowed to

nt the GDB remote serial protocol, like hexagon-lldb. Let's change the gdbstub to send stop messages only as a response to a previous GDB command that accepts such a reply. Signed-off-by: Matheus Tavares Bernardino Acked-by: Alex Bennée Signed-off-by: Taylor Simpson Message-Id: --- gdbs

[PULL v2 01/44] Hexagon (target/hexagon) Add support for v68/v69/v71/v73

Add support for the ELF flags Move target/hexagon/cpu.[ch] to be v73 Change the compiler flag used by "make check-tcg" The decbin instruction is removed in Hexagon v73, so check the version before trying to compile the instruction. Signed-off-by: Taylor Simpson Reviewed-by: Anton

[PULL v2 12/44] Hexagon (target/hexagon) Add overrides for loop setup instructions

These instructions have implicit writes to registers, so we don't want them to be helpers when idef-parser is off. Signed-off-by: Taylor Simpson Acked-by: Richard Henderson Message-Id: <20230427230012.3800327-4-tsimp...@quicinc.com> --- target/hexagon/gen_tcg.h | 21

[PULL v2 34/44] Hexagon: list available CPUs with `-cpu help`

; Signed-off-by: Matheus Tavares Bernardino Signed-off-by: Taylor Simpson Tested-by: Taylor Simpson Reviewed-by: Taylor Simpson Message-Id: --- target/hexagon/cpu.h | 3 +++ target/hexagon/cpu.c | 20 2 files changed, 23 insertions(+) diff --git a/target/hexagon/cpu.h b/t

[PULL v2 20/44] Hexagon (target/hexagon) Short-circuit packet register writes

BEFORE: 004000b4 movi_i32 new_r0,$0x1 mov_i32 r0,new_r0 AFTER: 004000b4 movi_i32 r0,$0x1 This patch reintroduces a use of check_for_attrib, so we remove the G_GNUC_UNUSED added earlier in this series. Signed-off-by: Taylor Simpson Reviewed-by: Richard Henderson Reviewed-by: Brian Cain

[PULL v2 28/44] Hexagon (target/hexagon) Move pred_written to DisasContext

: Taylor Simpson Reviewed-by: Richard Henderson Message-Id: <20230427230012.3800327-20-tsimp...@quicinc.com> --- target/hexagon/cpu.h | 2 -- target/hexagon/helper.h| 2 +- target/hexagon/translate.h | 2 +- target/hexagon/genptr.c| 2 +- target/hexagon/op_helper.c | 5 +++--

[PULL v2 13/44] Hexagon (target/hexagon) Add overrides for allocframe/deallocframe

These instructions have implicit writes to registers, so we don't want them to be helpers when idef-parser is off. Signed-off-by: Taylor Simpson Reviewed-by: Richard Henderson Message-Id: <20230427230012.3800327-5-tsimp...@quicinc.com> --- target/hexagon/gen

[PULL v2 15/44] Hexagon (target/hexagon) Remove log_reg_write from op_helper.[ch]

With the overrides added in prior commits, this function is not used Remove references in macros.h Signed-off-by: Taylor Simpson Reviewed-by: Richard Henderson Message-Id: <20230427230012.3800327-7-tsimp...@quicinc.com> --- target/hexagon/macros.h| 14 -- target/h

[PULL v2 36/44] Hexagon (iclass): update J4_hintjumpr slot constraints

instructions at the same slot during decoding time and throw an invalid packet exception. That will be done in the subsequent commit. Signed-off-by: Matheus Tavares Bernardino Reviewed-by: Taylor Simpson Signed-off-by: Taylor Simpson Message-Id: <0fcd8293642c6324119fbbab44741164b

[PULL v2 24/44] Hexagon (target/hexagon) Add overrides for disabled idef-parser insns

cases added to tests/tcg/hexagon/read_write_overlap.c Signed-off-by: Taylor Simpson Reviewed-by: Richard Henderson Message-Id: <20230427230012.3800327-16-tsimp...@quicinc.com> --- target/hexagon/gen_tcg.h | 18 target/hexagon/genptr.c

[PULL v2 08/44] Hexagon (target/hexagon) Add v73 scalar instructions

The following instructions are added J2_callrh J2_junprh Signed-off-by: Taylor Simpson Reviewed-by: Anton Johansson Message-Id: <20230427224057.3766963-9-tsimp...@quicinc.com> --- target/hexagon/gen_tcg.h | 4 target/hexagon/attribs_def.h.inc | 1 +

[PULL v2 09/44] Hexagon (tests/tcg/hexagon) Add v73 scalar tests

Tests added for the following instructions J2_callrh J2_jumprh Signed-off-by: Taylor Simpson Reviewed-by: Anton Johansson Message-Id: <20230427224057.3766963-10-tsimp...@quicinc.com> --- tests/tcg/hexagon/v73_scalar.c| 96 +++ tests/tcg/h

[PULL v2 14/44] Hexagon (target/hexagon) Add overrides for clr[tf]new

These instructions have implicit reads from p0, so we don't want them in helpers when idef-parser is off. Signed-off-by: Taylor Simpson Reviewed-by: Richard Henderson Message-Id: <20230427230012.3800327-6-tsimp...@quicinc.com> --- target/hexagon/gen_tcg.h | 16 tar

[PULL v2 35/44] Hexagon: append eflags to unknown cpu model string

message becomes: qemu-hexagon: unable to find CPU model 'unknown (0x69)' Signed-off-by: Matheus Tavares Bernardino Signed-off-by: Taylor Simpson Tested-by: Taylor Simpson Reviewed-by: Taylor Simpson Message-Id: <8a8d013cc619b94fd4fb577ae6a8df26cedb972b.1683225804.git.quic_math

[PULL v2 10/44] meson.build Add CONFIG_HEXAGON_IDEF_PARSER

Enable conditional compilation depending on whether idef-parser is configured Signed-off-by: Taylor Simpson Reviewed-by: Richard Henderson Message-Id: <20230427230012.3800327-2-tsimp...@quicinc.com> --- meson.build | 1 + 1 file changed, 1 insertion(+) diff --git a/meson.build b/meson

[PULL v2 17/44] Hexagon (target/hexagon) Clean up pred_written usage

later in this series, so we mark it with G_GNUC_UNUSED. Signed-off-by: Taylor Simpson Reviewed-by: Richard Henderson Message-Id: <20230427230012.3800327-9-tsimp...@quicinc.com> --- target/hexagon/genptr.c| 16 +--- target/hexagon/translate.

[PULL v2 19/44] Hexagon (target/hexagon) Mark registers as read during packet analysis

Have gen_analyze_funcs mark the registers that are read by the instruction. We also mark the implicit reads using instruction attributes. Signed-off-by: Taylor Simpson Reviewed-by: Richard Henderson Message-Id: <20230427230012.3800327-11-tsimp...@quicinc.com> --- target/hexagon/trans

[PULL v2 33/44] Hexagon (target/hexagon/*.py): raise exception on reg parsing error

ex_common.py. Signed-off-by: Matheus Tavares Bernardino Reviewed-by: Anton Johansson Tested-by: Taylor Simpson Reviewed-by: Taylor Simpson Signed-off-by: Taylor Simpson Message-Id: <1f5dbd92f68fdd89e2647e4ba527a2c32cf0f070.1683217043.git.quic_mathb...@quicinc.com> --- target/hexagon/gen_a

[PULL v2 31/44] Hexagon (target/hexagon) Additional instructions handled by idef-parser

gen_rvalue_extend gen_cast_op imm_print lexer properly sets size/signedness of constants Test cases added to tests/tcg/hexagon/fpstuff.c Signed-off-by: Taylor Simpson Tested-by: Anton Johansson Reviewed-by: Anton Johansson Message-Id: <20230501203125.4025991-1-tsimp...@quicinc.com> ---

[PULL v2 22/44] Hexagon (target/hexagon) Short-circuit packet HVX writes

In certain cases, we can avoid the overhead of writing to future_VRegs and write directly to VRegs. We consider HVX reads/writes when computing ctx->need_commit. Then, we can early-exit from gen_commit_hvx. Signed-off-by: Taylor Simpson Reviewed-by: Richard Henderson Message

[PULL v2 40/44] gdbstub: add test for untimely stop-reply packets

stop-reply packet asynchronously, when GDB was in fact waiting an ACK. Signed-off-by: Matheus Tavares Bernardino Acked-by: Alex Bennée Signed-off-by: Taylor Simpson Message-Id: --- tests/guest-debug/run-test.py| 16 .../tcg/multiarch/system/Makefile.softmmu-t

[PULL v2 41/44] Hexagon: add core gdbstub xml data for LLDB

From: Matheus Tavares Bernardino Signed-off-by: Matheus Tavares Bernardino Reviewed-by: Taylor Simpson Signed-off-by: Taylor Simpson Message-Id: --- MAINTAINERS| 1 + configs/targets/hexagon-linux-user.mak | 1 + target/hexagon/cpu.c | 3

[PULL v2 43/44] Hexagon (gdbstub): add HVX support

Signed-off-by: Taylor Simpson Co-authored-by: Brian Cain Signed-off-by: Brian Cain Co-authored-by: Matheus Tavares Bernardino Signed-off-by: Matheus Tavares Bernardino Reviewed-by: Brian Cain Message-Id: <17cb32f34d469f705c3cc066a3583935352ee048.1683214375.git.quic_mathb...@quicinc.

[PULL v2 44/44] Hexagon (linux-user/hexagon): handle breakpoints

From: Matheus Tavares Bernardino This enables LLDB to work with hexagon linux-user mode through the GDB remote protocol. Helped-by: Richard Henderson Signed-off-by: Matheus Tavares Bernardino Reviewed-by: Richard Henderson Signed-off-by: Taylor Simpson Message-Id: --- linux-user/hexagon

[PULL v2 42/44] Hexagon (gdbstub): fix p3:0 read and write via stub

From: Brian Cain Signed-off-by: Brian Cain Co-authored-by: Sid Manning Signed-off-by: Sid Manning Co-authored-by: Matheus Tavares Bernardino Signed-off-by: Matheus Tavares Bernardino Reviewed-by: Taylor Simpson Signed-off-by: Taylor Simpson Message-Id

RE: [PATCH] Hexagon (target/hexagon) Fix assignment to tmp registers

> -Original Message- > From: Marco Liebel (QUIC) > Sent: Monday, May 22, 2023 11:14 AM > To: qemu-devel@nongnu.org > Cc: Taylor Simpson ; Brian Cain > ; Marco Liebel (QUIC) > Subject: [PATCH] Hexagon (target/hexagon) Fix assignment to tmp registers > > The

RE: [PATCH 1/2] target/hexagon/*.py: remove undef vars from bad_register()

> -Original Message- > From: Matheus Tavares Bernardino > Sent: Tuesday, May 23, 2023 3:36 PM > To: qemu-devel@nongnu.org > Cc: Taylor Simpson ; Brian Cain > ; Marco Liebel (QUIC) > Subject: [PATCH 1/2] target/hexagon/*.py: remove undef vars from > bad_regis

RE: [PATCH 2/2] Hexagon: fix outdated `hex_new_*` references in comments

> -Original Message- > From: Matheus Tavares Bernardino > Sent: Tuesday, May 23, 2023 3:36 PM > To: qemu-devel@nongnu.org > Cc: Taylor Simpson ; Brian Cain > ; Marco Liebel (QUIC) > Subject: [PATCH 2/2] Hexagon: fix outdated `hex_new_*` references in > comments

RE: [PATCH v2 1/2] target/hexagon/*.py: clean up used 'toss' and 'numregs' vars

> -Original Message- > From: Matheus Tavares Bernardino > Sent: Wednesday, May 24, 2023 9:42 AM > To: qemu-devel@nongnu.org > Cc: Taylor Simpson ; Brian Cain > ; Marco Liebel (QUIC) ; > Alessandro Di Federico ; Anton Johansson > Subject: [PATCH v2 1/2] targe

RE: [PATCH v2 2/2] Hexagon: fix outdated `hex_new_*` comments

> -Original Message- > From: Matheus Tavares Bernardino > Sent: Wednesday, May 24, 2023 9:42 AM > To: qemu-devel@nongnu.org > Cc: Taylor Simpson ; Brian Cain > ; Marco Liebel (QUIC) > Subject: [PATCH v2 2/2] Hexagon: fix outdated `hex_new_*` comments > >

[PATCH 1/1] Hexagon (target/hexagon) Change Hexagon maintainer

Change Hexagon maintainer from Taylor Simpson to Brian Cain Put Taylor's gmail address in .mailmap Signed-off-by: Taylor Simpson --- MAINTAINERS | 2 +- .mailmap| 1 + 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/MAINTAINERS b/MAINTAINERS index 1b6466496d..426d33f4cb 1

[PATCH 0/1] Change Hexagon maintainer

I will be retiring from Qualcomm at the end of May, so I am placing the maintainership in the very capable hands of Brian Cain. Taylor Simpson (1): Hexagon (target/hexagon) Change Hexagon maintainer MAINTAINERS | 2 +- .mailmap| 1 + 2 files changed, 2 insertions(+), 1 deletion

[PULL 2/5] Hexagon (target/hexagon) Fix assignment to tmp registers

ere in the wrong place. Moving them to the correct location makes shuffling of .tmp vector registers work as expected. Signed-off-by: Marco Liebel Reviewed-by: Taylor Simpson Tested-by: Taylor Simpson Signed-off-by: Taylor Simpson Reviewed-by: Brian Cain Message-Id: <20230522174708.46419

[PULL 4/5] Hexagon: fix outdated `hex_new_*` comments

tweak them whenever we make a variable name change in the future, let's replace them with pseudocode. Suggested-by: Taylor Simpson Signed-off-by: Matheus Tavares Bernardino Reviewed-by: Taylor Simpson Signed-off-by: Taylor Simpson Message-Id: <8e1689e28dd7b1318369b55127cf47b82ab75921.16

[PULL 5/5] Hexagon (target/hexagon) Change Hexagon maintainer

Change Hexagon maintainer from Taylor Simpson to Brian Cain Put Taylor's gmail address in .mailmap Signed-off-by: Taylor Simpson Reviewed-by: Alex Bennée --- MAINTAINERS | 2 +- .mailmap| 1 + 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/MAINTAINERS b/MAINTAINERS

[PULL 3/5] target/hexagon/*.py: clean up used 'toss' and 'numregs' vars

ill restore the old full behavior. Suggested-by: Taylor Simpson Signed-off-by: Matheus Tavares Bernardino Reviewed-by: Taylor Simpson Tested-by: Taylor Simpson Signed-off-by: Taylor Simpson Message-Id: <3ffd4ccb972879f57f499705c624e8eaba7f8b52.1684939078.git.quic_mathb...@quicinc.com>

[PULL 0/5] Hexagon update

rco Liebel (1): Hexagon (target/hexagon) Fix assignment to tmp registers Matheus Tavares Bernardino (2): target/hexagon/*.py: clean up used 'toss' and 'numregs' vars Hexagon: fix outdated `hex_new_*` comments Taylor Simpson (2): Hexagon (tests/tcg/hexag

RE: [PULL 00/17] Hexagon (target/hexagon) updates

Just checking if this is on the radar to be merged ... > -Original Message- > From: Taylor Simpson > Sent: Monday, March 6, 2023 10:34 PM > To: qemu-devel@nongnu.org > Cc: Taylor Simpson ; richard.hender...@linaro.org; > phi...@linaro.org; peter.mayd...@lina

RE: [PATCH] Use f-strings in python scripts

> -Original Message- > From: Marco Liebel (QUIC) > Sent: Monday, March 13, 2023 11:26 AM > To: qemu-devel@nongnu.org > Cc: Taylor Simpson ; Marco Liebel (QUIC) > > Subject: [PATCH] Use f-strings in python scripts > > Replace python 2 format string with f

<    1   2   3   4   5   6   7   8   9   10   >