packets when allowed to
gdbstub: add test for untimely stop-reply packets
Hexagon: add core gdbstub xml data for LLDB
Hexagon (linux-user/hexagon): handle breakpoints
Paolo Bonzini (1):
target/hexagon: fix = vs. == mishap
Taylor Simpson (32):
Hexagon (target/hexagon)
into a single argument called
slotval.
Suggested-by: Richard Henderson
Signed-off-by: Taylor Simpson
Reviewed-by: Richard Henderson
Message-Id: <20230427230012.3800327-21-tsimp...@quicinc.com>
---
target/hexagon/cpu.h| 1 -
target/hexagon/macros.h
Signed-off-by: Taylor Simpson
Reviewed-by: Anton Johansson
Message-Id: <20230427224057.3766963-6-tsimp...@quicinc.com>
---
tests/tcg/hexagon/v68_hvx.c | 90 +
tests/tcg/hexagon/v6mpy_ref.c.inc | 161 ++
tests/tcg/hexagon/Makefile.target
ex_common.py.
Signed-off-by: Matheus Tavares Bernardino
Reviewed-by: Anton Johansson
Tested-by: Taylor Simpson
Reviewed-by: Taylor Simpson
Signed-off-by: Taylor Simpson
Message-Id:
<1f5dbd92f68fdd89e2647e4ba527a2c32cf0f070.1683217043.git.quic_mathb...@quicinc.com>
---
target/hexagon/gen_a
When generating TCG, make sure we have read all the operand registers
before writing to the destination registers.
This is a prerequesite for short-circuiting where the source and dest
operands could be the same.
Signed-off-by: Taylor Simpson
Reviewed-by: Richard Henderson
Message-Id
The encodings for these instructions changed some "don't care" bits
L2_loadw_locked
L4_loadd_locked
S2_storew_locked
S4_stored_locked
Signed-off-by: Taylor Simpson
Reviewed-by: Anton Johansson
Message-Id: <20230427224057.3766963-3-tsimp...@quicinc.com>
---
nts.
This should also make it easier to debug possible future errors caused
by missing updates to `find_iclass_slots()` rules in
target/hexagon/iclass.c.
Co-authored-by: Taylor Simpson
Signed-off-by: Taylor Simpson
Signed-off-by: Matheus Tavares Bernardino
Reviewed-by: Taylor Simpson
Tested-
;
Signed-off-by: Matheus Tavares Bernardino
Signed-off-by: Taylor Simpson
Tested-by: Taylor Simpson
Reviewed-by: Taylor Simpson
Message-Id:
---
target/hexagon/cpu.h | 3 +++
target/hexagon/cpu.c | 20
2 files changed, 23 insertions(+)
diff --git a/target/hexagon/cpu.h b/t
From: Paolo Bonzini
Changes in v2
Fix yyassert's for sign and zero extends
Coverity reports a parameter that is "set but never used". This is caused
by an assignment operator being used instead of equality.
Co-authored-by: Taylor Simpson
Signed-off-by: Paolo Bonzini
later in this series, so we mark it with G_GNUC_UNUSED.
Signed-off-by: Taylor Simpson
Reviewed-by: Richard Henderson
Message-Id: <20230427230012.3800327-9-tsimp...@quicinc.com>
---
target/hexagon/genptr.c| 16 +---
target/hexagon/translate.
: Taylor Simpson
Reviewed-by: Richard Henderson
Message-Id: <20230427230012.3800327-20-tsimp...@quicinc.com>
---
target/hexagon/cpu.h | 2 --
target/hexagon/helper.h| 2 +-
target/hexagon/translate.h | 2 +-
target/hexagon/genptr.c| 2 +-
target/hexagon/op_helper.c | 5 +++--
The new_value array in the CPUHexagonState is only used for bookkeeping
within the translation of a packet. With recent changes that eliminate
the need to free TCGv variables, these make more sense to be transient
and kept in DisasContext.
Suggested-by: Richard Henderson
Signed-off-by: Taylor
nt the GDB remote serial protocol, like hexagon-lldb. Let's
change the gdbstub to send stop messages only as a response to a
previous GDB command that accepts such a reply.
Signed-off-by: Matheus Tavares Bernardino
Acked-by: Alex Bennée
Signed-off-by: Taylor Simpson
Message-Id:
---
gdbs
Add DisasContext arg to gen_log_reg_write_pair also
Signed-off-by: Taylor Simpson
Reviewed-by: Richard Henderson
Message-Id: <20230427230012.3800327-3-tsimp...@quicinc.com>
---
target/hexagon/gen_tcg.h| 2 +-
target/hexagon/genptr.h | 2 +-
These instructions have implicit writes to registers, so we don't
want them to be helpers when idef-parser is off.
The following instructions are overriden
S2_cabacdecbin
SA1_cmpeqi
Remove the log_pred_write function from op_helper.c
Remove references in macros.h
Signed-off-by: T
These instructions have implicit writes to registers, so we don't
want them to be helpers when idef-parser is off.
Signed-off-by: Taylor Simpson
Acked-by: Richard Henderson
Message-Id: <20230427230012.3800327-4-tsimp...@quicinc.com>
---
target/hexagon/gen_tcg.h | 21
Tests added for the following instructions
J2_callrh
J2_jumprh
Signed-off-by: Taylor Simpson
Reviewed-by: Anton Johansson
Message-Id: <20230427224057.3766963-10-tsimp...@quicinc.com>
---
tests/tcg/hexagon/v73_scalar.c| 96 +++
tests/tcg/h
In certain cases, we can avoid the overhead of writing to future_VRegs
and write directly to VRegs. We consider HVX reads/writes when computing
ctx->need_commit. Then, we can early-exit from gen_commit_hvx.
Signed-off-by: Taylor Simpson
Reviewed-by: Richard Henderson
Message
BEFORE:
004000b4
movi_i32 new_r0,$0x1
mov_i32 r0,new_r0
AFTER:
004000b4
movi_i32 r0,$0x1
This patch reintroduces a use of check_for_attrib, so we remove the
G_GNUC_UNUSED added earlier in this series.
Signed-off-by: Taylor Simpson
Reviewed-by: Richard Henderson
Reviewed-by: Brian Cain
Precursor to moving new_value from the global state to DisasContext
USR will need to stay in the global state because some helpers will
set it's value
Signed-off-by: Taylor Simpson
Reviewed-by: Richard Henderson
Message-Id: <20230427230012.3800327-17-tsimp...@quicinc.com>
---
tar
Have gen_analyze_funcs mark the registers that are read by the
instruction. We also mark the implicit reads using instruction
attributes.
Signed-off-by: Taylor Simpson
Reviewed-by: Richard Henderson
Message-Id: <20230427230012.3800327-11-tsimp...@quicinc.com>
---
target/hexagon/trans
These instructions have implicit writes to registers, so we don't
want them to be helpers when idef-parser is off.
Signed-off-by: Taylor Simpson
Reviewed-by: Richard Henderson
Message-Id: <20230427230012.3800327-5-tsimp...@quicinc.com>
---
target/hexagon/gen
message
becomes:
qemu-hexagon: unable to find CPU model 'unknown (0x69)'
Signed-off-by: Matheus Tavares Bernardino
Signed-off-by: Taylor Simpson
Tested-by: Taylor Simpson
Reviewed-by: Taylor Simpson
Message-Id:
<8a8d013cc619b94fd4fb577ae6a8df26cedb972b.1683225804.git.quic_math
branch_taken
this_PC
Suggested-by: Richard Henderson
Signed-off-by: Taylor Simpson
Reviewed-by: Richard Henderson
Message-Id: <20230427230012.3800327-22-tsimp...@quicinc.com>
---
target/hexagon/cpu.h | 3 ---
target/hexagon/helper.h| 2 +-
target/hexagon/macros.h
With the overrides added in prior commits, this function is not used
Remove references in macros.h
Signed-off-by: Taylor Simpson
Reviewed-by: Richard Henderson
Message-Id: <20230427230012.3800327-7-tsimp...@quicinc.com>
---
target/hexagon/macros.h| 14 --
target/h
Enable conditional compilation depending on whether idef-parser
is configured
Signed-off-by: Taylor Simpson
Reviewed-by: Richard Henderson
Message-Id: <20230427230012.3800327-2-tsimp...@quicinc.com>
---
meson.build | 1 +
1 file changed, 1 insertion(+)
diff --git a/meson.build b/meson
cases added to tests/tcg/hexagon/read_write_overlap.c
Signed-off-by: Taylor Simpson
Reviewed-by: Richard Henderson
Message-Id: <20230427230012.3800327-16-tsimp...@quicinc.com>
---
target/hexagon/gen_tcg.h | 18
target/hexagon/genptr.c
From: Matheus Tavares Bernardino
This enables LLDB to work with hexagon linux-user mode through the GDB
remote protocol.
Helped-by: Richard Henderson
Signed-off-by: Matheus Tavares Bernardino
Reviewed-by: Richard Henderson
Signed-off-by: Taylor Simpson
Message-Id:
---
linux-user/hexagon
From: Brian Cain
Signed-off-by: Brian Cain
Co-authored-by: Sid Manning
Signed-off-by: Sid Manning
Co-authored-by: Matheus Tavares Bernardino
Signed-off-by: Matheus Tavares Bernardino
Reviewed-by: Taylor Simpson
Signed-off-by: Taylor Simpson
Message-Id
stop-reply packet
asynchronously, when GDB was in fact waiting an ACK.
Signed-off-by: Matheus Tavares Bernardino
Acked-by: Alex Bennée
Signed-off-by: Taylor Simpson
Message-Id:
---
tests/guest-debug/run-test.py| 16
.../tcg/multiarch/system/Makefile.softmmu-t
From: Matheus Tavares Bernardino
Signed-off-by: Matheus Tavares Bernardino
Reviewed-by: Taylor Simpson
Signed-off-by: Taylor Simpson
Message-Id:
---
MAINTAINERS| 1 +
configs/targets/hexagon-linux-user.mak | 1 +
target/hexagon/cpu.c | 3
Signed-off-by: Taylor Simpson
Co-authored-by: Brian Cain
Signed-off-by: Brian Cain
Co-authored-by: Matheus Tavares Bernardino
Signed-off-by: Matheus Tavares Bernardino
Reviewed-by: Brian Cain
Message-Id:
<17cb32f34d469f705c3cc066a3583935352ee048.1683214375.git.quic_mathb...@quicinc.
Signed-off-by: Taylor Simpson
Reviewed-by: Anton Johansson
Message-Id: <20230405164211.30015-3-tsimp...@quicinc.com>
---
target/hexagon/gen_tcg.h| 4 +-
target/hexagon/genptr.h | 10 ++---
target/hexagon/macros.h | 8
Most of these are not modelled in QEMU, so save the overhead of
calling a helper.
The only exception is dczeroa. It assigns to hex_dczero_addr, which
is handled during packet commit.
Signed-off-by: Taylor Simpson
Reviewed-by: Richard Henderson
Message-Id: <20230410202402.2856852-1-ts
Reducing the number of arguments reduces the overhead of the helper
call
Signed-off-by: Taylor Simpson
Reviewed-by: Philippe Mathieu-Daudé
Message-Id: <20230405164211.30015-2-tsimp...@quicinc.com>
---
target/hexagon/helper.h| 4 ++--
target/hexagon/translate.h | 1 +
target/h
From: Marco Liebel
Replace python 2 format string with f-strings
Signed-off-by: Marco Liebel
Signed-off-by: Taylor Simpson
Reviewed-by: Taylor Simpson
Tested-by: Taylor Simpson
Message-Id: <20230320092533.2859433-2-quic_mlie...@quicinc.com>
---
target/hexagon/gen_analyze_funcs.py
work, we fix some bugs in parser-helpers.c
gen_rvalue_extend
gen_cast_op
Test cases added to tests/tcg/hexagon/fpstuff.c
Signed-off-by: Taylor Simpson
Reviewed-by: Anton Johansson
Tested-by: Anton Johansson
Message-Id: <20230407205246.395196-1-tsimp...@quicinc.com>
---
target/h
This will facilitate adding additional tests in separate .c files
Signed-off-by: Taylor Simpson
Reviewed-by: Philippe Mathieu-Daudé
Message-Id: <20230406174241.853296-1-tsimp...@quicinc.com>
---
tests/tcg/hexagon/hvx_misc.h | 178 ++
tests/tcg/h
because the
imported semantics uses bit-reverse. However, they are
straightforward to implement in TCG with tcg_gen_ctzi_*
Test cases added to tests/tcg/hexagon/misc.c
Signed-off-by: Taylor Simpson
Reviewed-by: Richard Henderson
Message-Id: <20230405164211.30015-1-tsimp...@quicinc.com>
---
gon update
Marco Liebel (2):
Use f-strings in python scripts
Use black code style for python scripts
Matheus Tavares Bernardino (1):
Hexagon (translate.c): avoid redundant PC updates on COF
Taylor Simpson (8):
Hexagon (target/hexagon) Remove redundant/unu
off-by: Matheus Tavares Bernardino
Signed-off-by: Taylor Simpson
Reviewed-by: Anton Johansson
Reviewed-by: Taylor Simpson
Message-Id:
---
target/hexagon/translate.c | 21 +
1 file changed, 13 insertions(+), 8 deletions(-)
diff --git a/target/hexagon/translate.c b/target/he
The slot variable in helpers was only passed to log_reg_write function
where the argument is unused.
- Remove declaration from generated helper functions
- Remove slot argument from log_reg_write
Signed-off-by: Taylor Simpson
Reviewed-by: Richard Henderson
Message-Id: <20230407204521.35724
-off-by: Taylor Simpson
Reviewed-by: Richard Henderson
Message-Id: <20230405183048.147767-1-tsimp...@quicinc.com>
---
target/hexagon/macros.h | 65 ++---
1 file changed, 22 insertions(+), 43 deletions(-)
diff --git a/target/hexagon/macros.h b/target/h
> -Original Message-
> From: Richard Henderson
> Sent: Friday, April 21, 2023 3:21 AM
> To: Taylor Simpson ; qemu-devel@nongnu.org
> Cc: phi...@linaro.org; peter.mayd...@linaro.org; Brian Cain
> ; Matheus Bernardino (QUIC)
> ; stefa...@redhat.com; a...@rev.ng;
Reducing the number of arguments reduces the overhead of the helper
call
Signed-off-by: Taylor Simpson
Reviewed-by: Philippe Mathieu-Daudé
Message-Id: <20230405164211.30015-2-tsimp...@quicinc.com>
---
target/hexagon/helper.h| 4 ++--
target/hexagon/translate.h | 1 +
target/h
-off-by: Taylor Simpson
Reviewed-by: Richard Henderson
Message-Id: <20230405183048.147767-1-tsimp...@quicinc.com>
---
target/hexagon/macros.h | 65 ++---
1 file changed, 22 insertions(+), 43 deletions(-)
diff --git a/target/hexagon/macros.h b/target/h
From: Marco Liebel
Replace python 2 format string with f-strings
Signed-off-by: Marco Liebel
Signed-off-by: Taylor Simpson
Reviewed-by: Taylor Simpson
Tested-by: Taylor Simpson
Message-Id: <20230320092533.2859433-2-quic_mlie...@quicinc.com>
---
target/hexagon/gen_analyze_funcs.py
off-by: Matheus Tavares Bernardino
Signed-off-by: Taylor Simpson
Reviewed-by: Anton Johansson
Reviewed-by: Taylor Simpson
Message-Id:
---
target/hexagon/translate.c | 21 +
1 file changed, 13 insertions(+), 8 deletions(-)
diff --git a/target/hexagon/translate.c b/target/he
because the
imported semantics uses bit-reverse. However, they are
straightforward to implement in TCG with tcg_gen_ctzi_*
Test cases added to tests/tcg/hexagon/misc.c
Signed-off-by: Taylor Simpson
Reviewed-by: Richard Henderson
Message-Id: <20230405164211.30015-1-tsimp...@quicinc.com>
---
The slot variable in helpers was only passed to log_reg_write function
where the argument is unused.
- Remove declaration from generated helper functions
- Remove slot argument from log_reg_write
Signed-off-by: Taylor Simpson
Reviewed-by: Richard Henderson
Message-Id: <20230407204521.35724
Most of these are not modelled in QEMU, so save the overhead of
calling a helper.
The only exception is dczeroa. It assigns to hex_dczero_addr, which
is handled during packet commit.
Signed-off-by: Taylor Simpson
Reviewed-by: Richard Henderson
Message-Id: <20230410202402.2856852-1-ts
This will facilitate adding additional tests in separate .c files
Signed-off-by: Taylor Simpson
Reviewed-by: Philippe Mathieu-Daudé
Message-Id: <20230406174241.853296-1-tsimp...@quicinc.com>
---
tests/tcg/hexagon/hvx_misc.h | 178 ++
tests/tcg/h
Signed-off-by: Taylor Simpson
Reviewed-by: Anton Johansson
Message-Id: <20230405164211.30015-3-tsimp...@quicinc.com>
---
target/hexagon/gen_tcg.h| 4 +-
target/hexagon/genptr.h | 10 ++---
target/hexagon/macros.h | 8
hat breaks clang CI
Marco Liebel (2):
Use f-strings in python scripts
Use black code style for python scripts
Matheus Tavares Bernardino (1):
Hexagon (translate.c): avoid redundant PC updates on COF
Taylor
rts 2 and 3
The main goal is to move functionality out of generated helpers
Part 2: Patches 10-15
Short-circuit packet semantics
Part 3: Patches 16-21
Move bookkeeping items from CPUHexagonState to DisasContext
Taylor Simpson (21):
meson.build Add CONFIG_HEXAGON_IDEF_PARSER
He
Enable conditional compilation depending on whether idef-parser
is configured
Signed-off-by: Taylor Simpson
---
meson.build | 1 +
1 file changed, 1 insertion(+)
diff --git a/meson.build b/meson.build
index c44d05a13f..d4e438b033 100644
--- a/meson.build
+++ b/meson.build
@@ -1859,6 +1859,7
Add DisasContext arg to gen_log_reg_write_pair also
Signed-off-by: Taylor Simpson
---
target/hexagon/gen_tcg.h| 2 +-
target/hexagon/genptr.h | 2 +-
target/hexagon/genptr.c | 10 +-
target/hexagon/idef-parser/parser
These instructions have implicit writes to registers, so we don't
want them to be helpers when idef-parser is off.
Signed-off-by: Taylor Simpson
---
target/hexagon/gen_tcg.h | 32 +
target/hexagon/genptr.c | 44
2
These instructions have implicit writes to registers, so we don't
want them to be helpers when idef-parser is off.
Signed-off-by: Taylor Simpson
---
target/hexagon/gen_tcg.h | 21 +++
target/hexagon/genptr.c | 44
2 files change
These instructions have implicit writes to registers, so we don't
want them to be helpers when idef-parser is off.
The following instructions are overriden
S2_cabacdecbin
SA1_cmpeqi
Remove the log_pred_write function from op_helper.c
Remove references in macros.h
Signed-off-by: T
With the overrides added in prior commits, this function is not used
Remove references in macros.h
Signed-off-by: Taylor Simpson
---
target/hexagon/macros.h| 14 --
target/hexagon/op_helper.h | 4
target/hexagon/op_helper.c | 17 -
3 files changed, 35
These instructions have implicit reads from p0, so we don't want
them in helpers when idef-parser is off.
Signed-off-by: Taylor Simpson
---
target/hexagon/gen_tcg.h | 18 ++
target/hexagon/macros.h | 4
2 files changed, 18 insertions(+), 4 deletions(-)
diff --
Precursor to moving new_value from the global state to DisasContext
USR will need to stay in the global state because some helpers will
set it's value
Signed-off-by: Taylor Simpson
---
target/hexagon/cpu.h| 1 +
target/hexagon/genptr.h | 1 +
target/hexagon/mac
The new_value array in the CPUHexagonState is only used for bookkeeping
within the translation of a packet. With recent changes that eliminate
the need to free TCGv variables, these make more sense to be transient
and kept in DisasContext.
Suggested-by: Richard Henderson
Signed-off-by: Taylor
cases added to tests/tcg/hexagon/read_write_overlap.c
Signed-off-by: Taylor Simpson
---
target/hexagon/gen_tcg.h | 18
target/hexagon/genptr.c| 100 ++
tests/tcg/hexagon/read_write_overlap.c | 136 +
tests/tcg/hexagon
later in this series, so we change it to "static inline".
Signed-off-by: Taylor Simpson
---
target/hexagon/genptr.c| 16 +---
target/hexagon/translate.c | 53 --
2 files changed, 23 insertions(+), 46 deletions(-)
diff --git a/target/hexagon/
BEFORE:
004000b4
movi_i32 new_r0,$0x1
mov_i32 r0,new_r0
AFTER:
004000b4
movi_i32 r0,$0x1
Signed-off-by: Taylor Simpson
---
target/hexagon/cpu.h| 1 +
target/hexagon/gen_tcg.h| 3 +-
target/hexagon/genptr.h | 2 +
target/hexagon/
into a single argument called
slotval.
Signed-off-by: Taylor Simpson
---
target/hexagon/cpu.h| 1 -
target/hexagon/macros.h | 16
target/hexagon/op_helper.h | 12
target/hexagon/translate.h | 1 -
target/hexagon/genptr.c
In certain cases, we can avoid the overhead of writing to future_VRegs
and write directly to VRegs. We consider HVX reads/writes when computing
ctx->need_commit. Then, we can early-exit from gen_commit_hvx.
Signed-off-by: Taylor Simpson
---
target/hexagon/genptr.c| 6 -
tar
rly-exit from gen_pred_writes.
Signed-off-by: Taylor Simpson
---
target/hexagon/genptr.h| 1 +
target/hexagon/genptr.c| 15 ---
target/hexagon/translate.c | 14 +++---
3 files changed, 24 insertions(+), 6 deletions(-)
diff --git a/target/hexagon/genptr.h b/target/hexa
branch_taken
this_PC
Suggested-by: Richard Henderson
Signed-off-by: Taylor Simpson
---
target/hexagon/cpu.h | 3 ---
target/hexagon/helper.h| 2 +-
target/hexagon/macros.h| 6 +-
target/hexagon/translate.h | 5 ++---
target/hexagon/genptr.c| 6 +++---
target/hexagon
ction is an HVX instruction with a
generated helper.
We add an override for V6_vcombine so that it can be short-circuited
along with a test case in tests/tcg/hexagon/hvx_misc.c
Signed-off-by: Taylor Simpson
---
target/hexagon/gen_tcg_hvx.h| 23 +++
target/hexagon/transl
When generating TCG, make sure we have read all the operand registers
before writing to the destination registers.
This is a prerequesite for short-circuiting where the source and dest
operands could be the same.
Signed-off-by: Taylor Simpson
---
target/hexagon/genptr.c | 45
: Taylor Simpson
---
target/hexagon/cpu.h | 2 --
target/hexagon/helper.h| 2 +-
target/hexagon/translate.h | 2 +-
target/hexagon/genptr.c| 2 +-
target/hexagon/op_helper.c | 5 +++--
target/hexagon/translate.c | 9 -
6 files changed, 10 insertions(+), 12 deletions(-)
diff
Have gen_analyze_funcs mark the registers that are read by the
instruction. We also mark the implicit reads using instruction
attributes.
Signed-off-by: Taylor Simpson
---
target/hexagon/translate.h | 36 +++
target/hexagon/attribs_def.h.inc| 6 +++-
target
: Taylor Simpson
---
target/hexagon/cpu.h| 1 -
target/hexagon/gen_tcg.h| 12 ++--
target/hexagon/translate.h | 2 +-
target/hexagon/genptr.c | 10 +++---
target/hexagon/idef-parser/parser-helpers.c | 2
Add support for new Hexagon architecture versions v68/v69/v71/v73
Taylor Simpson (9):
Hexagon (target/hexagon) Add support for v68/v69/v71/v73
Hexagon (target/hexagon) Add v68 scalar instructions
Hexagon (tests/tcg/hexagon) Add v68 scalar tests
Hexagon (target/hexagon) Add v68 HVX
The encodings for these instructions changed some "don't care" bits
L2_loadw_locked
L4_loadd_locked
S2_storew_locked
S4_stored_locked
Signed-off-by: Taylor Simpson
---
target/hexagon/gen_tcg.h| 18 ++
target/hexagon/attribs_def.h.inc
The following instructions are added
V6_vasrvuhubrndsat
V6_vasrvuhubsat
V6_vasrvwuhrndsat
V6_vasrvwuhsat
V6_vassign_tmp
V6_vcombine_tmp
V6_vmpyuhvs
Signed-off-by: Taylor Simpson
---
target/hexagon/gen_tcg_hvx.h | 12 ++
target/hexagon
The following instructions are tested
V6_vasrvuhubrndsat
V6_vasrvuhubsat
V6_vasrvwuhrndsat
V6_vasrvwuhsat
V6_vassign_tmp
V6_vcombine_tmp
V6_vmpyuhvs
Signed-off-by: Taylor Simpson
---
tests/tcg/hexagon/v69_hvx.c | 318 ++
tests/tcg
Add support for the ELF flags
Move target/hexagon/cpu.[ch] to be v73
Change the compiler flag used by "make check-tcg"
The decbin instruction is removed in Hexagon v73, so check the
version before trying to compile the instruction.
Signed-off-by: Taylor Simpson
---
Signed-off-by: Taylor Simpson
---
tests/tcg/hexagon/v68_scalar.c| 186 ++
tests/tcg/hexagon/Makefile.target | 2 +
2 files changed, 188 insertions(+)
create mode 100644 tests/tcg/hexagon/v68_scalar.c
diff --git a/tests/tcg/hexagon/v68_scalar.c b/tests/tcg
Tests added for the following instructions
J2_callrh
J2_jumprh
Signed-off-by: Taylor Simpson
---
tests/tcg/hexagon/v73_scalar.c| 96 +++
tests/tcg/hexagon/Makefile.target | 2 +
2 files changed, 98 insertions(+)
create mode 100644 tests/tcg/hexagon
---
tests/tcg/hexagon/v6mpy_ref.h | 161 ++
tests/tcg/hexagon/v68_hvx.c | 90 +
tests/tcg/hexagon/Makefile.target | 3 +
3 files changed, 254 insertions(+)
create mode 100644 tests/tcg/hexagon/v6mpy_ref.h
create mode 100644 tests/tcg/hexag
The following instructions are added
V6_v6mpyvubs10_vxx
V6_v6mpyhubs10_vxx
V6_v6mpyvubs10
V6_v6mpyhubs10
Signed-off-by: Taylor Simpson
---
target/hexagon/mmvec/macros.h| 9 +-
target/hexagon/imported/mmvec/encode_ext.def | 8 +-
target/hexagon/imported/mmvec
The following instructions are added
J2_callrh
J2_junprh
Signed-off-by: Taylor Simpson
---
target/hexagon/gen_tcg.h | 4
target/hexagon/attribs_def.h.inc | 1 +
target/hexagon/imported/branch.idef | 7 ++-
target/hexagon/imported/encode_pp.def | 2 ++
4
F2_dfimm_n
F2_dfmpyll
F2_dfmpylh
To make these instructions work, we fix some bugs in parser-helpers.c
gen_rvalue_extend
gen_cast_op
imm_print
Test cases added to tests/tcg/hexagon/fpstuff.c
Signed-off-by: Taylor Simpson
---
target/hexagon/idef-parser/parser-helpers.h | 2
> -Original Message-
> From: Richard Henderson
> Sent: Wednesday, April 26, 2023 12:32 PM
> To: Taylor Simpson ; qemu-devel@nongnu.org
> Cc: phi...@linaro.org; a...@rev.ng; a...@rev.ng; Brian Cain
> ; Matheus Bernardino (QUIC)
> ; pbonz...@redhat.com;
> mar
> -Original Message-
> From: Anton Johansson
> Sent: Wednesday, April 26, 2023 1:06 PM
> To: Taylor Simpson ; qemu-devel@nongnu.org
> Cc: richard.hender...@linaro.org; phi...@linaro.org; a...@rev.ng; Brian Cain
> ; Matheus Bernardino (QUIC)
>
> Subject: Re: [PA
> -Original Message-
> From: Richard Henderson
> Sent: Wednesday, April 26, 2023 4:23 PM
> To: Taylor Simpson ; qemu-devel@nongnu.org
> Cc: phi...@linaro.org; a...@rev.ng; a...@rev.ng; Brian Cain
> ; Matheus Bernardino (QUIC)
>
> Subject: Re: [PATCH 08/21]
> -Original Message-
> From: Paolo Bonzini
> Sent: Thursday, April 27, 2023 7:57 AM
> To: qemu-devel@nongnu.org
> Cc: Taylor Simpson
> Subject: [PATCH] target/hexagon: fix = vs. == mishap
>
> WARNING: This email originated from outside of Qualcomm. Please b
Tests added for the following instructions
J2_callrh
J2_jumprh
Signed-off-by: Taylor Simpson
Reviewed-by: Anton Johansson
---
tests/tcg/hexagon/v73_scalar.c| 96 +++
tests/tcg/hexagon/Makefile.target | 2 +
2 files changed, 98 insertions(+)
create mode
The encodings for these instructions changed some "don't care" bits
L2_loadw_locked
L4_loadd_locked
S2_storew_locked
S4_stored_locked
Signed-off-by: Taylor Simpson
Reviewed-by: Anton Johansson
---
target/hexagon/gen_tcg.h| 18 ++
The following instructions are tested
V6_vasrvuhubrndsat
V6_vasrvuhubsat
V6_vasrvwuhrndsat
V6_vasrvwuhsat
V6_vassign_tmp
V6_vcombine_tmp
V6_vmpyuhvs
Signed-off-by: Taylor Simpson
Reviewed-by: Anton Johansson
---
tests/tcg/hexagon/v69_hvx.c | 318
Signed-off-by: Taylor Simpson
Reviewed-by: Anton Johansson
---
tests/tcg/hexagon/v68_scalar.c| 186 ++
tests/tcg/hexagon/Makefile.target | 2 +
2 files changed, 188 insertions(+)
create mode 100644 tests/tcg/hexagon/v68_scalar.c
diff --git a/tests/tcg/hexagon
The following instructions are added
V6_v6mpyvubs10_vxx
V6_v6mpyhubs10_vxx
V6_v6mpyvubs10
V6_v6mpyhubs10
Signed-off-by: Taylor Simpson
Reviewed-by: Anton Johansson
---
target/hexagon/mmvec/macros.h| 9 +-
target/hexagon/imported/mmvec/encode_ext.def | 8
The following instructions are added
J2_callrh
J2_junprh
Signed-off-by: Taylor Simpson
Reviewed-by: Anton Johansson
---
target/hexagon/gen_tcg.h | 4
target/hexagon/attribs_def.h.inc | 1 +
target/hexagon/imported/branch.idef | 7 ++-
target/hexagon
Add support for the ELF flags
Move target/hexagon/cpu.[ch] to be v73
Change the compiler flag used by "make check-tcg"
The decbin instruction is removed in Hexagon v73, so check the
version before trying to compile the instruction.
Signed-off-by: Taylor Simpson
Reviewed-by: Anton
Taylor Simpson (9):
Hexagon (target/hexagon) Add support for v68/v69/v71/v73
Hexagon (target/hexagon) Add v68 scalar instructions
Hexagon (tests/tcg/hexagon) Add v68 scalar tests
Hexagon (target/hexagon) Add v68 HVX instructions
Hexagon (tests/tcg/hexagon) Add v68 HVX tests
Hexagon
Signed-off-by: Taylor Simpson
Reviewed-by: Anton Johansson
---
tests/tcg/hexagon/v68_hvx.c | 90 +
tests/tcg/hexagon/v6mpy_ref.c.inc | 161 ++
tests/tcg/hexagon/Makefile.target | 3 +
3 files changed, 254 insertions(+)
create mode 100644
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