Various forms of declare, read, write, free
Signed-off-by: Taylor Simpson
---
target/hexagon/macros.h | 388
1 file changed, 388 insertions(+)
create mode 100644 target/hexagon/macros.h
diff --git a/target/hexagon/macros.h b/target/hexagon
Run the C preprocessor across the instruction definition and encoding
files to expand macros and prepare the iset.py file. The resulting
fill contains python data structures used to build the decode tree.
Signed-off-by: Taylor Simpson
---
target/hexagon/gen_dectree_import.c | 205
Changes to packet semantics to support HVX
Signed-off-by: Taylor Simpson
---
target/hexagon/translate.c | 174 +
target/hexagon/translate.h | 30
2 files changed, 204 insertions(+)
diff --git a/target/hexagon/translate.c b/target/hexagon
Signed-off-by: Taylor Simpson
---
target/hexagon/macros.h | +++
1 file changed, insertions(+)
diff --git a/target/hexagon/macros.h b/target/hexagon/macros.h
index 4399585..e89fe4c 100644
--- a/target/hexagon/macros.h
+++ b/target/hexagon
Utility functions called by various instructions
Signed-off-by: Taylor Simpson
---
target/hexagon/arch.c | 664 +
target/hexagon/arch.h | 62
target/hexagon/conv_emu.c | 370 +++
target/hexagon/conv_emu.h | 50 +++
target/hexagon
the macro.
Signed-off-by: Taylor Simpson
---
target/hexagon/imported/allext_macros.def | 25 +
target/hexagon/imported/mmvec/macros.def | 1110 +
2 files changed, 1135 insertions(+)
create mode 100644 target/hexagon/imported/allext_macros.def
create mode 100755
Helpers for load-locked/store-conditional
Signed-off-by: Taylor Simpson
---
target/hexagon/genptr_helpers.h | 52 +
1 file changed, 52 insertions(+)
diff --git a/target/hexagon/genptr_helpers.h b/target/hexagon/genptr_helpers.h
index 2b91fdb..b780522
Signed-off-by: Taylor Simpson
---
target/hexagon/helper.h| 1 +
target/hexagon/op_helper.c | 75 ++
2 files changed, 76 insertions(+)
diff --git a/target/hexagon/helper.h b/target/hexagon/helper.h
index 5dc0f71..3e4728d 100644
--- a/target
Used to determine legal VLIW slots for each instruction
Signed-off-by: Taylor Simpson
---
target/hexagon/iclass.c | 109
target/hexagon/iclass.h | 46
2 files changed, 155 insertions(+)
create mode 100644 target/hexagon
Signed-off-by: Taylor Simpson
---
target/hexagon/decode.c | 23 +-
target/hexagon/mmvec/decode_ext_mmvec.c | 673
target/hexagon/mmvec/decode_ext_mmvec.h | 24 ++
target/hexagon/q6v_decode.c | 14 +
4 files changed, 732 insertions
Override store instructions
Signed-off-by: Taylor Simpson
---
target/hexagon/helper_overrides.h | 241 ++
1 file changed, 241 insertions(+)
diff --git a/target/hexagon/helper_overrides.h
b/target/hexagon/helper_overrides.h
index 673b7a5..648fc5d 100644
Include the generated files and set up the data structures
Signed-off-by: Taylor Simpson
---
target/hexagon/genptr.c | 60 +
target/hexagon/genptr.h | 25 +
2 files changed, 85 insertions(+)
create mode 100644 target/hexagon
Override predicated store instructions
Signed-off-by: Taylor Simpson
---
target/hexagon/helper_overrides.h | 54 +++
1 file changed, 54 insertions(+)
diff --git a/target/hexagon/helper_overrides.h
b/target/hexagon/helper_overrides.h
index 648fc5d..9791d33
Helpers for instructions overriden for optimization
Signed-off-by: Taylor Simpson
---
target/hexagon/genptr_helpers.h | 314
1 file changed, 314 insertions(+)
diff --git a/target/hexagon/genptr_helpers.h b/target/hexagon/genptr_helpers.h
index 85b449a
Override predicated load instructions
Signed-off-by: Taylor Simpson
---
target/hexagon/helper_overrides.h | 235 ++
1 file changed, 235 insertions(+)
diff --git a/target/hexagon/helper_overrides.h
b/target/hexagon/helper_overrides.h
index 553..673b7a5
Override compound compare and jump instructions
Signed-off-by: Taylor Simpson
---
target/hexagon/helper_overrides.h | 105 ++
1 file changed, 105 insertions(+)
diff --git a/target/hexagon/helper_overrides.h
b/target/hexagon/helper_overrides.h
index 52e4a47
Override dczeroa, allocframe, and return instructions
Signed-off-by: Taylor Simpson
---
target/hexagon/helper_overrides.h | 209 ++
1 file changed, 209 insertions(+)
diff --git a/target/hexagon/helper_overrides.h
b/target/hexagon/helper_overrides.h
index
Read the instruction memory
Create a packet data structure
Generate TCG code for the start of the packet
Invoke the generate function for each instruction
Generate TCG code for the end of the packet
Signed-off-by: Taylor Simpson
---
target/hexagon/translate.c | 732
Override compare, transfer, conditional jump instructions
Signed-off-by: Taylor Simpson
---
target/hexagon/helper_overrides.h | 119 ++
1 file changed, 119 insertions(+)
diff --git a/target/hexagon/helper_overrides.h
b/target/hexagon/helper_overrides.h
Signed-off-by: Taylor Simpson
---
target/hexagon/mmvec/macros.h | 436 ++
1 file changed, 436 insertions(+)
diff --git a/target/hexagon/mmvec/macros.h b/target/hexagon/mmvec/macros.h
index 80adb83..93d86e7 100644
--- a/target/hexagon/mmvec/macros.h
+++ b
Signed-off-by: Taylor Simpson
---
target/hexagon/gdbstub.c | 62
1 file changed, 62 insertions(+)
diff --git a/target/hexagon/gdbstub.c b/target/hexagon/gdbstub.c
index f07cb9a..e97b0af 100644
--- a/target/hexagon/gdbstub.c
+++ b/target/hexagon
Signed-off-by: Taylor Simpson
---
target/hexagon/imported/allextenc.def| 20 +
target/hexagon/imported/encode.def | 1 +
target/hexagon/imported/mmvec/encode_ext.def | 830 +++
3 files changed, 851 insertions(+)
create mode 100644 target/hexagon
Add HVX support to the semantics generator
Signed-off-by: Taylor Simpson
---
target/hexagon/do_qemu.py | 175 ++---
target/hexagon/gen_semantics.c | 9 +++
2 files changed, 171 insertions(+), 13 deletions(-)
diff --git a/target/hexagon/do_qemu.py b
Various forms of declare, read, write, free for HVX operands
Signed-off-by: Taylor Simpson
---
target/hexagon/mmvec/macros.h | 232 ++
1 file changed, 232 insertions(+)
create mode 100644 target/hexagon/mmvec/macros.h
diff --git a/target/hexagon/mmvec
Functions to support scatter/gather
Signed-off-by: Taylor Simpson
---
target/hexagon/mmvec/system_ext_mmvec.c | 265
target/hexagon/mmvec/system_ext_mmvec.h | 38 +
2 files changed, 303 insertions(+)
create mode 100644 target/hexagon/mmvec
; From: Philippe Mathieu-Daudé
> Sent: Tuesday, February 11, 2020 1:02 AM
> To: Taylor Simpson ; qemu-devel@nongnu.org
> Cc: richard.hender...@linaro.org; laur...@vivier.eu; riku.voi...@iki.fi;
> aleksandar.m.m...@gmail.com
> Subject: Re: [RFC PATCH 55/66] Hexagon HVX import instruction e
Reviewed-by: Taylor Simpson
> -Original Message-
> From: Richard Henderson
> Sent: Tuesday, February 11, 2020 8:52 PM
> To: qemu-devel@nongnu.org
> Cc: peter.mayd...@linaro.org; alex.ben...@linaro.org; Taylor Simpson
>
> Subject: [PATCH 2/2] target/arm: Use tcg_g
Reviewed-by: Taylor Simpson
> -Original Message-
> From: Richard Henderson
> Sent: Tuesday, February 11, 2020 8:52 PM
> To: qemu-devel@nongnu.org
> Cc: peter.mayd...@linaro.org; alex.ben...@linaro.org; Taylor Simpson
>
> Subject: [PATCH 1/2] tcg: Add tcg_gen_gvec
Tested-by: Taylor Simpson
> -Original Message-
> From: Laurent Vivier
> Sent: Wednesday, February 12, 2020 6:57 AM
> To: qemu-devel@nongnu.org
> Cc: Aleksandar Markovic ; Laurent Vivier
> ; Matus Kysel ;
> milos.stojano...@rt-rk.com; Riku Voipio ; Josh Kunz
>
> -Original Message-
> From: Philippe Mathieu-Daudé
> Sent: Tuesday, February 11, 2020 1:41 AM
> To: Taylor Simpson ; qemu-devel@nongnu.org
> Cc: richard.hender...@linaro.org; laur...@vivier.eu; riku.voi...@iki.fi;
> aleksandar.m.m...@gmail.com
> Subject: Re: [RFC
> -Original Message-
> From: Matheus Tavares Bernardino
> Sent: Friday, January 13, 2023 7:39 AM
> To: qemu-devel@nongnu.org
> Cc: Taylor Simpson ; Brian Cain
> ; richard.hender...@linaro.org
> Subject: [PATCH 1/2] Hexagon (iclass): update J4_hintjumpr slot constra
> -Original Message-
> From: Matheus Tavares Bernardino
> Sent: Friday, January 13, 2023 7:39 AM
> To: qemu-devel@nongnu.org
> Cc: Taylor Simpson ; Brian Cain
> ; richard.hender...@linaro.org
> Subject: [PATCH 2/2] Hexagon (decode): look for pkts with multiple ins
-off-by: Markus Armbruster
> ---
> target/hexagon/hex_arch_types.h | 1 -
> target/hexagon/mmvec/macros.h | 1 -
> 2 files changed, 2 deletions(-)
Reviewed-by: Taylor Simpson
> -Original Message-
> From: Matheus Tavares Bernardino
> Sent: Wednesday, March 22, 2023 3:17 PM
> To: qemu-devel@nongnu.org
> Cc: Taylor Simpson ; richard.hender...@linaro.org;
> a...@rev.ng
> Subject: [PATCH] Hexagon (translate.c): avoid redundant PC updates o
> -Original Message-
> From: Alex Bennée
> Sent: Wednesday, March 29, 2023 10:34 AM
> To: Marco Liebel (QUIC)
> Cc: Taylor Simpson ; qemu-devel@nongnu.org
> Subject: Re: [PATCH] Use hexagon toolchain version 16.0.0
>
> Marco Liebel writes:
>
>
because the
imported semantics uses bit-reverse. However, they are
straightforward to implement in TCG with tcg_gen_ctzi_*
Test cases added to tests/tcg/hexagon/misc.c
Signed-off-by: Taylor Simpson
---
target/hexagon/gen_tcg.h | 24 +
tests/tcg/hexagon/misc.c | 56
Reducing the number of arguments reduces the overhead of the helper
call
Signed-off-by: Taylor Simpson
---
target/hexagon/helper.h| 4 ++--
target/hexagon/translate.h | 1 +
target/hexagon/op_helper.c | 4 ++--
target/hexagon/translate.c | 10 +-
4 files changed, 10 insertions
Signed-off-by: Taylor Simpson
---
target/hexagon/gen_tcg.h| 4 +-
target/hexagon/genptr.h | 10 ++---
target/hexagon/macros.h | 8
target/hexagon/genptr.c | 49 ++---
target/hexagon/idef-parser
-off-by: Taylor Simpson
---
target/hexagon/macros.h | 65 ++---
1 file changed, 22 insertions(+), 43 deletions(-)
diff --git a/target/hexagon/macros.h b/target/hexagon/macros.h
index 482a9c787f..f5f31b6930 100644
--- a/target/hexagon/macros.h
+++ b/target/hexagon
This will facilitate adding additional tests in separate .c files
Signed-off-by: Taylor Simpson
---
tests/tcg/hexagon/hvx_misc.h | 178 ++
tests/tcg/hexagon/hvx_misc.c | 160 +--
tests/tcg/hexagon/Makefile.target | 1 +
3 files
> -Original Message-
> From: Philippe Mathieu-Daudé
> Sent: Thursday, April 6, 2023 2:24 AM
> To: Taylor Simpson ; qemu-devel@nongnu.org
> Cc: richard.hender...@linaro.org; a...@rev.ng; a...@rev.ng; Brian Cain
> ; Matheus Bernardino (QUIC)
>
> Subject: Re: [P
This will facilitate adding additional tests in separate .c files
Signed-off-by: Taylor Simpson
---
tests/tcg/hexagon/hvx_misc.h | 178 ++
tests/tcg/hexagon/hvx_misc.c | 160 +--
tests/tcg/hexagon/Makefile.target | 1 +
3 files
> -Original Message-
> From: Matheus Bernardino (QUIC)
> Sent: Thursday, April 6, 2023 2:30 PM
> To: qemu-devel@nongnu.org
> Cc: Brian Cain ; Taylor Simpson
> ; alex.ben...@linaro.org; f4...@amsat.org;
> peter.mayd...@linaro.org; Sid Manning
> Subject: [PAT
The slot variable in helpers was only passed to log_reg_write function
where the argument is unused.
- Remove declaration from generated helper functions
- Remove slot argument from log_reg_write
Signed-off-by: Taylor Simpson
---
target/hexagon/macros.h| 2 +-
target/hexagon
work, we fix some bugs in parser-helpers.c
gen_rvalue_extend
gen_cast_op
Test cases added to tests/tcg/hexagon/fpstuff.c
Signed-off-by: Taylor Simpson
---
target/hexagon/idef-parser/parser-helpers.c | 16 +++---
tests/tcg/hexagon/fpstuff.c | 54
Most of these are not modelled in QEMU, so save the overhead of
calling a helper.
The only exception is dczeroa. It assigns to hex_dczero_addr, which
is handled during packet commit.
Signed-off-by: Taylor Simpson
---
target/hexagon/gen_tcg.h | 24
target/hexagon
> -Original Message-
> From: Richard Henderson
> Sent: Monday, April 10, 2023 8:30 PM
> To: Taylor Simpson ; qemu-devel@nongnu.org
> Cc: phi...@linaro.org; a...@rev.ng; a...@rev.ng; Brian Cain
> ; Matheus Bernardino (QUIC)
>
> Subject: Re: [PATCH] Hexagon (targe
Add control registers (c4, c5) to clobbers list
Made possible by new toolchain container
Signed-off-by: Taylor Simpson
---
tests/tcg/hexagon/preg_alias.c | 10 +-
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/tests/tcg/hexagon/preg_alias.c b/tests/tcg/hexagon
The F2_sffms instruction [r0 -= sfmpy(r1, r2)] doesn't properly
handle -0. Previously we would negate the input operand by subtracting
from zero. Instead, we negate by changing the sign bit.
Test case added to tests/tcg/hexagon/fpstuff.c
Signed-off-by: Taylor Simpson
---
target/he
,$0x1
brcond_i32 tmp0,$0x0,eq,$L1
and_i32 tmp0,r0,r1
mov_i32 new_r2,tmp0
br $L2
set_label $L1
or_i32 slot_cancelled,slot_cancelled,$0x8
set_label $L2
mov_i32 r2,new_r2
We'll remove the unnecessary manipulation of slot_cancelled in a
subsequent patch.
Signed-off-by: Taylor Simpson
-
reg_write[_pair] is called
It's only needed for special operands VxxV and VyV
Remove gen_log_qreg_write
Signed-off-by: Taylor Simpson
---
target/hexagon/cpu.h| 3 --
target/hexagon/gen_tcg_hvx.h| 17 +---
target/hexagon/translate.h | 16 +++-
Signed-off-by: Taylor Simpson
---
target/hexagon/gen_tcg.h | 4 ++
target/hexagon/genptr.c | 79
2 files changed, 83 insertions(+)
diff --git a/target/hexagon/gen_tcg.h b/target/hexagon/gen_tcg.h
index 9e8f3373ad..6267f51ccc 100644
--- a/target/hexagon
: Taylor Simpson
---
target/hexagon/gen_tcg.h | 15 ++-
target/hexagon/genptr.c | 10 +-
2 files changed, 23 insertions(+), 2 deletions(-)
diff --git a/target/hexagon/gen_tcg.h b/target/hexagon/gen_tcg.h
index 19697b42a5..d644e59a63 100644
--- a/target/hexagon/gen_tcg.h
+++ b
container
Changes in v4
Additional patch for bug fix
Remove pkt_has_store_s1 from runtime state with dealloc-return patch
New patches to utilize new analyzer to improve predicated instructions
Taylor Simpson (13):
Hexagon (target/hexagon) Add overrides for jumpr31 instructions
d the intermediate
step of writing to hex_new_value. Note that other checks will also
be needed (e.g., no instructions can raise an exception).
Signed-off-by: Taylor Simpson
---
target/hexagon/translate.h | 46 ++--
target/hexagon/genptr.c | 5 +-
t
SL2_return_fnew
This patch eliminates the last helper that uses write_new_pc, so we
remove it from op_helper.c
This patch also eliminates the last helper for load instructions, so we
remove the pkt_has_store_s1 runtime field as well as the mem_load[1248]
functions.
Signed-off-by: Taylor Simpson
Extend the analyze_ functions for HVX vector and predicate writes
Remove calls to ctx_log_vreg_write[_pair] from gen_tcg_funcs.py
During gen_start_packet, reload the predicated HVX registers into
fugure_VRegs and tmp_VRegs
Signed-off-by: Taylor Simpson
---
target/hexagon/translate.h
Add overrides for
J2_callr
J2_callrt
J2_callrf
Signed-off-by: Taylor Simpson
---
target/hexagon/gen_tcg.h | 6 ++
target/hexagon/macros.h | 12 +---
target/hexagon/genptr.c | 20
3 files changed, 27 insertions(+), 11 deletions(-)
diff --git a
Made possible by new toolchain container
Signed-off-by: Taylor Simpson
---
tests/tcg/hexagon/Makefile.target | 13 -
1 file changed, 12 insertions(+), 1 deletion(-)
diff --git a/tests/tcg/hexagon/Makefile.target
b/tests/tcg/hexagon/Makefile.target
index 18e6a5969e..f753b39d91
We only need to track slot for predicated stores and predicated HVX
instructions.
Add arguments to the probe helper functions to indicate if the slot
is predicated.
Signed-off-by: Taylor Simpson
---
target/hexagon/macros.h | 2 +-
target/hexagon/op_helper.h
Replace __builtin_* with inline assembly
The __builtin's are subject to change with different compiler
releases, so might break
Mark arrays as aligned when accessed as HVX vectors
Clean up comments
Signed-off-by: Taylor Simpson
---
tests/tcg/hexagon/scatter_gather.c
ulation of slot_cancelled in a
subsequent patch.
Signed-off-by: Taylor Simpson
---
target/hexagon/gen_tcg.h| 7 +-
target/hexagon/macros.h | 17 ---
target/hexagon/genptr.c | 120
target/hexagon/idef-parser/parser
: Taylor Simpson
---
target/hexagon/translate.h | 1 +
target/hexagon/attribs_def.h.inc| 1 +
target/hexagon/translate.c | 6 +-
target/hexagon/gen_analyze_funcs.py | 5 +
target/hexagon/hex_common.py| 1 +
5 files changed, 13 insertions(+), 1 deletion(-)
diff
reg_write[_pair] is called
It's only needed for special operands VxxV and VyV
Remove gen_log_qreg_write
Signed-off-by: Taylor Simpson
---
target/hexagon/cpu.h| 5 +--
target/hexagon/gen_tcg_hvx.h| 17 +---
target/hexagon/translate.h | 16 +++-
d the intermediate
step of writing to hex_new_value. Note that other checks will also
be needed (e.g., no instructions can raise an exception).
Signed-off-by: Taylor Simpson
---
target/hexagon/translate.h | 46 ++--
target/hexagon/genptr.c | 5 +-
t
Made possible by new toolchain container
Signed-off-by: Taylor Simpson
---
tests/tcg/hexagon/Makefile.target | 13 -
1 file changed, 12 insertions(+), 1 deletion(-)
diff --git a/tests/tcg/hexagon/Makefile.target
b/tests/tcg/hexagon/Makefile.target
index 18e6a5969e..f753b39d91
Replace __builtin_* with inline assembly
The __builtin's are subject to change with different compiler
releases, so might break
Mark arrays as aligned when accessed as HVX vectors
Clean up comments
Signed-off-by: Taylor Simpson
---
tests/tcg/hexagon/scatter_gather.c
Add overrides for
J2_callr
J2_callrt
J2_callrf
Signed-off-by: Taylor Simpson
---
target/hexagon/gen_tcg.h | 6 ++
target/hexagon/macros.h | 12 +---
target/hexagon/genptr.c | 20
3 files changed, 27 insertions(+), 11 deletions(-)
diff --git a
lyzer
Additional patch to determine when pkt_has_store_s1 needs to be set
Update fGEN_TCG_ to preserve --disable-hexagon-idef-parser config
in Remove gen_log_predicated_reg_write[_pair] patch
Move tcg_temp_free_i64 into gen_log_vreg_write
Add get_result_qreg function
Taylor Simpson (14):
He
new_r2,r2
and_i32 tmp0,p0,$0x1
brcond_i32 tmp0,$0x0,eq,$L1
and_i32 tmp0,r0,r1
mov_i32 new_r2,tmp0
br $L2
set_label $L1
set_label $L2
mov_i32 r2,new_r2
Signed-off-by: Taylor Simpson
---
target/hexagon/macros.h | 2 +-
target/hexagon/op_helper.h | 3
Signed-off-by: Taylor Simpson
---
target/hexagon/gen_tcg.h | 4 ++
target/hexagon/genptr.c | 79
2 files changed, 83 insertions(+)
diff --git a/target/hexagon/gen_tcg.h b/target/hexagon/gen_tcg.h
index 9e8f3373ad..6267f51ccc 100644
--- a/target/hexagon
Add control registers (c4, c5) to clobbers list
Made possible by new toolchain container
Signed-off-by: Taylor Simpson
---
tests/tcg/hexagon/preg_alias.c | 10 +-
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/tests/tcg/hexagon/preg_alias.c b/tests/tcg/hexagon
The F2_sffms instruction [r0 -= sfmpy(r1, r2)] doesn't properly
handle -0. Previously we would negate the input operand by subtracting
from zero. Instead, we negate by changing the sign bit.
Test case added to tests/tcg/hexagon/fpstuff.c
Signed-off-by: Taylor Simpson
---
target/he
: Taylor Simpson
---
target/hexagon/gen_tcg.h | 15 ++-
target/hexagon/genptr.c | 10 +-
2 files changed, 23 insertions(+), 2 deletions(-)
diff --git a/target/hexagon/gen_tcg.h b/target/hexagon/gen_tcg.h
index 19697b42a5..d644e59a63 100644
--- a/target/hexagon/gen_tcg.h
+++ b
SL2_return_fnew
This patch eliminates the last helper that uses write_new_pc, so we
remove it from op_helper.c
Signed-off-by: Taylor Simpson
---
target/hexagon/gen_tcg.h | 54
target/hexagon/genptr.c| 86 ++
target/hexagon/op_helper.c
Extend the analyze_ functions for HVX vector and predicate writes
Remove calls to ctx_log_vreg_write[_pair] from gen_tcg_funcs.py
During gen_start_packet, reload the predicated HVX registers into
fugure_VRegs and tmp_VRegs
Signed-off-by: Taylor Simpson
---
target/hexagon/translate.h
> -Original Message-
> From: Anton Johansson
> Sent: Tuesday, January 31, 2023 4:32 PM
> To: qemu-devel@nongnu.org
> Cc: a...@rev.ng; Taylor Simpson ; Brian Cain
> ; Michael Lambert
> Subject: [PATCH] target/hexagon/idef-parser: Remove unused code paths
>
>
> -Original Message-
> From: Anton Johansson
> Sent: Wednesday, February 1, 2023 6:30 AM
> To: Taylor Simpson ; qemu-devel@nongnu.org
> Cc: richard.hender...@linaro.org; phi...@linaro.org; a...@rev.ng; Brian Cain
> ; Matheus Bernardino (QUIC)
>
> Subject: Re:
> -Original Message-
> From: Richard Henderson
> Sent: Wednesday, November 17, 2021 1:18 AM
> To: Philippe Mathieu-Daudé ; qemu-devel@nongnu.org
> Cc: Laurent Vivier ; Taylor Simpson
>
> Subject: Re: [PATCH] linux-user/hexagon: Use generic target_stat64
> struc
i ; Vladimir
> Sementsov-Ogievskiy ; Eduardo Habkost
> ; Taylor Simpson ;
> k...@vger.kernel.org; Paolo Bonzini ; Kevin Wolf
> ; Philippe Mathieu-Daudé
> Subject: [PATCH-for-6.2? v2 2/3] misc: Spell QEMU all caps
>
> QEMU should be written all caps.
>
> Normally checkpatc
> -Original Message-
> From: Matheus Tavares Bernardino
> Sent: Monday, May 8, 2023 8:37 AM
> To: qemu-devel@nongnu.org
> Cc: Taylor Simpson
> Subject: [PATCH v2] Hexagon (decode): look for pkts with multiple insns at
> the same slot
>
> Each slot in a p
> -Original Message-
> From: Taylor Simpson
> Sent: Tuesday, May 9, 2023 11:46 AM
> To: Matheus Tavares Bernardino ; qemu-
> de...@nongnu.org
> Subject: RE: [PATCH v2] Hexagon (decode): look for pkts with multiple insns
> at the same slot
>
>
>
> >
> -Original Message-
> From: Matheus Tavares Bernardino
> Sent: Thursday, May 4, 2023 10:38 AM
> To: qemu-devel@nongnu.org
> Cc: alex.ben...@linaro.org; Brian Cain ;
> f4...@amsat.org; peter.mayd...@linaro.org; Taylor Simpson
> ; phi...@linaro.org;
> rich
> -Original Message-
> From: Marco Liebel (QUIC)
> Sent: Tuesday, May 9, 2023 1:43 PM
> To: qemu-devel@nongnu.org
> Cc: Taylor Simpson ; Brian Cain
> ; Matheus Bernardino (QUIC)
> ; Marco Liebel (QUIC)
>
> Subject: [PATCH] Remove test_vshuff from hvx_misc te
> -Original Message-
> From: Brian Cain
> Sent: Tuesday, May 9, 2023 3:01 PM
> To: Taylor Simpson ; Marco Liebel (QUIC)
> ; qemu-devel@nongnu.org
> Cc: Matheus Bernardino (QUIC)
> Subject: RE: [PATCH] Remove test_vshuff from hvx_misc tests
>
>
&
> -Original Message-
> From: Taylor Simpson
> Sent: Saturday, April 29, 2023 2:57 PM
> To: Richard Henderson ; qemu-
> de...@nongnu.org
> Cc: phi...@linaro.org; a...@rev.ng; a...@rev.ng; Brian Cain
> ; Matheus Bernardino (QUIC)
>
> Subject: RE: [PATCH v2 0
> -Original Message-
> From: Matheus Tavares Bernardino
> Sent: Friday, January 13, 2023 7:39 AM
> To: qemu-devel@nongnu.org
> Cc: Taylor Simpson ; Brian Cain
> ; richard.hender...@linaro.org
> Subject: [PATCH 1/2] Hexagon (iclass): update J4_hintjumpr slot constra
Signed-off-by: Taylor Simpson
Reviewed-by: Anton Johansson
Message-Id: <20230427224057.3766963-4-tsimp...@quicinc.com>
---
tests/tcg/hexagon/v68_scalar.c| 186 ++
tests/tcg/hexagon/Makefile.target | 2 +
2 files changed, 188 insertions(+)
create mode
The following instructions are added
V6_vasrvuhubrndsat
V6_vasrvuhubsat
V6_vasrvwuhrndsat
V6_vasrvwuhsat
V6_vassign_tmp
V6_vcombine_tmp
V6_vmpyuhvs
Signed-off-by: Taylor Simpson
Reviewed-by: Anton Johansson
Message-Id: <20230427224057.3766963-7-tsimp...@quicinc.
instructions at the same slot during decoding time and
throw an invalid packet exception. That will be done in the subsequent
commit.
Signed-off-by: Matheus Tavares Bernardino
Reviewed-by: Taylor Simpson
Signed-off-by: Taylor Simpson
Message-Id:
<0fcd8293642c6324119fbbab44741164b
The following instructions are added
J2_callrh
J2_junprh
Signed-off-by: Taylor Simpson
Reviewed-by: Anton Johansson
Message-Id: <20230427224057.3766963-9-tsimp...@quicinc.com>
---
target/hexagon/gen_tcg.h | 4
target/hexagon/attribs_def.h.inc | 1 +
: Taylor Simpson
Reviewed-by: Richard Henderson
Message-Id: <20230427230012.3800327-19-tsimp...@quicinc.com>
---
target/hexagon/cpu.h| 1 -
target/hexagon/gen_tcg.h| 12 ++--
target/hexagon/translate.h | 2 +-
target/h
These instructions have implicit reads from p0, so we don't want
them in helpers when idef-parser is off.
Signed-off-by: Taylor Simpson
Reviewed-by: Richard Henderson
Message-Id: <20230427230012.3800327-6-tsimp...@quicinc.com>
---
target/hexagon/gen_tcg.h | 16
tar
The following instructions are added
V6_v6mpyvubs10_vxx
V6_v6mpyhubs10_vxx
V6_v6mpyvubs10
V6_v6mpyhubs10
Signed-off-by: Taylor Simpson
Reviewed-by: Anton Johansson
Message-Id: <20230427224057.3766963-5-tsimp...@quicinc.com>
---
target/hexagon/mmvec/macros.h
Add support for the ELF flags
Move target/hexagon/cpu.[ch] to be v73
Change the compiler flag used by "make check-tcg"
The decbin instruction is removed in Hexagon v73, so check the
version before trying to compile the instruction.
Signed-off-by: Taylor Simpson
Reviewed-by: Anton
The following instructions are tested
V6_vasrvuhubrndsat
V6_vasrvuhubsat
V6_vasrvwuhrndsat
V6_vasrvwuhsat
V6_vassign_tmp
V6_vcombine_tmp
V6_vmpyuhvs
Signed-off-by: Taylor Simpson
Reviewed-by: Anton Johansson
Message-Id: <20230427224057.3766963-8-tsimp...@quicinc.
Reviewed-by: Taylor Simpson
Tested-by: Taylor Simpson
Signed-off-by: Taylor Simpson
Message-Id: <20230509184231.2467626-1-quic_mlie...@quicinc.com>
---
tests/tcg/hexagon/hvx_misc.c | 45
1 file changed, 45 deletions(-)
diff --git a/tests/tcg/hexagon/hvx_mi
ction is an HVX instruction with a
generated helper.
We add an override for V6_vcombine so that it can be short-circuited
along with a test case in tests/tcg/hexagon/hvx_misc.c
Signed-off-by: Taylor Simpson
Reviewed-by: Richard Henderson
Message-Id: <20230427230012.3800327-15-tsimp...@qui
rly-exit from gen_pred_writes.
Signed-off-by: Taylor Simpson
Reviewed-by: Richard Henderson
Message-Id: <20230427230012.3800327-13-tsimp...@quicinc.com>
---
target/hexagon/genptr.h| 1 +
target/hexagon/genptr.c| 15 ---
target/hexagon/translate.c | 14 +++---
gen_rvalue_extend
gen_cast_op
imm_print
lexer properly sets size/signedness of constants
Test cases added to tests/tcg/hexagon/fpstuff.c
Signed-off-by: Taylor Simpson
Tested-by: Anton Johansson
Reviewed-by: Anton Johansson
Message-Id: <20230501203125.4025991-1-tsimp...@quicinc.com>
---
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