From: Stefan Markovic
Perform needed checks before actual prctl() PR_SET_FP_MODE and
PR_GET_FP_MODE work based on kernel implementation. Also, update
necessary hflags.
Signed-off-by: Stefan Markovic
---
linux-user/syscall.c | 18 ++
1 file changed, 18 insertions(+)
diff --git
On 15.11.18. 16:59, Aleksandar Markovic wrote:
> From: Aleksandar Markovic
>
> Add Stefan Markovic as a MIPS reviewer. He had several key
> contributions to QEMU for MIPS this year. He is a meticulous
> person with the ability to think and act on many levels.
>
> Sign
++
1 file changed, 109 insertions(+)
Reviewed-by: Stefan Markovic
diff --git a/target/mips/cpu.h b/target/mips/cpu.h
index 28af4d1..cd54073 100644
--- a/target/mips/cpu.h
+++ b/target/mips/cpu.h
@@ -195,6 +195,115 @@ struct CPUMIPSState {
#define MSAIR_ProcID8
On 15.10.2018. 12:50, Aleksandar Markovic wrote:
From: Aleksandar Markovic
Yongbok Kim used two email adresses for QEMU contributions -
his company changed its ownership/name.
Signed-off-by: Aleksandar Markovic
---
.mailmap | 1 +
1 file changed, 1 insertion(+)
Reviewed-by: Stefan
ON SET
+ *=
Misspelled EXTENSION. Otherwise:
Reviewed-by: Stefan Markovic
+ *
+ * MXU (full name: MIPS eXtension/enhanced Unit) is an SIMD extension of MIPS32
+ * instructions set. It is designed to fit the needs of signal, graphical and
+ * video processing application
* the control register.
*
+ * The notation used in MXU assembler mnemonics:
+ *
+ * XRa, XRb, XRa, XRb - MXU registers
XRa and XRb duplicated. Did You mean XRc and XRd instead? Otherwise:
Reviewed-by: Stefan Markovic
+ * Rb, Rc, Rd, Rs, Rt - general purpose MIPS registers
+ * s12
, 156 insertions(+)
Reviewed-by: Stefan Markovic
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 73d971e..4dfc360 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -1490,6 +1490,162 @@ enum {
* Q16SCOP XRa, XRb, XRc, XRdS32M2I XRa, Rb
(+)
Reviewed-by: Stefan Markovic
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 4dfc360..941b546 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -1652,6 +1652,282 @@ enum {
* Programming Manual", Ingenic Semiconductor Co, Ltd., 2017
*/
On 16.10.18. 16:00, Peter Maydell wrote:
On 23 August 2018 at 14:34, Aleksandar Markovic
wrote:
From: Stefan Markovic
Add emulation of DSP ASE instructions for nanoMIPS - part 1.
Reviewed-by: Aleksandar Markovic
Signed-off-by: Aleksandar Markovic
Signed-off-by: Stefan Markovic
Hi
(-)
Reviewed-by: Stefan Markovic
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 74ef160..1afb105 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -1,5 +1,5 @@
/*
- * MIPS32 emulation for qemu: main translation routines.
+ * MIPS emulation for QEMU: main
ate.c | 40
1 file changed, 32 insertions(+), 8 deletions(-)
Reviewed-by: Stefan Markovic
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 1afb105..e5db92e 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -463,8 +463,
S32SFL XRa, XRb, XRc, XRd, optn2 Q16SARV XRa, XRb, Rb
> @@ -1504,7 +1504,7 @@ enum {
>*
>* ┌─ 00 ─ OPC_MXU_S32MADD
>* ├─ 01 ─ OPC_MXU_S32MADDU
> - * ├─ 10 ─
> + * ├─ 10 ─ (non-MXU OPC_MULL)
OPC_MUL instead of OPC_MU
On 25.10.18. 10:49, Aleksandar Markovic wrote:
> From: Aleksandar Markovic
>
> Add nanoMIPS CRC32 instruction pool.
>
> Signed-off-by: Aleksandar Markovic
> ---
> target/mips/translate.c | 10 ++
> 1 file changed, 10 insertions(+)
Reviewed-by: Stefan Ma
gt; +generate_exception_end(ctx, EXCP_RI);
> +}
> +}
> +
> +/*
> + * This code generates a "reserved instruction" exception if the
> + * Config5 EVA bit is NOT set.
> + */
> +static inline void check_eva(DisasContext *ctx)
> +{
> +if (!unlike
On 24.10.18. 14:18, Aleksandar Markovic wrote:
> From: Aleksandar Markovic
>
> Provide the placeholder and add the invocation logic for MXU
> decoding engine.
>
> Signed-off-by: Aleksandar Markovic
> ---
> target/mips/translate.c | 8
> 1 file changed, 8 insertions(+)
>
> diff --git
xception_end(ctx, EXCP_RI);
> +break;
> +}
> +}
> +
> +/*
> + *
> + * Decode MXU pool01
> + *
> + * S32SLT, D16SLT, D16AVG, D16AVGR, Q8AVG, Q8AVGR:
> + * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
> + * +--
On 24.10.18. 14:18, Aleksandar Markovic wrote:
> From: Aleksandar Markovic
>
> Add bit encoding for MXU accumulate add/subtract 1-bit pattern
> 'aptn1'.
>
> Signed-off-by: Aleksandar Markovic
> ---
> target/mips/translate.c | 6 ++
> 1 file changed,
On 24.10.18. 14:18, Aleksandar Markovic wrote:
> From: Aleksandar Markovic
>
> Add bit encoding for MXU execute 2-bit add/subtract pattern 'eptn2'.
>
> Signed-off-by: Aleksandar Markovic
> ---
> target/mips/translate.c | 6 ++
> 1 file changed, 6 i
On 24.10.18. 14:18, Aleksandar Markovic wrote:
> From: Aleksandar Markovic
>
> Move MUL, S32M2I, S32I2M handling out of switch. These are all
> instructions that do not depend on MXU_EN flag of MXU_CR.
>
> Signed-off-by: Aleksandar Markovic
> ---
> target/mips/translate.c | 41
t/mips/translate.c | 509
> ++--
> 1 file changed, 238 insertions(+), 271 deletions(-)
Reviewed-by: Stefan Markovic
> diff --git a/target/mips/translate.c b/target/mips/translate.c
> index 61c1662..3620ae5 100644
> --- a/target/mips/translate.c
> +++ b/target/mips/translate
et/mips/translate.c | 84
> +++--
> 1 file changed, 74 insertions(+), 10 deletions(-)
Reviewed-by: Stefan Markovic
> diff --git a/target/mips/translate.c b/target/mips/translate.c
> index 3620ae5..9bd5f27 100644
> --- a/target/mips/translate.c
> +
From: Stefan Markovic
This series includes support for prctl() PR_GET_FP_MODE and PR_SET_FP_MODE.
This requires
extracting MIPS.abiflags section from ELF file and fp_abi value handling.
Stefan Markovic (6):
Define MIPS_ABI_FP_UNKNOWN macro
Extend image_info struct with MIPS specific fp_abi
From: Stefan Markovic
Signed-off-by: Stefan Markovic
---
linux-user/qemu.h | 4
1 file changed, 4 insertions(+)
diff --git a/linux-user/qemu.h b/linux-user/qemu.h
index 1beb6a2..a752c1c 100644
--- a/linux-user/qemu.h
+++ b/linux-user/qemu.h
@@ -61,6 +61,10 @@ struct image_info
From: Stefan Markovic
Floating-point mode is calculated from MIPS.abiflags FP ABI value
(based on kernel implementation). Illegal combinations are rejected.
Signed-off-by: Stefan Markovic
---
linux-user/mips/cpu_loop.c | 75 ++
1 file changed, 75
From: Stefan Markovic
Signed-off-by: Stefan Markovic
---
linux-user/elfload.c | 4
1 file changed, 4 insertions(+)
diff --git a/linux-user/elfload.c b/linux-user/elfload.c
index 5881233..5bccd2e 100644
--- a/linux-user/elfload.c
+++ b/linux-user/elfload.c
@@ -2396,6 +2396,7 @@ static
From: Stefan Markovic
Signed-off-by: Stefan Markovic
---
linux-user/elfload.c | 33 +
1 file changed, 33 insertions(+)
diff --git a/linux-user/elfload.c b/linux-user/elfload.c
index 055f6a9..5881233 100644
--- a/linux-user/elfload.c
+++ b/linux-user/elfload.c
From: Stefan Markovic
Signed-off-by: Stefan Markovic
---
linux-user/mips/target_syscall.h | 2 ++
linux-user/mips64/target_syscall.h | 2 ++
linux-user/syscall.c | 62 +++---
3 files changed, 62 insertions(+), 4 deletions(-)
diff --git a/linux
From: Stefan Markovic
Signed-off-by: Stefan Markovic
---
include/elf.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/include/elf.h b/include/elf.h
index 5f45f9b..c151164 100644
--- a/include/elf.h
+++ b/include/elf.h
@@ -87,6 +87,8 @@ typedef int64_t Elf64_Sxword;
#define
In that case, I guess this should be OK for now, as MXU support is
initiated by Craig and this will be
an easy add-on when he provide necessary information.
Reviewed-by: Stefan Markovic
On 28.10.18. 19:39, Aleksandar Markovic wrote:
>> Subject: Re: [PATCH v7 04/20] target/mips: A
Following the patch 04/20 discussion:
Reviewed-by: Stefan Markovic
On 26.10.18. 11:45, Stefan Markovic wrote:
>
> On 24.10.18. 14:18, Aleksandar Markovic wrote:
>> From: Aleksandar Markovic
>>
>> Move MUL, S32M2I, S32I2M handling out of switch. These are all
>
On 29.10.18. 12:15, Aleksandar Markovic wrote:
> From: Aleksandar Markovic
>
> Coverity found two fallthroughs that lack break statements. Fix them.
>
> Signed-off-by: Aleksandar Markovic
> ---
> target/mips/translate.c | 2 ++
> 1 file changed, 2 insertions(+)
Revi
: Friday, October 26, 2018 20:12 CEST
From: Peter Maydell
To: Stefan Markovic
CC: QEMU Developers , Petar Jovanovic
, Riku Voipio , Aleksandar
Markovic , Aurelien Jarno ,
Laurent Vivier
References: <1540563667-23300-1-git-send-email-stefan.marko...@rt-rk.com>
<1540563667-23300-6-git-s
From: Stefan Markovic
Implement MIPS specific prctl() PR_SET_FP_MODE and PR_GET_FP_MODE emulation.
Reviewed-by: Aleksandar Markovic
Signed-off-by: Stefan Markovic
---
linux-user/mips/target_syscall.h | 2 ++
linux-user/mips64/target_syscall.h | 2 ++
linux-user/syscall.c
From: Stefan Markovic
Floating-point mode is calculated from MIPS.abiflags FP ABI value
(based on kernel implementation). Illegal combinations are rejected.
Reviewed-by: Aleksandar Markovic
Signed-off-by: Stefan Markovic
---
linux-user/mips/cpu_loop.c | 75
From: Stefan Markovic
Add MIPS_ABI_FP_UNKNOWN as QEMU internal value to represent
unknown fp_abi (based on kernel mips/include/asm/elf.h definition)
Reviewed-by: Aleksandar Markovic
Signed-off-by: Stefan Markovic
---
include/elf.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/include
From: Stefan Markovic
Add MIPS specific image_info struct fields fp_abi and interp_fp_abi
to store executable and interpreter fp_abi values (based on kernel
struct arch_elf_state in mips/include/asm/elf.h).
Reviewed-by: Aleksandar Markovic
Signed-off-by: Stefan Markovic
---
linux-user/qemu.h
From: Stefan Markovic
This series includes support for prctl() PR_GET_FP_MODE and PR_SET_FP_MODE.
This requires
extracting MIPS.abiflags section from ELF file and fp_abi value handling.
v1->v2:
- added commit messages
- fixed exit() error codes and appropriate exit messages prin
From: Stefan Markovic
Read MIPS.abiflags section from ELF file into Mips_elf_abiflags_v0 struct.
Reviewed-by: Aleksandar Markovic
Signed-off-by: Stefan Markovic
---
linux-user/elfload.c | 33 +
1 file changed, 33 insertions(+)
diff --git a/linux-user
From: Stefan Markovic
Set fp_abi and interp_fp_abi values to current fp_abi value read from
MIPS.abiflags.
Reviewed-by: Aleksandar Markovic
Signed-off-by: Stefan Markovic
---
linux-user/elfload.c | 4
1 file changed, 4 insertions(+)
diff --git a/linux-user/elfload.c b/linux-user
On 30.10.18. 12:36, Aleksandar Markovic wrote:
> From: Aleksandar Markovic
>
> Rename MMI-related masks.
>
> Signed-off-by: Aleksandar Markovic
> ---
> target/mips/translate.c | 20 ++--
> 1 file changed, 10 insertions(+), 10 deletions(-)
Revi
nsertions(+), 235 deletions(-)
Reviewed-by: Stefan Markovic
> diff --git a/target/mips/translate.c b/target/mips/translate.c
> index e38d50d..4b008d8 100644
> --- a/target/mips/translate.c
> +++ b/target/mips/translate.c
> @@ -2099,7 +2099,7 @@ enum {
>* The T
On 30.10.18. 12:36, Aleksandar Markovic wrote:
> From: Aleksandar Markovic
>
> Rename MMI-related functions.
>
> Signed-off-by: Aleksandar Markovic
> ---
> target/mips/translate.c | 32
> 1 file changed, 16 insertions(+), 16 deletions(
On 25.11.18. 21:49, Philippe Mathieu-Daudé wrote:
> Signed-off-by: Philippe Mathieu-Daudé
> ---
> MAINTAINERS | 2 ++
> 1 file changed, 2 insertions(+)
Reviewed-by: Stefan Markovic
> diff --git a/MAINTAINERS b/MAINTAINERS
> index 007f89f126..4e396cbe71 100644
> ---
On 25.11.18. 21:49, Philippe Mathieu-Daudé wrote:
> Signed-off-by: Philippe Mathieu-Daudé
> ---
> MAINTAINERS | 1 +
> 1 file changed, 1 insertion(+)
Reviewed-by: Stefan Markovic
> diff --git a/MAINTAINERS b/MAINTAINERS
> index aa17e9bbd3..81a22b2ccf 100644
> ---
From: Stefan Markovic
Update QEMU documentation with nanoMIPS ISA info and add list of QEMU
supported MIPS/nanoMIPS CPU models.
Stefan Markovic (2):
qemu-doc: Add nanoMIPS ISA information
docs/qemu-cpu-models: Add MIPS/nanoMIPS QEMU supported CPU models
docs/qemu-cpu-models.texi | 163
From: Stefan Markovic
Add nanoMIPS information in qemu-doc.texi with example of usage
included.
Signed-off-by: Stefan Markovic
---
qemu-doc.texi | 29 +
1 file changed, 29 insertions(+)
diff --git a/qemu-doc.texi b/qemu-doc.texi
index f7ad1df..6ef593d 100644
--- a
From: Stefan Markovic
Add list of supported and preferred CPU models for MIPS32, MIPS64
and nanoMIPS hosts.
Signed-off-by: Stefan Markovic
---
docs/qemu-cpu-models.texi | 163 +-
1 file changed, 161 insertions(+), 2 deletions(-)
diff --git a/docs
efan,
>
> On 28/11/18 14:43, Stefan Markovic wrote:
>> From: Stefan Markovic
>>
>> Add nanoMIPS information in qemu-doc.texi with example of usage
>> included.
>>
>> Signed-off-by: Stefan Markovic
>> ---
>> qemu-doc.texi | 29 ++
Of course. Investigation is in progress.
Thanks,
Stefan
On 29.11.18. 11:23, Peter Maydell wrote:
> On Thu, 29 Nov 2018 at 10:18, Stefan Markovic wrote:
>> I'll investigate further running with --enable-debug option to fix this
>> issue.
>>
>> In the meantim
ensa/core-test_kc705_be/xtensa-modules.inc.c
> tests/tcg/cris/check_abs.c
> tests/tcg/cris/check_addc.c
> tests/tcg/cris/check_addcm.c
> tests/tcg/cris/check_addoq.c
> tests/tcg/cris/check_bound.c
> tests/tcg/cris/check_ftag.c
> tes
+---
> 2 files changed, 8 insertions(+), 6 deletions(-)
Reviewed-by: Stefan Markovic
> diff --git a/disas/nanomips.cpp b/disas/nanomips.cpp
> index 1238c2ff33..f9ef0a25f4 100644
> --- a/disas/nanomips.cpp
> +++ b/disas/nanomips.cpp
> @@ -1,13 +1,13 @@
> /*
>* Sour
-
> disas/nanomips.cpp | 264 ++---
> disas/nanomips.h | 2 +-
> 2 files changed, 133 insertions(+), 133 deletions(-)
Reviewed-by: Stefan Markovic
> diff --git a/disas/nanomips.cpp b/disas/nanomips.cpp
> index 935c2dee3c..cfad1
disas/nanomips.h | 32 ++---
> 2 files changed, 72 insertions(+), 72 deletions(-)
Reviewed-by: Stefan Markovic
> diff --git a/disas/nanomips.cpp b/disas/nanomips.cpp
> index 9e876305f1..477df84d93 100644
> --- a/disas/nanomips.cpp
> +++ b/disas/nanomips.cpp
> @@ -683,7
> disas/nanomips.cpp | 208 -
> disas/nanomips.h | 25 --
> 2 files changed, 233 deletions(-)
Reviewed-by: Stefan Markovic
> diff --git a/disas/nanomips.cpp b/disas/nanomips.cpp
> index f9ef0a25f4..935c2dee3c 100644
> ---
t; be now complete.
>
> Signed-off-by: Aleksandar Markovic
> ---
> target/mips/translate.c | 140 +---
> 1 file changed, 102 insertions(+), 38 deletions(-)
Reviewed-by: Stefan Markovic
> diff --git a/target/mips/translate.c b/target
d, 170 insertions(+), 12 deletions(-)
Reviewed-by: Stefan Markovic
> diff --git a/target/mips/translate.c b/target/mips/translate.c
> index e3a5a73e59..c74a831a17 100644
> --- a/target/mips/translate.c
> +++ b/target/mips/translate.c
> @@ -24649,6 +24649,172 @@ static void gen_
et/mips/translate.c | 74 -
> 1 file changed, 44 insertions(+), 30 deletions(-)
Reviewed-by: Stefan Markovic
> diff --git a/target/mips/translate.c b/target/mips/translate.c
> index 74d16ce52e..e3a5a73e59 100644
> --- a/target/mips/translate.c
> +++ b/target/mips/tra
d, 335 insertions(+), 21 deletions(-)
Reviewed-by: Stefan Markovic
> diff --git a/target/mips/translate.c b/target/mips/translate.c
> index c74a831a17..339de8c32b 100644
> --- a/target/mips/translate.c
> +++ b/target/mips/translate.c
> @@ -24815,6 +24815,338 @@ stati
ed, 194 insertions(+), 3 deletions(-)
Reviewed-by: Stefan Markovic
> diff --git a/target/mips/translate.c b/target/mips/translate.c
> index 339de8c32b..96905b78ac 100644
> --- a/target/mips/translate.c
> +++ b/target/mips/translate.c
> @@ -25147,6 +25147,199 @@ static voi
On 3.1.19. 17:34, Aleksandar Markovic wrote:
> From: Aleksandar Markovic
>
> Add preprocessor constants for 32 major CP0 registers.
>
> Signed-off-by: Aleksandar Markovic
> ---
> target/mips/cpu.h | 32
> 1 file changed, 32 insertions(
--
> target/mips/cpu.h | 165
> +++---
> 1 file changed, 84 insertions(+), 81 deletions(-)
Reviewed-by: Stefan Markovic
> diff --git a/target/mips/cpu.h b/target/mips/cpu.h
> index 03c03fd..6c2a7e4 100644
> --- a/t
+--
> 2 files changed, 12 insertions(+), 4 deletions(-)
Reviewed-by: Stefan Markovic
> diff --git a/target/mips/cpu.h b/target/mips/cpu.h
> index b095422..1c2c682 100644
> --- a/target/mips/cpu.h
> +++ b/target/mips/cpu.h
> @@ -164,8 +164,8 @@ typedef struct mips_de
> 1 file changed, 136 insertions(+), 136 deletions(-)
Reviewed-by: Stefan Markovic
> diff --git a/target/mips/translate.c b/target/mips/translate.c
> index e9c23a5..6af292f 100644
> --- a/target/mips/translate.c
> +++ b/target/mips/translate.c
> @@ -6476,7 +6476,7 @@ static void
On 3.1.19. 17:34, Aleksandar Markovic wrote:
> From: Yongbok Kim
>
> Update ITU to handle bus errors.
>
> Signed-off-by: Yongbok Kim
> Signed-off-by: Aleksandar Markovic
> ---
> hw/misc/mips_itu.c | 22 ++
> 1 file changed, 22 insertions(+)
R
| 6 +
> target/mips/internal.h | 1 +
> target/mips/op_helper.c | 50 +
> target/mips/translate.c | 66
> ++---
> 5 files changed, 120 insertions(+), 4 deletions(-)
Reviewed-by: Stefan Markovic
ude/hw/misc/mips_itu.h | 4
> 2 files changed, 25 insertions(+), 1 deletion(-)
Reviewed-by: Stefan Markovic
> diff --git a/hw/misc/mips_itu.c b/hw/misc/mips_itu.c
> index 43bbec4..4801958 100644
> --- a/hw/misc/mips_itu.c
> +++ b/hw/misc/mips_itu.c
> @@ -55,9 +55,17 @@ t
isc/mips_itu.c | 28 ++--
> include/hw/misc/mips_itu.h | 4
> target/mips/cpu.h | 5 +
> target/mips/op_helper.c| 14 ++
> 5 files changed, 53 insertions(+), 6 deletions(-)
Reviewed-by: Stefan Markovic
> diff --git a/hw/
default:
Regards,
Stefan
From: Philippe Mathieu-Daudé on behalf of
Philippe Mathieu-Daudé
Sent: Wednesday, July 4, 2018 10:31:27 PM
To: Aleksandar Markovic; qemu-devel@nongnu.org; Richard Henderson
Cc: aurel...@aurel32.net; Aleksandar Markovic; Stefan Markov
July 5, 2018 5:13:42 PM
To: Stefan Markovic; Aleksandar Markovic; qemu-devel@nongnu.org; Richard
Henderson
Cc: Petar Jovanovic; Aleksandar Markovic; aurel...@aurel32.net; Paul Burton
Subject: Re: [Qemu-devel] [PATCH v3 5/8] target/mips: Add CP0 BadInstrX register
On 07/05/2018 10:27 AM, Stefan Mar
c: f4...@amsat.org; aurel...@aurel32.net; Stefan Markovic; Petar Jovanovic;
Paul Burton
Subject: Re: [PATCH v2 32/33] gdbstub: Add XML support for GDB for nanoMIPS
> Subject: [PATCH v2 32/33] gdbstub: Add XML support for GDB for nanoMIPS
>
> From: Stefan Markovic
>
> Add XML support files
From: Aleksandar Markovic
Add ISA_NANOMIPS32 and CPU_NANOMIPS32 preprocessor constants.
Reviewed-by: Richard Henderson
Signed-off-by: Yongbok Kim
Signed-off-by: Aleksandar Markovic
Signed-off-by: Stefan Markovic
---
target/mips/mips-defs.h | 4
1 file changed, 4 insertions(+)
diff
From: Aleksandar Markovic
Remove "range style" case statements to make code analysis easier.
This is needed also for some upcoming nanoMIPS-related refactorings.
Signed-off-by: Aleksandar Markovic
Reviewed-by: Philippe Mathieu-Daudé
---
target/mips/translate.c | 249 +
From: Yongbok Kim
Config3.ISAOnExc is read only in nanoMIPS.
Signed-off-by: Yongbok Kim
Signed-off-by: Aleksandar Markovic
Signed-off-by: Stefan Markovic
---
target/mips/op_helper.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/target/mips/op_helper.c b/target/mips
From: Yongbok Kim
BadVAddr should not be updated if (env->hflags & MIPS_HFLAG_DM) is
set.
Signed-off-by: Yongbok Kim
Signed-off-by: Aleksandar Markovic
Reviewed-by: Philippe Mathieu-Daudé
---
target/mips/helper.c| 4 +++-
target/mips/op_helper.c | 12 +---
2 files changed, 12 in
From: Yongbok Kim
Add emulation of LI48, ADDIU48, ADDIUGP48, ADDIUPC48, LWPC48, and
SWPC48 instructions.
Signed-off-by: Yongbok Kim
Signed-off-by: Aleksandar Markovic
Signed-off-by: Stefan Markovic
Reviewed-by: Aleksandar Markovic
---
target/mips/translate.c | 66
From: Aleksandar Markovic
Remove duplicate preprocessor constant definition for EF_MIPS_ARCH.
The duplicate was introduced in commit 45506bdd.
Signed-off-by: Aleksandar Markovic
---
include/elf.h | 1 -
1 file changed, 1 deletion(-)
diff --git a/include/elf.h b/include/elf.h
index 934dbbd..c
From: Aleksandar Markovic
Synchronize content of linux-user/mips/syscall_nr.h and
linux-user/mips64/syscall_nr.h with Linux kernel 4.18 headers.
This adds 7 new syscall numbers, the last being NR_statx.
Signed-off-by: Aleksandar Markovic
Signed-off-by: Stefan Markovic
---
linux-user/mips
MIPS machine variants
linux-user: Update MIPS syscall numbers up to kernel 4.18 headers
Aleksandar Rikalo (1):
linux-user: Add availability control to some syscalls
Stefan Markovic (1):
target/mips: Add CP0 BadInstrX register
Yongbok Kim (2):
target/mips: Don't update BadVAddr regist
From: Stefan Markovic
Signed-off-by: Yongbok Kim
Signed-off-by: Aleksandar Markovic
Signed-off-by: Stefan Markovic
---
target/mips/helper.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/target/mips/helper.c b/target/mips/helper.c
index 5299f21..9535131 100644
--- a/target/mips
From: Yongbok Kim
Add emulation of basic floating point arithmetic for nanoMIPS.
Signed-off-by: Yongbok Kim
Signed-off-by: Aleksandar Markovic
Signed-off-by: Stefan Markovic
Reviewed-by: Aleksandar Markovic
---
target/mips/translate.c | 300
From: Aleksandar Markovic
Add MIPS machine variants ELF flags so that the emulation behavior
can be adjusted if needed.
Signed-off-by: Aleksandar Markovic
Signed-off-by: Stefan Markovic
---
include/elf.h | 23 +++
1 file changed, 23 insertions(+)
diff --git a/include
From: Yongbok Kim
Add emulation of nanoMIPS instructions that are situated in pool32a0.
Signed-off-by: Yongbok Kim
Signed-off-by: Aleksandar Markovic
Signed-off-by: Stefan Markovic
Reviewed-by: Aleksandar Markovic
---
target/mips/translate.c | 190
From: Yongbok Kim
Add emulation of nanoMIPS instructions situated in pool p_lsx, and
emulation of LSA instruction as well.
Signed-off-by: Yongbok Kim
Signed-off-by: Aleksandar Markovic
Signed-off-by: Stefan Markovic
Reviewed-by: Aleksandar Markovic
---
target/mips/translate.c | 139
From: Yongbok Kim
Add emulation of LWXS16, LB16, SB16, LBU16, LH16, SH16, LHU16, LW16, LWSP16,
LW4X4, SW4X4, LWGP16, SWSP16, SW16, and SWGP16 instructions.
Signed-off-by: Yongbok Kim
Signed-off-by: Aleksandar Markovic
Signed-off-by: Stefan Markovic
---
target/mips/translate.c | 114
From: Aleksandar Markovic
Update email addresses of Aleksandar Markovic and Paul Burton in the
MAINTAINERS file. Also, add corresponding items in the .mailmap file.
Signed-off-by: Aleksandar Markovic
Reviewed-by: Philippe Mathieu-Daudé
---
.mailmap| 7 +--
MAINTAINERS | 9 +
2
From: Yongbok Kim
MFHC0 and MTHC0 used to handle EntryLo0 and EntryLo1 registers only,
and placing ELPA flag checks before switch statement were technically
correct. However, after adding handling more registers, these checks
should be moved to act only in cases of handling EntryLo0 and
EntryLo1.
From: Aleksandar Rikalo
Signed-off-by: Aleksandar Markovic
Signed-off-by: Stefan Markovic
---
linux-user/strace.c | 14 +-
linux-user/syscall.c | 25 +
2 files changed, 38 insertions(+), 1 deletion(-)
diff --git a/linux-user/strace.c b/linux-user/strace.c
From: Aleksandar Markovic
Update CP0 registers Config0, Config1, Config2, Config3,
Config4, and Config5 bit definitions.
Some of these bits will be utilized by upcoming nanoMIPS changes.
Signed-off-by: Aleksandar Markovic
Reviewed-by: Philippe Mathieu-Daudé
---
target/mips/cpu.h | 157 ++
From: Stefan Markovic
Add nanoMIPS opcodes for DSP ASE instruction pools and instructions.
Signed-off-by: Aleksandar Markovic
Signed-off-by: Stefan Markovic
---
target/mips/translate.c | 144
1 file changed, 144 insertions(+)
diff --git a
arget/mips: Implement emulation of nanoMIPS ROTX instruction
target/mips: Add handling of branch delay slots for nanoMIPS
mips_malta: Add basic nanoMIPS boot code for MIPS' Malta
Paul Burton (1):
mips_malta: Setup GT64120 BARs in nanoMIPS bootloader
Stefan Markovic (8):
target/mips: Ad
From: Aleksandar Markovic
If checkpatch.pl is applied (using switch "-f") on file
target/mips/msa_helper.c, it will hang.
This is a workaround by correcting the source file. The workaround is
found by partial deleting and undeleting of the code in msa_helper.c
in binary search fashion.
The bug
From: Yongbok Kim
Add emulation of misc nanoMIPS 16-bit instructions from instruction
pools P16, P16.BR, P16.BRI, P16.4X4 and other related pools.
Signed-off-by: Yongbok Kim
Signed-off-by: Aleksandar Markovic
Signed-off-by: Stefan Markovic
---
target/mips/translate.c | 258
From: Yongbok Kim
Add emulation of various nanoMIPS load and store instructions.
Signed-off-by: Yongbok Kim
Signed-off-by: Aleksandar Markovic
Signed-off-by: Stefan Markovic
Reviewed-by: Aleksandar Markovic
---
target/mips/translate.c | 271
From: Yongbok Kim
Add some basic utility functions and macros for nanoMIPS decoding
engine.
Signed-off-by: Yongbok Kim
Signed-off-by: Aleksandar Markovic
Signed-off-by: Stefan Markovic
---
target/mips/translate.c | 35 +++
1 file changed, 35 insertions
From: Yongbok Kim
Add empty body and invocation of decode_nanomips_opc() if the bit
ISA_NANOMIPS32 is set in env->insn_flags.
Signed-off-by: Yongbok Kim
Signed-off-by: Aleksandar Markovic
Signed-off-by: Stefan Markovic
---
target/mips/translate.c | 22 --
1 file chan
From: Aleksandar Markovic
Signed-off-by: Aleksandar Markovic
Signed-off-by: Stefan Markovic
---
linux-user/mips/cpu_loop.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/linux-user/mips/cpu_loop.c b/linux-user/mips/cpu_loop.c
index 1d3dc9e..c9c20cf 100644
--- a/linux-user/mips
From: Matthew Fortune
ISA mode bit (LSB of address) is no longer required but is also
masked to allow for tools transition. The flag has_isa_mode has the
key role in the implementation.
Signed-off-by: Yongbok Kim
Signed-off-by: Aleksandar Markovic
Signed-off-by: Stefan Markovic
---
target
From: Yongbok Kim
Add emulation of various flavors of nanoMIPS branch instructions.
Signed-off-by: Yongbok Kim
Signed-off-by: Aleksandar Markovic
Signed-off-by: Stefan Markovic
Reviewed-by: Aleksandar Markovic
---
target/mips/translate.c | 277
From: Yongbok Kim
Add emulation of NOT16, AND16, XOR16, OR16 instructions.
Reviewed-by: Richard Henderson
Signed-off-by: Yongbok Kim
Signed-off-by: Aleksandar Markovic
Signed-off-by: Stefan Markovic
---
target/mips/translate.c | 22 ++
1 file changed, 22 insertions
From: Aleksandar Markovic
Add nanoMIPS-related values in ELF header fields as specified in
nanoMIPS' "ELF ABI Supplement".
Signed-off-by: Aleksandar Markovic
Signed-off-by: Stefan Markovic
---
include/elf.h | 20
1 file changed, 20 insertions(+)
diff
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