Re: [Qemu-devel] [PATCH 8/8] target/mips: Update ITU to handle bus errors

[Stefan Markovic]

On 3.1.19. 17:34, Aleksandar Markovic wrote:
> From: Yongbok Kim <yongbok....@mips.com>
>
> Update ITU to handle bus errors.
>
> Signed-off-by: Yongbok Kim <yongbok....@mips.com>
> Signed-off-by: Aleksandar Markovic <amarko...@wavecomp.com>
> ---
>   hw/misc/mips_itu.c | 22 ++++++++++++++++++++++
>   1 file changed, 22 insertions(+)


Reviewed-by: Stefan Markovic <smarko...@wavecomp.com>


> diff --git a/hw/misc/mips_itu.c b/hw/misc/mips_itu.c
> index 5c49bdd..e8860dc 100644
> --- a/hw/misc/mips_itu.c
> +++ b/hw/misc/mips_itu.c
> @@ -375,6 +375,12 @@ static void view_pv_try_write(ITCStorageCell *c)
>       view_pv_common_write(c);
>   }
>   
> +static void raise_exception(int excp)
> +{
> +    current_cpu->exception_index = excp;
> +    cpu_loop_exit(current_cpu);
> +}
> +
>   static uint64_t itc_storage_read(void *opaque, hwaddr addr, unsigned size)
>   {
>       MIPSITUState *s = (MIPSITUState *)opaque;
> @@ -382,6 +388,14 @@ static uint64_t itc_storage_read(void *opaque, hwaddr 
> addr, unsigned size)
>       ITCView view = get_itc_view(addr);
>       uint64_t ret = -1;
>   
> +    switch (size) {
> +    case 1:
> +    case 2:
> +        s->icr0 |= 1 << ITC_ICR0_ERR_AXI;
> +        raise_exception(EXCP_DBE);
> +        return 0;
> +    }
> +
>       switch (view) {
>       case ITCVIEW_BYPASS:
>           ret = view_bypass_read(cell);
> @@ -420,6 +434,14 @@ static void itc_storage_write(void *opaque, hwaddr addr, 
> uint64_t data,
>       ITCStorageCell *cell = get_cell(s, addr);
>       ITCView view = get_itc_view(addr);
>   
> +    switch (size) {
> +    case 1:
> +    case 2:
> +        s->icr0 |= 1 << ITC_ICR0_ERR_AXI;
> +        raise_exception(EXCP_DBE);
> +        return;
> +    }
> +
>       switch (view) {
>       case ITCVIEW_BYPASS:
>           view_bypass_write(cell, data);