I have made a bare metal "Hello World" program for the Netduino2. I have
pushed it here:
https://github.com/skintigh/baremetal_netduino2
It should output "Test 1/4" to USART 1, "Test 2/4" to USART 2, "Test 3/4"
to USART 3 and "Test 4/4" to UART 4.
What actually happens in QEMU is only the first
T4 to /tmp/uart4. 2 and 3
still disappear but that seems to be a bug and I have reported it. Now to
test this on a chip with 8 UARTS...
Thanks again!
On Wed, Oct 5, 2016 at 5:21 PM, Alistair Francis
wrote:
> On Wed, Oct 5, 2016 at 10:45 AM, Seth K wrote:
> > Thanks for that link.
> &
The only machine I saw listed in the help output is "netduino2." I pulled
QEMU from github, was that the right thing to do?
I found the specifications for the stm32f2xx and some similar chips and
verified the addresses and interrupts are correct.
The stm32f205 should support 6 UARTs, and the 6 ad
ote:
> > On Fri, Oct 7, 2016 at 8:59 AM, Seth K wrote:
> >> The only machine I saw listed in the help output is "netduino2." I
> pulled
> >> QEMU from github, was that the right thing to do?
> >>
> >> I found the specifications for the st
zy?
I don't understand Qemu enough to know what should be calling the functions
that handle UART read/write. Is there something I should look at in Qemu
and try to intercept?
On Fri, Oct 7, 2016 at 6:27 PM, Alistair Francis
wrote:
> On Fri, Oct 7, 2016 at 1:04 PM, Seth K wrote:
> >
of 3804 which means
nothing.
On Wed, Oct 12, 2016 at 6:25 PM, Seth K wrote:
> It's a bare metal program so I don't really have anywhere to print to,
> other than my custom function to output to the uart. I did double check all
> the address to make sure they agreed with the
Thank you all for help with my last patch. I found one more entry in my
notes that could be a bug, or could be a misunderstanding on my part.
The memory map in DocID15818 (Rev 15) datasheet says:
ADC1 - ADC2 - ADC3: 0x40012000-0x400123FF
That suggests a size of 0x400 (they share that range?)
I corrected these 2 memory regions based on specifications from the chip
manufacturer. The existing ranges seem to overlap and and cause odd
behavior and/or crashes when trying to set up multiple UARTs,
I also played with changing MAX_SERIAL_PORTS to 8 to match the hardware,
but I did not include t
On Thu, Nov 15, 2018 at 7:05 AM Peter Maydell
wrote:
> On 4 November 2018 at 07:42, Seth K wrote:
> > I corrected these 2 memory regions based on specifications from the chip
> > manufacturer. The existing ranges seem to overlap and and cause odd
> > behavior and/or cra
19 November 2018 at 10:43, Philippe Mathieu-Daudé
> wrote:
> > > > Hi Seth,
> > > >
> > > > On Mon, Nov 19, 2018 at 4:17 AM Seth K wrote:
> > > >>
> > > >> From: Seth Kintigh
> > > >>
> > > >> I corre
I need to simulate 3 chips that are on one board and that talk to each
other through UART, SPI and GPIO. The chips verify each other's work, and I
need to be able to observe this communication for debugging. Can something
like this be done in QEMU?
My first thought was to create the chip then crea
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