On 21/06/2023 09:39, Gerd Hoffmann wrote:
On Tue, Jun 20, 2023 at 01:26:15PM +0100, Robert Beckett wrote:
On 20/06/2023 10:41, Gerd Hoffmann wrote:
Hi,
The guest driver should be able to restore resources after resume.
Thank you for your suggestion!
As far as I know, resources are
On 08/06/2023 03:56, Jiqian Chen wrote:
After suspending and resuming guest VM, you will get
a black screen, and the display can't come back.
This is because when guest did suspending, it called
into qemu to call virtio_gpu_gl_reset. In function
virtio_gpu_gl_reset, it destroyed resources and
On Thu, 2023-02-02 at 12:05 +0100, Igor Mammedov wrote:
> MultiBitFeatureInfo looks like an interesting
> idea
Yeah, we can feel how much effort Lei spent on this.
> but among fixing whatever issues this has atm,
> you'd probably need to introduce a new qdev_bitfield property
> infrastructure s
In the rollback in msix_set_vector_notifiers(), original patch forgot to
undo msix_vector_poll_notifier pointer.
Fixes: bbef882cc193 ("msi: add API to get notified about pending bit poll")
Signed-off-by: Robert Hoo
---
hw/pci/msix.c | 1 +
1 file changed, 1 insertion(+)
diff --gi
On 11/13/2023 6:05 PM, Philippe Mathieu-Daudé wrote:
Hi Robert,
On 13/11/23 09:13, Robert Hoo wrote:
In the rollback in msix_set_vector_notifiers(), original patch forgot to
undo msix_vector_poll_notifier pointer.
Out of curiosity, nobody complained during 11 years, so in which
use case did
On Thu, 2021-12-23 at 20:29 +0800, Chao Peng wrote:
> From: "Kirill A. Shutemov"
>
> The patch introduces new MEMFD_OPS facility around file created by
> memfd_create() to allow a third kernel component to make use of
> memory
> bookmarked in a memfd and gets notifier when the memory in the file
On Mon, 2021-04-19 at 17:59 -0400, Eduardo Habkost wrote:
> On Mon, Apr 19, 2021 at 04:18:25PM -0400, Eduardo Habkost wrote:
> > On Fri, Apr 16, 2021 at 10:08:24AM +0800, Robert Hoo wrote:
> > > Since commit fa4518741e (target-i386: Rename struct XMMReg to
> > > ZMMReg),
Hi,
Ping...
Thanks.
On Thu, 2021-04-29 at 09:35 +0800, Robert Hoo wrote:
> As it's been marked deprecated since v5.2, now I think it's time
> remove it
> from code.
>
> Signed-off-by: Robert Hoo
> ---
> Changelog:
> v3:
> Update deprecated.rs
The '-display' help information is not very correct. This patch sort
it a little.
Also, in its help information, reveals what implicit display option
will be chosen if no definition.
Changelog:
v2:
--fix typo of 'display'
--change some discription words
Signed-off-by:
}
}
return 0;
}
static void __exit remover_module_exit(void)
{
printk(KERN_INFO "forcefully-remove-bootfb unloaded\n");
}
module_init(remover_module_init);
module_exit(remover_module_exit);
module_param(bootfb_start, ullong, );
module_param(bootfb_end, ullong, );
MODULE_LICENSE("Dual BSD/GPL");
MODULE_AUTHOR("Robert Ou ");
MODULE_DESCRIPTION("Forcefully removes BOOTFB I/O resource");
On Jul 12, 2016 08:12, "Alex Williamson" wrote:
>
> On Tue, 12 Jul 2016 02:30:44 -0700
> Robert Ou wrote:
>
> > I would like to report on a hack that I created to successfully use
> > vfio-pci to pass through a boot GPU. The short TL;DR summary is that
> &
me time to understand the framework help message generation.
Signed-off-by: Robert Ho
---
qemu-options.hx | 32 +---
1 file changed, 25 insertions(+), 7 deletions(-)
diff --git a/qemu-options.hx b/qemu-options.hx
index 17f15ad..69cf668 100644
--- a/qemu-options.hx
Public bug reported:
At least qemu-i368 and qemu-x86_64 hang in floatx80_sqrt in versions
2.6.0 and git (2.6.50) for some input values, likely due to an infinite
loop at fpu/softfloat.c:6569.
Steps to reproduce:
1) Compile attached code: gcc -o test test.c -lm
2) `qemu-i368 test` and `qemu-x86_64
hcp_decode', if an options'
>> length 'len' appeared towards the end of 'bp_vend' array, ensuing
>> read could lead to an OOB memory access issue. Add check to avoid it.
>>
>> Reported-by: Reno Robert
>> Signed-off-by: Prasad
Public bug reported:
We had an illumos user trying to run illumos in QEMU 2.9.0 with the
qemu-xhci device enabled. Note, that while this was discovered against
QEMU 2.9.0, from my current read of the HEAD, it is still present. The
illumos bug at https://www.illumos.org/issues/8173 has additional
i
Hi,
>From $qemu_src/qga/ code, guest-exec should be supported.
But from $qemu_src/scripts/qmp/qemu-ga-client output, it is not supported, on
client side. Why didn't implement on client side? or any configuration I missed?
Best Regards,
Robert Hoo
t in guest to execute
some program? any other utils?
Best Regards,
Robert Hoo
Best Regards,
Robert Hoo
> -Original Message-
> From: Michael Roth [mailto:mdr...@linux.vnet.ibm.com]
> Sent: Wednesday, August 2, 2017 0:44
> To: Hu, Robert ; qemu-devel@nongnu.org; qemu-
> disc...@nongnu.org
> Subject: Re: [Qemu-devel] Does qemu guest agent s
Thanks for fixing. Sorry I missed the whole discussion for I hadn't checked my
linux.intel.com account for a long time.
Best Regards,
Robert Hoo
> -Original Message-
> From: Qemu-devel
> On Behalf Of Bandan Das
> Sent: Monday, November 26, 2018 12:17
> To: Edu
wrapper (g_strdup_printf) instead of native
(sprintf).
v3: patch 2&3 in v2 are corrupted. Re-format patches.
v2: coding style changes to pass ./scripts/checkpatch.pl.
Robert Hoo (3):
kvm: Add support to KVM_GET_MSR_FEATURE_INDEX_LIST and KVM_GET_MSRS
system ioctl
x86: Data struc
Add kvm_get_supported_feature_msrs() to get supported MSR feature index list.
Add kvm_arch_get_supported_msr_feature() to get each MSR features value.
Signed-off-by: Robert Hoo
---
include/sysemu/kvm.h | 2 ++
target/i386/kvm.c| 80
2
Note RSBA is specially treated -- no matter host support it or not, qemu
pretends it is supported.
Signed-off-by: Robert Hoo
---
target/i386/cpu.c | 31 ++-
target/i386/cpu.h | 8
target/i386/kvm.c | 11 +++
3 files changed, 49 insertions(+), 1
Add FeatureWordType indicator in struct FeatureWordInfo.
Change feature_word_info[] accordingly.
Change existing functions that refer to feature_word_info[] accordingly.
Signed-off-by: Robert Hoo
---
target/i386/cpu.c | 188 +++---
1 file changed
On Wed, 2018-10-24 at 07:16 -0300, Eduardo Habkost wrote:
> On Mon, Oct 15, 2018 at 12:47:24PM +0800, Robert Hoo wrote:
> > Add FeatureWordType indicator in struct FeatureWordInfo.
> > Change feature_word_info[] accordingly.
> > Change existing functions that refer
On Wed, 2018-10-24 at 07:06 -0300, Eduardo Habkost wrote:
> On Mon, Oct 15, 2018 at 12:47:25PM +0800, Robert Hoo wrote:
> > Note RSBA is specially treated -- no matter host support it or not,
> > qemu
> > pretends it is supported.
> >
> > Signed-off-by: Robert
On Wed, 2018-10-24 at 07:06 -0300, Eduardo Habkost wrote:
> On Mon, Oct 15, 2018 at 12:47:25PM +0800, Robert Hoo wrote:
> > Note RSBA is specially treated -- no matter host support it or not,
> > qemu
> > pretends it is supported.
> >
> > Signed-off-by: Robert
Note RSBA is specially treated -- no matter host support it or not, qemu
pretends it is supported.
Changes in v6: filter out MSR features whose dependent CPUID enumeration is not
there.
Signed-off-by: Robert Hoo
Reviewed-by: Eduardo Habkost
---
target/i386/cpu.c | 31
Add kvm_get_supported_feature_msrs() to get supported MSR feature index list.
Add kvm_arch_get_supported_msr_feature() to get each MSR features value.
Signed-off-by: Robert Hoo
Reviewed-by: Eduardo Habkost
---
include/sysemu/kvm.h | 2 ++
target/i386/kvm.c| 80
(sprintf).
v3: patch 2&3 in v2 are corrupted. Re-format patches.
v2: coding style changes to pass ./scripts/checkpatch.pl.
Robert Hoo (3):
kvm: Add support to KVM_GET_MSR_FEATURE_INDEX_LIST and KVM_GET_MSRS
system ioctl
x86: Data structure changes to support MSR based features
Add FeatureWordType indicator in struct FeatureWordInfo.
Change feature_word_info[] accordingly.
Change existing functions that refer to feature_word_info[] accordingly.
Signed-off-by: Robert Hoo
---
target/i386/cpu.c | 205 --
target/i386
On Thu, 2018-09-20 at 00:07 -0300, Eduardo Habkost wrote:
> Hi,
>
> Thanks for the patch and sorry for taking so long to review it.
Never mind. I understand you're really busy. :-)
>
> On Sun, Sep 02, 2018 at 07:46:06PM +0800, Robert Hoo wrote:
> > Add kvm_get_suppo
On Thu, 2018-09-20 at 00:13 -0300, Eduardo Habkost wrote:
> On Sun, Sep 02, 2018 at 07:46:07PM +0800, Robert Hoo wrote:
> > Note RSBA is specially treated -- no matter host support it or not,
> > qemu
> > pretends it is supported.
> >
> > Signed-off-by: Robert Ho
On Thu, 2018-09-20 at 14:22 -0300, Eduardo Habkost wrote:
> On Thu, Sep 20, 2018 at 03:45:42PM +0800, Robert Hoo wrote:
> [...]
> > > > diff --git a/target/i386/cpu.c b/target/i386/cpu.c
> > > > index a252c26..0160e97 100644
> > > > --- a/target/
On Thu, 2018-09-20 at 14:18 -0300, Eduardo Habkost wrote:
> On Thu, Sep 20, 2018 at 05:55:48PM +0800, Robert Hoo wrote:
> > On Thu, 2018-09-20 at 00:13 -0300, Eduardo Habkost wrote:
> > > On Sun, Sep 02, 2018 at 07:46:07PM +0800, Robert Hoo wrote:
> > > > Note R
PCONFIG is not supposed to be exposed to guest. These 2 patches fix this.
Robert Hoo (2):
i386: remove the new CPUID 'PCONFIG' from Icelake-Server CPU model
Revert "i386: Add CPUID bit for PCONFIG"
target/i386/cpu.c | 5 ++---
target/i386/cpu.h | 1 -
2 files changed
Signed-off-by: Robert Hoo
---
target/i386/cpu.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index 677a3bd..b6113d0 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -2613,8 +2613,7 @@ static X86CPUDefinition builtin_x86_defs
This reverts commit 5131dc433df54b37e8e918d8fba7fe10344e7a7b.
For new instruction 'PCONFIG' will not be exposed to guest.
Signed-off-by: Robert Hoo
---
target/i386/cpu.c | 2 +-
target/i386/cpu.h | 1 -
2 files changed, 1 insertion(+), 2 deletions(-)
diff --git a/target/i386/cpu.
On Wed, 2018-12-19 at 14:01 +, Daniel P. Berrangé wrote:
> On Wed, Dec 19, 2018 at 09:44:40PM +0800, Robert Hoo wrote:
> > Signed-off-by: Robert Hoo
> > ---
> > target/i386/cpu.c | 3 +--
> > 1 file changed, 1 insertion(+), 2 deletions(-)
> >
> > diff
On Thu, 2018-12-20 at 13:38 +0100, Paolo Bonzini wrote:
> On 20/12/18 01:18, Robert Hoo wrote:
> > On Wed, 2018-12-19 at 14:01 +, Daniel P. Berrangé wrote:
> > > On Wed, Dec 19, 2018 at 09:44:40PM +0800, Robert Hoo wrote:
> > > > Signed-off-by: Robert Hoo
&g
On Fri, 2018-12-21 at 07:27 +0100, Paolo Bonzini wrote:
> On 20/12/18 13:50, Robert Hoo wrote:
> > On Thu, 2018-12-20 at 13:38 +0100, Paolo Bonzini wrote:
> > > On 20/12/18 01:18, Robert Hoo wrote:
> > > > I think the sooner, the better. Take the time window th
On Fri, 2018-12-21 at 16:03 +0100, Paolo Bonzini wrote:
> On 21/12/18 15:04, Robert Hoo wrote:
> > > So this series is correct and I will follow up with one for
> > > INTEL_PT;
> > > however, this begs the question of how the patches are being
> > > tested.
On Fri, 2018-12-21 at 16:27 +0100, Paolo Bonzini wrote:
> On 21/12/18 16:22, Philippe Mathieu-Daudé wrote:
> > Hi Paolo,
> >
> > On 12/21/18 7:30 AM, Paolo Bonzini wrote:
> > > From: Robert Hoo
> > >
> > > Processor tracing is not yet implemen
On Sat, 2018-12-22 at 10:13 +0100, Paolo Bonzini wrote:
> On 22/12/18 02:01, Robert Hoo wrote:
> > On Fri, 2018-12-21 at 16:27 +0100, Paolo Bonzini wrote:
> > > On 21/12/18 16:22, Philippe Mathieu-Daudé wrote:
> > > > Hi Paolo,
> > > >
> &
On Thu, 2018-08-23 at 14:11 -0300, Eduardo Habkost wrote:
> On Thu, Aug 23, 2018 at 02:28:28PM +0800, Robert Hoo wrote:
> > On Sat, 2018-08-18 at 12:05 -0300, Eduardo Habkost wrote:
> [...]
> > > We don't want QEMU to refuse to run if the kernel doesn't have
> >
).
v3: patch 2&3 in v2 are corrupted. Re-format patches.
v2: coding style changes to pass ./scripts/checkpatch.pl.
Robert Hoo (3):
x86: Data structure changes to support MSR based features
kvm: Add support to KVM_GET_MSR_FEATURE_INDEX_LIST and
KVM_GET_MSRS system ioctl
x86: defi
Add kvm_get_supported_feature_msrs() to get supported MSR feature index list.
Add kvm_arch_get_supported_msr_feature() to get each MSR features value.
Signed-off-by: Robert Hoo
---
include/sysemu/kvm.h | 2 ++
target/i386/cpu.c| 7 ++---
target/i386/kvm.c| 72
Note RSBA is specially treated -- no matter host support it or not, qemu
pretends it is supported.
Signed-off-by: Robert Hoo
---
target/i386/cpu.c | 27 ++-
target/i386/cpu.h | 12
2 files changed, 38 insertions(+), 1 deletion(-)
diff --git a/target/i386
Add FeatureWordType indicator in struct FeatureWordInfo.
Change feature_word_info[] accordingly.
Change existing functions that refer to feature_word_info[] accordingly.
Signed-off-by: Robert Hoo
---
target/i386/cpu.c | 172 +-
1 file changed
On Fri, 2018-08-17 at 17:52 +0200, Paolo Bonzini wrote:
> On 10/08/2018 16:06, Robert Hoo wrote:
> > x86_cpu_get_feature_words(): limit to CPUID_FEATURE_WORD only.
>
> This should also grow support for MSR feature words.
>
> My suggestion is that you add another patch after
> -Original Message-
> From: Eric Blake [mailto:ebl...@redhat.com]
> Sent: Thursday, September 6, 2018 1:41
> To: Eduardo Habkost
> Cc: Robert Hoo ; Paolo Bonzini
> ; Hu, Robert ; r...@twiddle.net;
> thomas.lenda...@amd.com; qemu-devel@nongnu.org; Liu, Jingqi
> ;
On Mon, 2018-09-10 at 14:38 -0300, Eduardo Habkost wrote:
> On Thu, Sep 06, 2018 at 06:00:29AM +, Hu, Robert wrote:
> >
> > >
> > > Yeah, since this type is used in the qom-get backdoor that evades
> > > introspection,
> > > it's
On Sun, 2018-09-02 at 19:46 +0800, Robert Hoo wrote:
Ping ... :-)
> KVM side has added the framework (kvm.git:d1d93fa90) to support MSR
> based features.
> Here is the QEMU part, including data structure changes/expanding,
> referring
> functions changes, and the imp
On Tue, 2018-07-03 at 15:38 +0200, Paolo Bonzini wrote:
> On 03/07/2018 13:07, Robert Hoo wrote:
> >> FEAT_XSAVE_COMP_LO, /* CPUID[EAX=0xd,ECX=0].EAX */
> >> FEAT_XSAVE_COMP_HI, /* CPUID[EAX=0xd,ECX=0].EDX */
> >> +FEATURE_WORDS_NUM_CPUID,
>
PCONFIG: Platform configuration, enumerated by CPUID.(EAX=07H, ECX=0):
EDX[bit18].
Signed-off-by: Robert Hoo
---
target/i386/cpu.c | 2 +-
target/i386/cpu.h | 1 +
2 files changed, 2 insertions(+), 1 deletion(-)
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index 7f787ef..9407071 100644
Support of IA32_PRED_CMD MSR already be enumerated by same CPUID bit as
SPEC_CTRL.
Signed-off-by: Robert Hoo
---
target/i386/cpu.c | 2 +-
target/i386/cpu.h | 1 +
2 files changed, 2 insertions(+), 1 deletion(-)
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index b0b87c3..7f787ef 100644
ake CPU model itself but fundamental. So split these work apart
and do it later.
https://lists.gnu.org/archive/html/qemu-devel/2018-07/msg00774.html
https://lists.gnu.org/archive/html/qemu-devel/2018-07/msg00796.html
Signed-off-by: Robert Hoo
---
tar
WBNOINVD: Write back and do not invalidate cache, enumerated by
CPUID.(EAX=8008H, ECX=0):EBX[bit 9].
Signed-off-by: Robert Hoo
---
target/i386/cpu.c | 2 +-
target/i386/cpu.h | 2 ++
2 files changed, 3 insertions(+), 1 deletion(-)
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index
].
https://software.intel.com/sites/default/files/managed/c5/63/336996-Speculative-Execution-Side-Channel-Mitigations.pdf
Signed-off-by: Robert Hoo
---
target/i386/cpu.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/target/i386/cpu.h b/target/i386/cpu.h
index 2c5a0d9..ae97005 100644
--- a
.
Fix some patch format error and update some trivial patch descrptions.
v2
Per Paolo's comment, remove unnecessary CPU vmstate check for
write/read only
IA32_PRED_CMD and IA32_ARCH_CAPABILITIES MSRs.
Robert Hoo (5):
i386: Add new MSR indices for IA32_PRED_CMD and IA32_ARCH_CAPABIL
Best Regards,
Robert Hoo
> -Original Message-
> From: Paolo Bonzini
> Sent: Wednesday, July 4, 2018 21:39
> To: Liu, Jingqi
> Cc: r...@twiddle.net; ehabk...@redhat.com; mtosa...@redhat.com; qemu-
> de...@nongnu.org; Wang, Wei W ; Hu, Robert
>
> Subject: R
WBNOINVD: Write back and do not invalidate cache, enumerated by
CPUID.(EAX=8008H, ECX=0):EBX[bit 9].
Signed-off-by: Robert Hoo
---
target/i386/cpu.c | 2 +-
target/i386/cpu.h | 2 ++
2 files changed, 3 insertions(+), 1 deletion(-)
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index
://software.intel.com/sites/default/files/managed/c5/63/336996-Speculative-Execution-Side-Channel-Mitigations.pdf
Signed-off-by: Robert Hoo
---
target/i386/cpu.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/target/i386/cpu.h b/target/i386/cpu.h
index 2c5a0d9..ae97005 100644
--- a/target/i386
ake CPU model itself but fundamental. So split these work apart
and do it later.
https://lists.gnu.org/archive/html/qemu-devel/2018-07/msg00774.html
https://lists.gnu.org/archive/html/qemu-devel/2018-07/msg00796.html
Signed-off-by: Robert Hoo
---
tar
PCONFIG: Platform configuration, enumerated by CPUID.(EAX=07H, ECX=0):
EDX[bit18].
Signed-off-by: Robert Hoo
---
target/i386/cpu.c | 2 +-
target/i386/cpu.h | 1 +
2 files changed, 2 insertions(+), 1 deletion(-)
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index 878b1ce..b83d0a9 100644
expression frame work from CPUID features
only to MSR bit included as well.
Fix some patch format error and update some trivial patch descrptions.
v2
Per Paolo's comment, remove unnecessary CPU vmstate check for
write/read only
IA32_PRED_CMD and IA32_ARCH_CAPABILITIES MSRs.
Robert H
Support of IA32_PRED_CMD MSR already be enumerated by same CPUID bit as
SPEC_CTRL.
At present, mark CPUID_7_0_EDX_ARCH_CAPABILITIES unmigratable, per Paolo's
comment.
Signed-off-by: Robert Hoo
---
target/i386/cpu.c | 3 ++-
target/i386/cpu.h | 1 +
2 files changed, 3 insertions(+), 1 del
On Tue, 2018-07-03 at 08:00 -0300, Eduardo Habkost wrote:
> On Tue, Jul 03, 2018 at 03:35:13PM +0800, Robert Hoo wrote:
> > On Thu, 2018-06-28 at 15:28 -0300, Eduardo Habkost wrote:
> > > On Wed, Jun 27, 2018 at 07:27:21PM +0800, Robert Hoo wrote:
> > > > Support o
On Fri, 2018-07-13 at 10:11 -0400, konrad.w...@oracle.com wrote:
> (Apologies if this comes out as HTML, using Thunderbird instead of mutt
> here)..
>
> > +uint64_t pred_cmd;
> > +uint64_t arch_capabilities;
>
> Could this be 'arch_cap' ?
>
> >
> > /* End of state preserved by
Define FeatureWordType.
Expand FeatureWordInfo to support both CPUID type feature word as well as
MSR type's.
Change feature_word_info[] accordingly.
Signed-off-by: Robert Hoo
---
target/i386/cpu.c | 133 ++
target/i386/cpu.h | 5 ++
2
x86_cpu_get_supported_feature_word().
Signed-off-by: Robert Hoo
---
include/sysemu/kvm.h | 2 ++
target/i386/kvm.c| 78
2 files changed, 80 insertions(+)
diff --git a/include/sysemu/kvm.h b/include/sysemu/kvm.h
index 0b64b8e..0cf792f 100644
--- a/include/sysemu/kvm.h
KVM side has added the framework (kvm.git:d1d93fa90) to support MSR based
features.
Here is the QEMU part, including data structure changes/expanding, referring
functions changes, and the implementations on
KVM_GET_MSR_FEATURE_INDEX_LIST and KVM_GET_MSRS system ioctl.
Robert Hoo (3):
x86
.
x86_cpu_get_supported_feature_word(): add MSR_FEATURE_WORD type support.
x86_cpu_adjust_feat_level(): assert the requested feature must be
CPUID_FEATURE_WORD type.
Signed-off-by: Robert Hoo
---
target/i386/cpu.c | 76 +--
1 file changed, 57 insertions(+), 19 deletions
x86_cpu_get_supported_feature_word().
Signed-off-by: Robert Hoo
---
include/sysemu/kvm.h | 2 ++
target/i386/kvm.c| 78
2 files changed, 80 insertions(+)
diff --git a/include/sysemu/kvm.h b/include/sysemu/kvm.h
index 0b64b8e..0cf792f 100644
--- a/include/sysemu/kvm.h
style changes to pass ./scripts/checkpatch.pl.
Robert Hoo (3):
x86: Data structure changes to support MSR based features
kvm: Add support to KVM_GET_MSR_FEATURE_INDEX_LIST and KVM_GET_MSRS
system ioctl
Change other funcitons referring to feature_word_info[]
include/sysemu
.
x86_cpu_get_supported_feature_word(): add MSR_FEATURE_WORD type support.
x86_cpu_adjust_feat_level(): assert the requested feature must be
CPUID_FEATURE_WORD type.
Signed-off-by: Robert Hoo
---
target/i386/cpu.c | 76 +--
1 file changed, 57 insertions(+), 19 deletions
Define FeatureWordType.
Expand FeatureWordInfo to support both CPUID type feature word as well as
MSR type's.
Change feature_word_info[] accordingly.
Signed-off-by: Robert Hoo
---
target/i386/cpu.c | 133 ++
target/i386/cpu.h | 5 ++
2
.
x86_cpu_get_supported_feature_word(): add MSR_FEATURE_WORD type support.
x86_cpu_adjust_feat_level(): assert the requested feature must be
CPUID_FEATURE_WORD type.
Signed-off-by: Robert Hoo
---
target/i386/cpu.c | 77 +--
1 file changed, 58 insertions(+), 19 deletions
x86_cpu_get_supported_feature_word().
Signed-off-by: Robert Hoo
---
include/sysemu/kvm.h | 2 ++
target/i386/kvm.c| 79
2 files changed, 81 insertions(+)
diff --git a/include/sysemu/kvm.h b/include/sysemu/kvm.h
index 0b64b8e..97d8d9d 100644
--- a/include/sysemu/kvm.h
mp;3 in v2 are corrupted. Re-format patches.
v2: coding style changes to pass ./scripts/checkpatch.pl.
----
Robert Hoo (3):
x86: Data structure changes to support MSR based features
kvm: Add support to KVM_GET_MSR_FEATURE_INDEX_LIST and KVM_GET_MSRS
system ioctl
Change o
Define FeatureWordType.
Expand FeatureWordInfo to support both CPUID type feature word as well as
MSR type's.
Change feature_word_info[] accordingly.
Signed-off-by: Robert Hoo
---
target/i386/cpu.c | 133 ++
target/i386/cpu.h | 5 ++
2
.
Robert Hoo (5):
i386: Add support for IA32_PRED_CMD and IA32_ARCH_CAPABILITIES MSRs
i386: Add CPUID bit and feature words for IA32_ARCH_CAPABILITIES MSR
i386: Add CPUID bit for PCONFIG
i386: Add CPUID bit for WBNOINVD
i386: Add new CPU model Icelake-{Server,Client}
target/i386/cpu.c
://software.intel.com/sites/default/files/managed/c5/63/336996-Speculative-Execution-Side-Channel-Mitigations.pdf
Signed-off-by: Robert Hoo
---
target/i386/cpu.h | 4
target/i386/kvm.c | 27 ++-
target/i386/machine.c | 40
3
Support of IA32_PRED_CMD MSR already be enumerated by same CPUID bit as
SPEC_CTRL.
Signed-off-by: Robert Hoo
---
target/i386/cpu.c | 2 +-
target/i386/cpu.h | 1 +
2 files changed, 2 insertions(+), 1 deletion(-)
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index 1e69e68..3134af4 100644
PCONFIG: Platform configuration, enumerated by CPUID.(EAX=07H, ECX=0):
EDX[bit18].
Reference:
https://software.intel.com/sites/default/files/managed/c5/15/architecture-instruction-set-extensions-programming-reference.pdf
Signed-off-by: Robert Hoo
---
target/i386/cpu.c | 2 +-
target/i386/cpu.h
WBNOINVD: Write back and do not invalidate cache, enumerated by
CPUID.(EAX=8008H, ECX=0):EBX[bit 9].
Reference:
https://software.intel.com/sites/default/files/managed/c5/15/architecture-instruction-set-extensions-programming-reference.pdf
Signed-off-by: Robert Hoo
---
target/i386/cpu.c | 2
ned-off-by: Robert Hoo
---
target/i386/cpu.c | 116 ++
1 file changed, 116 insertions(+)
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index 821b7bd..2613e1a 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -2276,6 +2276,122
On Mon, 2018-06-25 at 13:51 +0200, Paolo Bonzini wrote:
> On 25/06/2018 05:39, Robert Hoo wrote:
> > IA32_PRED_CMD MSR gives software a way to issue commands that affect the
> > state
> > of indirect branch predictors. Enumerated by CPUID.(EAX=7H,ECX=0):EDX[26].
> >
On Mon, 2018-06-25 at 14:06 +0200, Paolo Bonzini wrote:
> On 25/06/2018 05:39, Robert Hoo wrote:
> > Support of IA32_PRED_CMD MSR already be enumerated by same CPUID bit as
> > SPEC_CTRL.
> >
> > Signed-off-by: Robert Hoo
> > ---
> > target/i386/cpu.c | 2
Support of IA32_PRED_CMD MSR already be enumerated by same CPUID bit as
SPEC_CTRL.
Signed-off-by: Robert Hoo
---
target/i386/cpu.c | 2 +-
target/i386/cpu.h | 1 +
2 files changed, 2 insertions(+), 1 deletion(-)
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index e6c2f8a..953098c 100644
WBNOINVD: Write back and do not invalidate cache, enumerated by
CPUID.(EAX=8008H, ECX=0):EBX[bit 9].
Signed-off-by: Robert Hoo
---
target/i386/cpu.c | 2 +-
target/i386/cpu.h | 1 +
2 files changed, 2 insertions(+), 1 deletion(-)
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index
://software.intel.com/sites/default/files/managed/c5/63/336996-Speculative-Execution-Side-Channel-Mitigations.pdf
Signed-off-by: Robert Hoo
---
target/i386/cpu.h | 4
target/i386/kvm.c | 27 ++-
2 files changed, 30 insertions(+), 1 deletion(-)
diff --git a/target/i386
PCONFIG: Platform configuration, enumerated by CPUID.(EAX=07H, ECX=0):
EDX[bit18].
Signed-off-by: Robert Hoo
---
target/i386/cpu.c | 2 +-
target/i386/cpu.h | 1 +
2 files changed, 2 insertions(+), 1 deletion(-)
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index 953098c..c2c3cdb 100644
ned-off-by: Robert Hoo
---
target/i386/cpu.c | 116 ++
1 file changed, 116 insertions(+)
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index 92bfbbc..ff3273a 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -2382,6 +2382,122
.
Changelog:
v2
Per Paolo's comment, remove unnecessary CPU vmstate check for
write/read only
IA32_PRED_CMD and IA32_ARCH_CAPABILITIES MSRs.
Robert Hoo (5):
i386: Add support for IA32_PRED_CMD and IA32_ARCH_CAPABILITIES MSRs
i386: Add CPUID bit and feature words for IA32_ARCH_CAPABIL
On Wed, 2018-06-27 at 14:03 -0300, Eduardo Habkost wrote:
> On Wed, Jun 27, 2018 at 07:27:20PM +0800, Robert Hoo wrote:
> > IA32_PRED_CMD MSR gives software a way to issue commands that affect the
> > state
> > of indirect branch predictors. Enumerated by CPUID.
On Thu, 2018-06-28 at 15:28 -0300, Eduardo Habkost wrote:
> On Wed, Jun 27, 2018 at 07:27:21PM +0800, Robert Hoo wrote:
> > Support of IA32_PRED_CMD MSR already be enumerated by same CPUID bit as
> > SPEC_CTRL.
> >
> > Signed-off-by: Robert Hoo
>
> Based on kern
On Thu, 2018-06-28 at 16:20 +0200, Paolo Bonzini wrote:
> On 28/06/2018 11:25, Robert Hoo wrote:
> >>> +uint64_t pred_cmd;
> >>> +uint64_t arch_capabilities;
> >> What's the purpose of those CPUX86State fields, if the migration
> >> se
On Tue, 2018-07-03 at 11:06 +0200, Paolo Bonzini wrote:
> On 03/07/2018 10:48, Robert Hoo wrote:
> >>
> >> However, I suggest adding it to the FeatureWord enum, since everything
> >> that handles FeatureWord applies to this new kind of MSR as well.
> >>
On Fri, 2018-08-10 at 10:17 -0500, Eric Blake wrote:
> On 08/10/2018 09:06 AM, Robert Hoo wrote:
>
> In the subject: s/funcitons/functions/
>
> Also, it may be worth using a topic prefix (most of our commit messages
> resemble:
>
> topic: Description of patch
>
On Fri, 2018-08-17 at 00:10 -0300, Eduardo Habkost wrote:
[trim...]
> > +
> > typedef struct FeatureWordInfo {
> > -/* feature flags names are taken from "Intel Processor Identification
> > and
> > +FeatureWordType type;
> > + /* feature flags names are taken from "Intel Processor Ident
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