On Mon, Aug 6, 2012 at 7:29 PM, Peter Maydell wrote:
> On 6 August 2012 03:16, Peter A. G. Crosthwaite
> wrote:
>> Slave creation function that can be used to create an SSI slave without
>> qdev_init() being called. This give machine models a change to set
>> properties.
>
> Not convinced about
On Mon, Aug 6, 2012 at 7:38 PM, Peter Maydell wrote:
> On 6 August 2012 03:16, Peter A. G. Crosthwaite
> wrote:
>> Allow multiple qdev_init_gpio_in() calls for the one device. The first call
>> will
>> define GPIOs 0-N-1, the next GPIOs N- ... . Allows different GPIOs to be
>> handled
>> with d
On Mon, Aug 6, 2012 at 7:25 PM, Peter Maydell wrote:
> On 6 August 2012 03:16, Peter A. G. Crosthwaite
> wrote:
>> Added default CS behaviour for SSI slaves. SSI devices can set a property
>> to enable CS behaviour which will create a GPIO on the device which is the
>> CS. Tristating of the bus o
On Mon, Aug 6, 2012 at 7:50 PM, Peter Maydell wrote:
> On 6 August 2012 03:16, Peter A. G. Crosthwaite
> wrote:
>> Added SPI controller to the reference design, with two n25q128 spi-flashes
>> connected.
>>
>> Signed-off-by: Peter A. G. Crosthwaite
>> ---
>> hw/petalogix_ml605_mmu.c | 28
On Mon, 2012-08-06 at 17:42 +0100, Peter Maydell wrote:
> Fix a variety of typos in comments in target-arm files.
>
> Signed-off-by: Peter Maydell
Reviewed-by: Peter Crosthwaite
> ---
> Changes v1->v2: s/inputs values/input values/
>
> target-arm/arm-semi.c|
On Mon, Aug 6, 2012 at 7:48 PM, Peter Maydell wrote:
> On 6 August 2012 03:16, Peter A. G. Crosthwaite
> wrote:
>> Added a FIFO API that can be used to create and operate byte FIFOs.
>
> I'm not asking for actual conversions, but it would be nice to see a
> list of some devices that could in prin
>> +
>> +extern const VMStateDescription vmstate_fifo8;
>> +
>> +#define VMSTATE_FIFO8(_field, _state) { \
>> +.name = (stringify(_field)), \
>> +.size = sizeof(Fifo8), \
>> +.vmsd
>>> +sdhci_update_irq(s);
>>> +break;
>>> +}
>>> +}
>>> +}
>>
>> So I think the guest can make this loop never terminate if it sets up
>> a loop of ACT_LINK descriptors, right? I don't know how we should
>> handle this but I'm pretty sure "make qemu sit there for
On Tue, Aug 7, 2012 at 4:28 PM, Igor Mitsyanko wrote:
> On 08/07/2012 10:10 AM, Peter Crosthwaite wrote:
>>>>
>>>> +
>>>> +extern const VMStateDescription vmstate_fifo8;
>>>> +
>>>> +#define VMSTATE_FIFO8(_field, _state) {
Hi All,
We seem to be having difficulty getting a review/merge on this patch. I
have sent two series, two pings and a PULL, with only a single reply
from P. Maydell asking for other reviewers to weigh in:
- on July 17 P. Maydell wrote ---
I guess I should mention that I'm assumin
On Wed, Aug 8, 2012 at 5:22 PM, Markus Armbruster wrote:
> Peter Maydell writes:
>
>> On 7 August 2012 20:26, Markus Armbruster wrote:
>>> qemu-system-arm lm3s811evb
>>> qemu-system-arm lm3s6965evb
>>> qemu-system-arm: /work/armbru/qemu/hw/qdev.c:310:
>>> qdev_get_gpio_in: Assertion `n
Resend of pull,
Edgars review addressed.
On Fri, Aug 10, 2012 at 12:30 PM, Peter A. G. Crosthwaite
wrote:
> are available in the git repository at:
>
> git://developer.petalogix.com/public/qemu.git ..BRANCH.NOT.VERIFIED..
>
> Anthony Liguori (1):
> qom: Reimplement Interfaces
>
> Peter A
Apoligies,
bad remote, please disregard.
On Fri, Aug 10, 2012 at 12:32 PM, Peter Crosthwaite
wrote:
> Resend of pull,
>
> Edgars review addressed.
>
> On Fri, Aug 10, 2012 at 12:30 PM, Peter A. G. Crosthwaite
> wrote:
>> are available in the git re
On Mon, 2012-08-06 at 10:13 +0100, Peter Maydell wrote:
> On 6 August 2012 03:16, Peter A. G. Crosthwaite
> wrote:
> > Added VMSD stub for SSI slaves. Fields may be added to this VMSD for generic
> > SSI slave state (e.g. the CS line state).
>
> This is more me being confused about how this shoul
On Fri, Aug 10, 2012 at 7:15 PM, Andreas Färber wrote:
> Am 10.08.2012 05:16, schrieb Peter A. G. Crosthwaite:
>> From: Anthony Liguori
>>
>> The current implementation of Interfaces is poorly designed. Each interface
>> that an object implements ends up being an object that's tracked by the
>>
Ping!
Any further thoughts here?
There seem to be a few minor correction for PPM, but the sore-thumb
issue is the long/infinite ADMA. Is there an (easy) AIO based solution
to be had or do we need to do some sort of ptimer hack?
Regards,
Peter
On Tue, Aug 7, 2012 at 4:31 PM, Peter Crosthwaite
On Fri, Aug 10, 2012 at 11:42 PM, Stefan Hajnoczi wrote:
> On Fri, Aug 10, 2012 at 01:54:26PM +1000, Peter A. G. Crosthwaite wrote:
>> The sizep arg is populated with the size of the loaded device tree. Since
>> this
>> is one of those informational "please populate" type arguments it should be
>
On Mon, Aug 6, 2012 at 7:41 PM, Peter Maydell wrote:
> On 6 August 2012 03:16, Peter A. G. Crosthwaite
> wrote:
>> To be more consistent with the newer ways of error signalling. That and
>> SIGABT
>> is easier to debug with than exit(1).
>>
>> Signed-off-by: Peter A. G. Crosthwaite
>
> Reviewed
On Thu, Aug 16, 2012 at 5:17 AM, Markus Armbruster wrote:
> Cc: Peter Crosthwaite
>
> Suppress default floppy, CD-ROM and SD card drives for machines
> petalogix-ml605 and petalogix-s3adsp1800.
>
> Signed-off-by: Markus Armbruster
Reviewed-by: Peter Crosth
On Thu, Aug 16, 2012 at 5:17 AM, Markus Armbruster wrote:
> Cc: Peter Crosthwaite
>
> Suppress default floppy and CD-ROM drives. SD card was already
> suppressed.
>
> Signed-off-by: Markus Armbruster
Reviewed-by: Peter Crosthwaite
> ---
> hw/xilinx_zynq.c | 2
On Tue, Aug 14, 2012 at 10:50 PM, Anthony Liguori wrote:
> "Peter A. G. Crosthwaite" writes:
>
>> Hi All. A couple of times now ive had debug issues due to silent failure of
>> object_property_set. This function silently fails if the requested property
>> does not exist for the target object. To
On Tue, Aug 14, 2012 at 6:46 PM, Peter Maydell wrote:
> On 14 August 2012 09:27, Juan Quintela wrote:
>> "Peter A. G. Crosthwaite" wrote:
>>> Hi All. PMM raised a query on a recent series of mine (the SSI series) about
>>> handling VMSD for devices which define state at multiple levels of the QO
On Mon, Aug 20, 2012 at 9:02 PM, Andreas Färber wrote:
> Am 20.08.2012 04:18, schrieb Peter Crosthwaite:
>> [...] Here's my code as it stands:
>>
>> Error *errp = NULL;
>> object_property_set_link(OBJECT(dev), OBJECT(cpus[0]), "cpu0", &errp);
>
- I guess there is same reasy why you want to split the device state,
it could be on the other series where I haven't read it though.
>>
>> So this is exactly what I have done in the SSI. Correct me if I am
>> wrong but it is the same setup as PCI where the VMSTATE_PCI_DEVICE
>> (V
Hi Andreas,
Thanks for that, I will rename the switch to -kernel-dtb.
You are correct that 7/7 should have the usage in it, that patch was
incorrectly generated, I will regenerate and resend the series tomorrow for
another review cycle.
Regards.
Peter
On Tue, Jan 24, 2012 at 5:22 PM, Andreas F
Hi All,
So on the topic of these command line arguments for initrd, dtb and
friends, another related issue we have encountered (and have hacked around
in our tree) is not being able to relocate the initrd or kernel. Currently
these memory locations are hardcoded in arm_boot.c:
#define KERNEL_ARGS
Hi Grant,
The patch series for dts driven machine creation we (myself and Edgar) use
that you are referring to was rejected a few months ago on the grounds that
it conflicted with QOM:
http://lists.gnu.org/archive/html/qemu-devel/2011-08/msg02953.html
I am maintaining it our of tree, although I
On Mon, Jan 30, 2012 at 6:42 AM, Edgar E. Iglesias wrote:
> On Sat, Jan 28, 2012 at 11:48:37AM -0700, Grant Likely wrote:
> > On Fri, Jan 27, 2012 at 10:34:01PM +, Paul Brook wrote:
> > > > If compiled with CONFIG_FDT, allow user to specify a device tree
> file using
> > > > the -dtb argument
2012/2/7 Paul Brook
> > Implemented cadence Triple Timer Counter (TCC)
>
> It looks like you're implementing a periodic timer as sequence of chained
> oneshot timers. This is a bad idea. In qemu interrupt latency may be
> high,
> so you're likely to suffer from significant time skew.
>
> Ok, I
Hi Peter,
Anthony suggested to us the Idea of setting up bootloaders as devices in
order to solve this command line argument problem. I have posted a patch to
the mailing list ([RFC PATCH] arm boot: added QOM device definition) which
is my first attempt at this for arm_boot, i.e. arm_boot.c is now
2012/2/7 Paul Brook
> > This is an RFC for a suite of Device models and a machine model for the
> > Xilinx Zynq-7000 Extensible Processing Platform:
> >
> > http://www.xilinx.com/products/silicon-devices/epp/zynq-7000/index.htm
>
> I don't see any documentation on that page. Are technical docs av
2012/2/8 Paul Brook
> > diff --git a/hw/versatilepb.c b/hw/versatilepb.c
> > index 6e28e78..e42d845 100644
> > --- a/hw/versatilepb.c
> > +++ b/hw/versatilepb.c
> > @@ -313,12 +313,14 @@ static void versatile_init(ram_addr_t ram_size,
> > /* 0x101f3000 UART2. */
> > /* 0x101f4000 SSPI
2012/2/8 Paul Brook
> > > > Implemented cadence Triple Timer Counter (TCC)
> > >
> > > It looks like you're implementing a periodic timer as sequence of
> chained
> > > oneshot timers. This is a bad idea. In qemu interrupt latency may be
> > > high,
> > > so you're likely to suffer from signifi
2012/2/8 Paul Brook
> > > > + arm_load_kernel(env, &versatile_binfo);
> > > > + }
> > > >
> > > > }
> > >
> > > This should be using the new object you just added.
> >
> > Yes I agree. There is another question tho that if this approach is to be
> > considered, should this call t
2012/2/8 Paul Brook
> > > I suspect we want to replace the arm_load_kernel call with an
> > > arm_linux_loader device with appropriate properties.
> >
> > Ok, so does this mean the machine model would still explicitly
> instantiate
> > the bootloader device?
>
> Yes. Bootloaders inherently have
2012/2/8 Paul Brook
> > > - When are interrupts raised. You mention a user specified match
> value.
> > > Do we also get an interrupt on wraparound?
> >
> > Yes, an interrupts occur on wrap around of the 16 bit timer value. There
> > are three match registers which correspond to three more
> >
On Wed, Feb 8, 2012 at 10:41 PM, Alexander Graf wrote:
>
> On 08.02.2012, at 13:27, Paul Brook wrote:
>
> >> 2012/2/8 Paul Brook
> >>
> > I suspect we want to replace the arm_load_kernel call with an
> > arm_linux_loader device with appropriate properties.
>
> Ok, so does this
On Wed, Feb 8, 2012 at 11:10 PM, Alexander Graf wrote:
>
> On 08.02.2012, at 14:04, Peter Crosthwaite wrote:
>
>
>
> On Wed, Feb 8, 2012 at 10:41 PM, Alexander Graf wrote:
>
>>
>> On 08.02.2012, at 13:27, Paul Brook wrote:
>>
>> >> 2012/
On Wed, Feb 8, 2012 at 11:35 PM, Alexander Graf wrote:
>
> On 08.02.2012, at 14:30, Peter Crosthwaite wrote:
>
>
>
> On Wed, Feb 8, 2012 at 11:10 PM, Alexander Graf wrote:
>
>>
>> On 08.02.2012, at 14:04, Peter Crosthwaite wrote:
>>
>>
>>
2012/2/9 Paul Brook
> > So if we consider this bootloader a device and its -dtb argument a
> property
> > of that device, then what you are implying is that every device property
> of
> > every device in a machine must be managed by the machine model? Isn't the
> > dynamic machine model work that
So here are some of the problems im trying to solve with the bootloader:
Smp bootstrap secondary CPUs while loading an elf (currently elfs will be
assumed to be not kernels).
Change the kernel, initrd and dtb load address on the command line.
Use my own SMP secondary bootloop.
My intention with t
2012/2/9 Paul Brook
> > So here are some of the problems im trying to solve with the bootloader:
> >
> > Smp bootstrap secondary CPUs while loading an elf (currently elfs will be
> > assumed to be not kernels).
> > Change the kernel, initrd and dtb load address on the command line.
> > Use my own
Alrighty,
So it seems like the bootloader as a device idea has some support, just
need to work out a few implementaiton details. It seems the consensus is
that machine models will instantiate the device. The latest idea is the
machine model will pass some of core props to the bootloader while othe
On Thu, Feb 9, 2012 at 11:22 PM, Andreas Färber wrote:
> Am 08.02.2012 08:55, schrieb Peter A. G. Crosthwaite:
> > From: "Peter A. G. Crosthwaite"
> >
> > Create a QOM device for bootstrapping linux on arm. Wraps the existing
> > arm_boot code and calls arm_load_kernel() at device init. Allows b
2012/2/12 Paul Brook
> > +static void cadence_timer_sync(CadenceTimerState *s)
> > +{
> >...
> > +r = (int64_t)cadence_timer_get_steps(s, s->cpu_time - old_time);
> > +x = (int64_t)s->reg_value + ((s->reg_count & COUNTER_CTRL_DEC) ? -r
> :
> > r); +
> > +for (i = 0; i < 3; ++i) {
> >
the C flag which should happen before the update.
Fixed the ordering of the two, the old carry is read by "r13,RRX" before being
updated.
Signed-off-by: Peter Crosthwaite
Reported-by: Vinesh Peringat
---
target-arm/translate.c |2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
(see the FIXME:s) at the moment but im pushing
for this now as the more conterversial QOM-entangled aspects of this device
model are encapsulated by this series. The device does also fully work for
Linux.
Edgar E. Iglesias (1):
nand: Reset addressing after READSTATUS.
Peter Crosthwaite (6
This field is completely unused. The base address should also be abstracted
away from the device anyway. Removed.
Signed-off-by: Peter Crosthwaite
---
hw/pflash_cfi01.c |2 --
hw/pflash_cfi02.c |4 +---
2 files changed, 1 insertions(+), 5 deletions(-)
diff --git a/hw/pflash_cfi01.c b
This field is completely unused.
Signed-off-by: Peter Crosthwaite
---
hw/pflash_cfi01.c |2 --
1 files changed, 0 insertions(+), 2 deletions(-)
diff --git a/hw/pflash_cfi01.c b/hw/pflash_cfi01.c
index 4f3f5f0..ebc8a57 100644
--- a/hw/pflash_cfi01.c
+++ b/hw/pflash_cfi01.c
@@ -62,7 +62,6
morph into something else with Anthony sysbus purge
so its intended to be a bridging patch until those refactorings go live.
Signed-off-by: Peter Crosthwaite
---
hw/sysbus.c | 11 ---
hw/sysbus.h |2 ++
2 files changed, 10 insertions(+), 3 deletions(-)
diff --git a/hw/sysbus.c b
Initial device model for the pl35x series of memory controllers. The SRAM
interface is just implemented as a passthrough using memory regions. NAND
interfaces are modelled.
Signed-off-by: Peter Crosthwaite
---
default-configs/arm-softmmu.mak |1 +
hw/Makefile.objs|1
Add the pl353 memory controller with both NAND and parallel flashes
attached.
Signed-off-by: Peter Crosthwaite
---
hw/xilinx_zynq.c | 49 +
1 files changed, 41 insertions(+), 8 deletions(-)
diff --git a/hw/xilinx_zynq.c b/hw/xilinx_zynq.c
From: Edgar E. Iglesias
Signed-off-by: Edgar E. Iglesias
---
hw/nand.c |6 ++
1 files changed, 6 insertions(+), 0 deletions(-)
diff --git a/hw/nand.c b/hw/nand.c
index 01f3ada..f931d0c 100644
--- a/hw/nand.c
+++ b/hw/nand.c
@@ -478,6 +478,12 @@ void nand_setio(DeviceState *dev, uint32
Hi All,
Thanks for the responses. Ill look into further in the near future,
probably starting the the Linker based approaches.
Regards,
Peter
QOMified the pflash_cfi0x so machine models can connect them up in custom ways.
Kept the pflash_cfi0x_register functions as is. They can still be used to
create a flash straight onto system memory.
Signed-off-by: Peter Crosthwaite
---
hw/pflash_cfi01.c | 142
Support for the Quad SPI flash controller in Xilinx Zynq.
Peter Crosthwaite (3):
m25p80: Support for Quad SPI
xilinx_spips: Generalised to model QSPI
xilinx_zynq: added QSPI controller
hw/m25p80.c | 61 +++-
hw/xilinx_spips.c | 289
: Peter Crosthwaite
---
hw/m25p80.c | 61 +++---
1 files changed, 57 insertions(+), 4 deletions(-)
diff --git a/hw/m25p80.c b/hw/m25p80.c
index 9a56de8..3895e73 100644
--- a/hw/m25p80.c
+++ b/hw/m25p80.c
@@ -72,6 +72,10 @@ typedef struct
Added the QSPI controller to the Zynq. 4 SPI devices are attached to allow
modelling of the different geometries. E.G. Dual parallel and dual stacked
mode can both be tested with this one arrangement.
Signed-off-by: Peter Crosthwaite
---
hw/xilinx_zynq.c | 40
: Peter Crosthwaite
---
hw/xilinx_spips.c | 289 ++--
1 files changed, 255 insertions(+), 34 deletions(-)
diff --git a/hw/xilinx_spips.c b/hw/xilinx_spips.c
index f64a782..538f091 100644
--- a/hw/xilinx_spips.c
+++ b/hw/xilinx_spips.c
@@ -28,6 +28,7
On Fri, Oct 19, 2012 at 6:06 PM, Peter Maydell wrote:
> On 19 October 2012 07:40, Peter Crosthwaite
> wrote:
>> Add a variant to sysbus_mmio_map that allow specifying a target memory
>> region.
>> The requested device memory region is mapped within the argument tar
Add more helpful debug information to the cadence UART.
Signed-off-by: Peter Crosthwaite
---
hw/cadence_uart.c | 11 +++
1 files changed, 7 insertions(+), 4 deletions(-)
diff --git a/hw/cadence_uart.c b/hw/cadence_uart.c
index f8afc4e..483a316 100644
--- a/hw/cadence_uart.c
+++ b/hw
On Fri, Oct 19, 2012 at 8:32 PM, Peter Maydell wrote:
> On 19 October 2012 07:40, Peter Crosthwaite
> wrote:
>> Add the pl353 memory controller with both NAND and parallel flashes
>> attached.
>>
>> Signed-off-by: Peter Crosthwaite
>>
On Fri, Oct 19, 2012 at 8:24 PM, Peter Maydell wrote:
> On 19 October 2012 07:40, Peter Crosthwaite
> wrote:
>> QOMified the pflash_cfi0x so machine models can connect them up in custom
>> ways.
>>
>> Kept the pflash_cfi0x_register functions as is. They can stil
On Fri, Oct 19, 2012 at 10:18 PM, Edgar E. Iglesias
wrote:
> On Fri, Oct 19, 2012 at 12:59:49PM +0100, Peter Maydell wrote:
>> On 19 October 2012 07:40, Peter Crosthwaite
>> wrote:
>> > From: Edgar E. Iglesias
>> >
>> > Signed-off-by: Edgar E. Igle
pflash when debug was turned on (P6)
Removed NAND READ_STATUS address reset patch (fomerly P6)
Peter Crosthwaite (6):
pflash_cfi0x: remove unused base field
pflash_cfi01: remove unused total_len field
pflash_cfi0x: QOMified
hw: Model of Primecell pl35x mem controller
xilinx_zynq: add pl353
This field is completely unused. The base address should also be abstracted
away from the device anyway. Removed.
Signed-off-by: Peter Crosthwaite
Reviewed-by: Peter Maydell
---
hw/pflash_cfi01.c |2 --
hw/pflash_cfi02.c |4 +---
2 files changed, 1 insertions(+), 5 deletions(-)
diff
QOMified the pflash_cfi0x so machine models can connect them up in custom ways.
Kept the pflash_cfi0x_register functions as is. They can still be used to
create a flash straight onto system memory.
Signed-off-by: Peter Crosthwaite
---
changed from v1:
Removed union usages (PMM review)
Changed
Add the pl353 memory controller with both NAND and parallel flashes
attached.
Signed-off-by: Peter Crosthwaite
---
changed from v1:
fixed property names (see patch 3)
hw/xilinx_zynq.c | 50 ++
1 files changed, 42 insertions(+), 8 deletions
This DPRINTF was throwing a warning due to a missing cast.
Signed-off-by: Peter Crosthwaite
---
hw/pflash_cfi01.c |3 ++-
1 files changed, 2 insertions(+), 1 deletions(-)
diff --git a/hw/pflash_cfi01.c b/hw/pflash_cfi01.c
index 6164a97..90c111d 100644
--- a/hw/pflash_cfi01.c
+++ b/hw
This field is completely unused.
Signed-off-by: Peter Crosthwaite
Reviewed-by: Peter Maydell
---
hw/pflash_cfi01.c |2 --
1 files changed, 0 insertions(+), 2 deletions(-)
diff --git a/hw/pflash_cfi01.c b/hw/pflash_cfi01.c
index 4f3f5f0..ebc8a57 100644
--- a/hw/pflash_cfi01.c
+++ b/hw
Initial device model for the pl35x series of memory controllers. The SRAM
interface is just implemented as a passthrough using memory regions. NAND
interfaces are modelled.
Signed-off-by: Peter Crosthwaite
---
changed since v1:
use sysbus_mmio_get_region() for SRAM mappings (PMM Review)
fixed
On Tue, Oct 23, 2012 at 2:12 AM, Peter Maydell wrote:
> On 22 October 2012 08:19, Peter Crosthwaite
> wrote:
>> Initial device model for the pl35x series of memory controllers. The SRAM
>> interface is just implemented as a passthrough using memory regions. NAND
>>
On Tue, Oct 23, 2012 at 12:20 AM, Josh Cartwright
wrote:
> Change the cadence_uart such that tx/rx is enabled on reset. Assuming
> both are enabled makes debugging early Linux kernel bootup a little bit
> easier.
>
> Signed-off-by: Josh Cartwright
> ---
>
> I've used this patch mostly for my own
Just put RAM regions in the unimplemented spaces in the MMIO region. These
regions have undefined behaviour, but this at least stops QEMU from segfaulting
when the guest bangs on these registers (and sucessfully fakes reading and
writing the registers with no side effects).
Signed-off-by: Peter
A few debug messages in EHCI must have missed out on updates during incremental
developments. Fixed.
Signed-off-by: Peter Crosthwaite
---
hw/usb/hcd-ehci.c | 21 ++---
1 files changed, 10 insertions(+), 11 deletions(-)
diff --git a/hw/usb/hcd-ehci.c b/hw/usb/hcd-ehci.c
index
Add QOM device definition for sysbus attached EHCI.
Signed-off-by: Peter Crosthwaite
---
hw/usb/hcd-ehci.c | 53 -
1 files changed, 52 insertions(+), 1 deletions(-)
diff --git a/hw/usb/hcd-ehci.c b/hw/usb/hcd-ehci.c
index 862564c..17482f7
Pull the DMAContext for the PCI DMA out at device init time and put it into
the device state. Use dma_memory_read/write() instead of pci specific versions.
Signed-off-by: Peter Crosthwaite
---
hw/usb/hcd-ehci.c | 13 -
1 files changed, 8 insertions(+), 5 deletions(-)
diff --git
Guard against re-definition of EHCI_DEBUG. Allows for turning on of debug info
from configure (using --qemu-extra-cflags="-DEHCI_DEBUG=1") rather than source
code hacking.
Signed-off-by: Peter Crosthwaite
---
hw/usb/hcd-ehci.c |2 ++
1 files changed, 2 insertions(+), 0 deletion
Add the two usb controllers in Zynq.
Signed-off-by: Peter Crosthwaite
---
hw/xilinx_zynq.c | 16
1 files changed, 16 insertions(+), 0 deletions(-)
diff --git a/hw/xilinx_zynq.c b/hw/xilinx_zynq.c
index c55dafb..ed6934f 100644
--- a/hw/xilinx_zynq.c
+++ b/hw/xilinx_zynq.c
Seperate the PCI stuff from the EHCI components. Extracted the PCIDevice
out into a new wrapper struct to make EHCIState non-PCI-specific. Seperated
tho non PCI init component out into a seperate "common" init function.
Signed-off-by: Peter Crosthwaite
---
hw/usb/hcd-ehc
The capabilities register and operational register offsets can vary from one
EHCI implementation to the next. Parameterise accordingly.
Signed-off-by: Peter Crosthwaite
---
hw/usb/hcd-ehci.c | 68 -
1 files changed, 36 insertions(+), 32
Debian (dd of=/dev/sdx ...) to get some test
coverage outside of Zynq. More testing welcome.
Few other bits and pieces of cleanup in there too, around the EHCI_DEBUG
printfery.
Peter Crosthwaite (8):
usb/ehci: parameterise the register region offsets
usb/ehci: Abstract away PCI DMA API
usb
icular, use it in the sysbus-ohci device, which fixes a
> segfault when attempting to use that device.
>
> Signed-off-by: Peter Maydell
Reviewed-by: Peter Crosthwaite
> ---
> As suggested by Avi. I could have split this patch into one defining
> the new global and one actually u
On Thu, Oct 25, 2012 at 10:10 PM, Gerd Hoffmann wrote:
>> typedef struct EHCIItfState {
>> -PCIDevice pcidev;
>> +/* FIXME: Figure out a better way to share one Property[] array between
>> two
>> + * QOM types with different parents
>> + */
>> +union {
>> +PCIDevice p
On Thu, Oct 25, 2012 at 10:08 PM, Gerd Hoffmann wrote:
>> +typedef struct EHCIItfState {
>> +PCIDevice pcidev;
>> +struct EHCIState ehci;
>> +} EHCIItfState;
>
> EHCIPCIState ?
>
>> static const VMStateDescription vmstate_ehci = {
>> .name= "ehci",
>> -.version_id = 2,
>
On Thu, Oct 25, 2012 at 10:16 PM, Peter Maydell
wrote:
> On 25 October 2012 13:12, Gerd Hoffmann wrote:
>>> +static inline void zynq_init_usb(uint32_t base_addr, qemu_irq irq)
>>> +{
>>> +DeviceState *dev = qdev_create(NULL, "ehci-sysbus");
>>
>> I'd suggest to have a "ehci-sysbus-zynq" devic
On Thu, Oct 25, 2012 at 10:19 PM, Gerd Hoffmann wrote:
> On 10/25/12 11:47, Peter Crosthwaite wrote:
>> Just put RAM regions in the unimplemented spaces in the MMIO region. These
>> regions have undefined behaviour, but this at least stops QEMU from
>> segfaulting
>&
On Thu, Oct 25, 2012 at 10:57 PM, Gerd Hoffmann wrote:
> Hi,
>
>>> ... then you don't need to fiddle with the versions as the vmstate wire
>>> format doesn't change then.
>>>
>>
>> Does that work considering you have turned one layer of VMSD into two?
>> Can it equivocate machines saved with the
On Thu, Oct 25, 2012 at 11:14 PM, Gerd Hoffmann wrote:
> On 10/25/12 14:56, Peter Crosthwaite wrote:
>> On Thu, Oct 25, 2012 at 10:16 PM, Peter Maydell
>> wrote:
>>> On 25 October 2012 13:12, Gerd Hoffmann wrote:
>>>>> +static inline void zynq_in
On Thu, Oct 25, 2012 at 11:50 PM, Peter Maydell
wrote:
> On 25 October 2012 14:41, Avi Kivity wrote:
>> On 10/25/2012 03:28 PM, Peter Maydell wrote:
>>> On 25 October 2012 14:21, Avi Kivity wrote:
You could easily have the top-level container have ->ops that generate
an exception.
>>>
Copying patch inline to make some comments on it
diff --git a/hw/usb/hcd-uhci.c b/hw/usb/hcd-uhci.c
index b6b972f..64442a4 100644
--- a/hw/usb/hcd-uhci.c
+++ b/hw/usb/hcd-uhci.c
@@ -88,6 +88,13 @@ enum {
typedef struct UHCIState UHCIState;
typedef struct UHCIAsync UHCIAsync;
typedef struct UHCI
On Fri, Oct 26, 2012 at 9:54 AM, Peter Crosthwaite
wrote:
> Copying patch inline to make some comments on it
>
> diff --git a/hw/usb/hcd-uhci.c b/hw/usb/hcd-uhci.c
> index b6b972f..64442a4 100644
> --- a/hw/usb/hcd-uhci.c
> +++ b/hw/usb/hcd-uhci.c
> @@ -88,6 +88,13 @@ enu
On Fri, Oct 26, 2012 at 10:48 AM, David Gibson
wrote:
> On Thu, Oct 25, 2012 at 08:33:13PM +1000, Peter Crosthwaite wrote:
>> On Oct 24, 2012 3:27 AM, "Peter Maydell" wrote:
>> >
>> > Define a new global dma_context_memory which is a DMACon
see individual patch change logs)
Peter Crosthwaite (10):
usb/ehci: Use class_data to init PCI variations
usb/ehci: parameterise the register region offsets
usb/ehci: Abstract away PCI DMA API
usb/ehci: seperate out PCIisms
usb/ehci: Add Sysbus Infrastructure
usb/ehci: Add Xilinx ps7 USB
when attempting to use that device.
Signed-off-by: Peter Maydell
Reviewed-by: Peter Crosthwaite
---
dma.h |5 +
exec.c|5 +
hw/usb/hcd-ohci.c |2 +-
3 files changed, 11 insertions(+), 1 deletions(-)
diff --git a/dma.h b/dma.h
index 91ccdb5..eedf878
Definition of the USB controller implemented in Zynq.
Signed-off-by: Peter Crosthwaite
---
hw/usb/hcd-ehci.c | 10 ++
1 files changed, 10 insertions(+), 0 deletions(-)
diff --git a/hw/usb/hcd-ehci.c b/hw/usb/hcd-ehci.c
index 50a85d5..443038b 100644
--- a/hw/usb/hcd-ehci.c
+++ b/hw
Guard against re-definition of EHCI_DEBUG. Allows for turning on of debug info
from configure (using --qemu-extra-cflags="-DEHCI_DEBUG=1") rather than source
code hacking.
Signed-off-by: Peter Crosthwaite
---
hw/usb/hcd-ehci.c |2 ++
1 files changed, 2 insertions(+), 0 deletion
Just put RAM regions in the unimplemented spaces in the MMIO region. These
regions have undefined behaviour, but this at least stops QEMU from segfaulting
when the guest bangs on these registers (and sucessfully fakes reading and
writing the registers with no side effects).
Signed-off-by: Peter
A few debug messages in EHCI must have missed out on updates during incremental
developments. Fixed.
Signed-off-by: Peter Crosthwaite
---
hw/usb/hcd-ehci.c | 21 ++---
1 files changed, 10 insertions(+), 11 deletions(-)
diff --git a/hw/usb/hcd-ehci.c b/hw/usb/hcd-ehci.c
index
Pull the DMAContext for the PCI DMA out at device init time and put it into
the device state. Use dma_memory_read/write() instead of pci specific versions.
Signed-off-by: Peter Crosthwaite
---
hw/usb/hcd-ehci.c | 13 -
1 files changed, 8 insertions(+), 5 deletions(-)
diff --git
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