On Mon, 15 Jan 2024 08:32:59 PST (-0800), stefa...@gmail.com wrote:
Dear QEMU and KVM communities,
QEMU will apply for the Google Summer of Code and Outreachy internship
programs again this year. Regular contributors can submit project
ideas that they'd like to mentor by replying to this email be
On Tue, 30 Jan 2024 12:28:27 PST (-0800), stefa...@gmail.com wrote:
On Tue, 30 Jan 2024 at 14:40, Palmer Dabbelt wrote:
On Mon, 15 Jan 2024 08:32:59 PST (-0800), stefa...@gmail.com wrote:
> Dear QEMU and KVM communities,
> QEMU will apply for the Google Summer of Code and Outreachy inte
On Tue, 30 Jan 2024 17:26:11 PST (-0800), alistai...@gmail.com wrote:
On Wed, Jan 31, 2024 at 10:30 AM Palmer Dabbelt wrote:
On Tue, 30 Jan 2024 12:28:27 PST (-0800), stefa...@gmail.com wrote:
> On Tue, 30 Jan 2024 at 14:40, Palmer Dabbelt wrote:
>>
>> On Mon, 15 Jan 2024 08:3
On Wed, 31 Jan 2024 06:39:25 PST (-0800), stefa...@gmail.com wrote:
On Tue, 30 Jan 2024 at 14:40, Palmer Dabbelt wrote:
On Mon, 15 Jan 2024 08:32:59 PST (-0800), stefa...@gmail.com wrote:
I'm not 100% sure this is a sane GSoC idea, as it's a bit open ended and
might have some tr
s that's how
the ISA handles open source implementations).
Link: https://github.com/riscv/riscv-isa-manual/pull/1213
Signed-off-by: Palmer Dabbelt
---
target/riscv/cpu.c | 16
target/riscv/cpu_vendorid.h | 3 +++
2 files changed, 19 insertions(+)
diff --git a/target/r
On Thu, 01 Feb 2024 09:39:22 PST (-0800), alex.ben...@linaro.org wrote:
Palmer Dabbelt writes:
On Tue, 30 Jan 2024 12:28:27 PST (-0800), stefa...@gmail.com wrote:
On Tue, 30 Jan 2024 at 14:40, Palmer Dabbelt wrote:
On Mon, 15 Jan 2024 08:32:59 PST (-0800), stefa...@gmail.com wrote:
> D
On Thu, 01 Feb 2024 10:57:00 PST (-0800), alex.ben...@linaro.org wrote:
Palmer Dabbelt writes:
On Thu, 01 Feb 2024 09:39:22 PST (-0800), alex.ben...@linaro.org wrote:
Palmer Dabbelt writes:
On Tue, 30 Jan 2024 12:28:27 PST (-0800), stefa...@gmail.com wrote:
On Tue, 30 Jan 2024 at 14:40
On Thu, 25 Apr 2019 10:32:43 PDT (-0700), richard.hender...@linaro.org wrote:
On 4/25/19 10:26 AM, Richard Henderson wrote:
{
+ illegal 011 0 - 0 01 # c.addi16sp, RES nzimm=0
addi011 . 00010 . 01 @c_addi16sp
lui 011 . . . 01 @c_lu
On Thu, 25 Apr 2019 10:26:35 PDT (-0700), richard.hender...@linaro.org wrote:
---
target/riscv/translate.c | 13 ++---
1 file changed, 10 insertions(+), 3 deletions(-)
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index d1f599a92d..009c146e8f 100644
--- a/target/riscv
On Mon, 06 May 2019 08:52:43 PDT (-0700), finte...@gmail.com wrote:
According to the spec, "All bits besides SSIP, USIP, and UEIP in the sip
register are read-only." Further, if an interrupt is not delegated to mode
x,
then "the corresponding bits in xip [...] should appear to be hardwired to
zer
, ret_value, new_value,
+ write_mask & env->mideleg & sip_writable_mask);
+*ret_value &= env->mideleg;
+return ret;
}
/* Supervisor Protection and Translation */
Reviewed-by: Palmer Dabbelt
Thanks!
On Wed, 08 May 2019 10:38:35 PDT (-0700), jonat...@fintelia.io wrote:
There is an analogous change for ARM here:
https://patchwork.kernel.org/patch/10649857
Signed-off-by: Jonathan Behrens
---
target/riscv/csr.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/target/risc
get_ipc_perm {
abi_int __key; /* Key. */
--
2.17.2
Reviewed-by: Palmer Dabbelt
I'm assuming this is going in through someone else's tree, so I'm not going to
pick it up into mine.
On Thu, 06 Jun 2019 16:22:47 PDT (-0700), alistai...@gmail.com wrote:
Hello,
As a test of the waters, how would the QEMU community feel about
including the RISC-V OpenSBI project as a ROM submodule?
The idea would be to have OpenSBI (similar to ATF for ARM and a BIOS
for x86) included by defaul
On Thu, 06 Jun 2019 19:50:57 PDT (-0700), richard.hender...@linaro.org wrote:
Also, unless I'm misunderstanding something our implementation of LR/SC is
pretty broken. We're just using a CAS to check if the value changed, which
suffers from the ABA problem that LR/SC is there to fix in the f
On Fri, 17 May 2019 15:11:01 PDT (-0700), Alistair Francis wrote:
From: Michael Clark
Due to the design of the disassembler, the immediate is not
known during decoding of the opcode; so to handle compressed
encodings with reserved immediate values (non-zero), we need
to add an additional check
On Fri, 17 May 2019 15:11:04 PDT (-0700), Alistair Francis wrote:
From: Michael Clark
The constraint for `rdinstreth` was comparing the csr number to 0xc80,
which is `cycleh` instead. Fix this.
Author: Wladimir J. van der Laan
I'm not sure what this tag is supposed to mean. If this is the
}
+
+env->badaddr = addr;
+riscv_raise_exception(&cpu->env, cs->exception_index, GETPC());
+}
+
void riscv_cpu_do_unaligned_access(CPUState *cs, vaddr addr,
MMUAccessType access_type, int mmu_idx,
uintptr_t retaddr)
Reviewed-by: Palmer Dabbelt
On Fri, 17 May 2019 15:10:56 PDT (-0700), Alistair Francis wrote:
This should be the last series bringing the patches from the RISC-V fork
into mainline QEMU.
Dayeol Lee (1):
target/riscv: Fix PMP range boundary address bug
Michael Clark (3):
disas/riscv: Disassemble reserved compressed enc
On Tue, 28 May 2019 11:30:20 PDT (-0700), jonat...@fintelia.io wrote:
Currently mcounteren.TM acts as though it is hardwired to zero, even though
QEMU allows it to be set. This change resolves the issue by allowing reads to
the time and timeh control registers when running in a privileged mode
On Thu, 30 May 2019 03:57:12 PDT (-0700), Peter Maydell wrote:
On Sun, 26 May 2019 at 02:10, Palmer Dabbelt wrote:
From: Fabien Chouteau
QEMU model of the GPIO device on the SiFive E300 series SOCs.
The pins are not used by a board definition yet, however this
implementation can already be
ch in SiFiveESoCState, so instead we just include them within
the struct.
Thanks to Peter for pointing out the bug and suggesting the fix!
Fixes: 30efbf330a45 ("SiFive RISC-V GPIO Device")
Signed-off-by: Palmer Dabbelt
---
hw/riscv/sifive_e.c | 12 +---
include/hw/riscv/
On Fri, 14 Jun 2019 05:25:50 PDT (-0700), phi...@redhat.com wrote:
On 6/14/19 2:08 PM, Palmer Dabbelt wrote:
Coverity pointed out a memory leak in riscv_sifive_e_soc_realize(),
where a pair of recently added MemoryRegion instances would not be freed
if there were errors elsewhere in the
On Mon, 11 Mar 2019 06:52:33 PDT (-0700), pbonz...@redhat.com wrote:
On 11/03/19 13:46, Thomas Huth wrote:
On 11/03/2019 10.12, David Abdurachmanov wrote:
Re-enable PCI_DEVICES for RISC-V.
The patch is based on other /Kconfig.
Signed-off-by: David Abdurachmanov
Fixes: 82a230d5a303 ("riscv-sof
From: Bastian Koppelmann
Reviewed-by: Richard Henderson
Signed-off-by: Bastian Koppelmann
Signed-off-by: Peer Adelt
Signed-off-by: Palmer Dabbelt
---
target/riscv/insn_trans/trans_rvi.inc.c | 93 +
target/riscv/translate.c| 59 +---
2
From: Bastian Koppelmann
with all 16 bit insns moved to decodetree no path is falling back to
gen_system(), so we can remove it.
Reviewed-by: Richard Henderson
Signed-off-by: Bastian Koppelmann
Signed-off-by: Peer Adelt
Signed-off-by: Palmer Dabbelt
---
target/riscv/translate.c | 34
From: Bastian Koppelmann
With decodetree we don't need to convert RISC-V opcodes into to MemOps
as the old gen_load() did.
Reviewed-by: Richard Henderson
Signed-off-by: Bastian Koppelmann
Signed-off-by: Peer Adelt
Signed-off-by: Palmer Dabbelt
---
target/riscv/insn_trans/trans_rvi.
From: Bastian Koppelmann
decodetree handles all instructions now so the fallback is not necessary
anymore.
Reviewed-by: Richard Henderson
Signed-off-by: Bastian Koppelmann
Signed-off-by: Peer Adelt
Signed-off-by: Palmer Dabbelt
---
target/riscv/translate.c | 21 +
1
From: Bastian Koppelmann
Reviewed-by: Richard Henderson
Signed-off-by: Bastian Koppelmann
Signed-off-by: Palmer Dabbelt
---
target/riscv/insn_trans/trans_rvi.inc.c | 18 +-
target/riscv/insn_trans/trans_rvm.inc.c | 14 +++---
target/riscv/translate.c
From: Bastian Koppelmann
Reviewed-by: Richard Henderson
Signed-off-by: Bastian Koppelmann
Signed-off-by: Peer Adelt
Signed-off-by: Palmer Dabbelt
---
target/riscv/insn_trans/trans_rvm.inc.c | 55 ++--
target/riscv/translate.c| 320 ++--
2 files changed
From: Bastian Koppelmann
Reviewed-by: Richard Henderson
Signed-off-by: Bastian Koppelmann
Signed-off-by: Peer Adelt
Signed-off-by: Palmer Dabbelt
---
target/riscv/insn16.decode | 31
target/riscv/insn_trans/trans_rvc.inc.c | 101
target/riscv
Signed-off-by: Bastian Koppelmann
Signed-off-by: Peer Adelt
Signed-off-by: Palmer Dabbelt
---
target/riscv/insn32.decode | 3 +-
target/riscv/insn_trans/trans_rvi.inc.c | 21 +
target/riscv/translate.c| 40 +++--
3 files changed, 34
From: Bastian Koppelmann
Acked-by: Alistair Francis
Reviewed-by: Richard Henderson
Signed-off-by: Bastian Koppelmann
Signed-off-by: Peer Adelt
Signed-off-by: Palmer Dabbelt
---
target/riscv/insn32-64.decode | 6 +++
target/riscv/insn_trans/trans_rvf.inc.c | 60
From: Bastian Koppelmann
gen_arith_imm() does a lot of decoding manually, which was hard to read
in case of the shift instructions and is not necessary anymore with
decodetree.
Reviewed-by: Richard Henderson
Signed-off-by: Bastian Koppelmann
Signed-off-by: Peer Adelt
Signed-off-by: Palmer
From: Bastian Koppelmann
With decodetree we don't need to convert RISC-V opcodes into to MemOps
as the old gen_store() did.
Reviewed-by: Richard Henderson
Signed-off-by: Bastian Koppelmann
Signed-off-by: Peer Adelt
Signed-off-by: Palmer Dabbelt
---
target/riscv/insn_trans/trans_rvi.
From: Bastian Koppelmann
trans_jalr() is the only caller, so move the code into trans_jalr().
Acked-by: Alistair Francis
Reviewed-by: Richard Henderson
Signed-off-by: Bastian Koppelmann
Signed-off-by: Peer Adelt
Signed-off-by: Palmer Dabbelt
---
target/riscv/insn_trans/trans_rvi.inc.c
From: Bastian Koppelmann
Reviewed-by: Richard Henderson
Signed-off-by: Bastian Koppelmann
Signed-off-by: Peer Adelt
Signed-off-by: Palmer Dabbelt
---
target/riscv/insn16.decode | 43 +++
target/riscv/insn_trans/trans_rvc.inc.c | 151
target/riscv
From: Bastian Koppelmann
Acked-by: Alistair Francis
Reviewed-by: Richard Henderson
Signed-off-by: Bastian Koppelmann
Signed-off-by: Peer Adelt
Signed-off-by: Palmer Dabbelt
---
target/riscv/insn32-64.decode | 8 +
target/riscv/insn_trans/trans_rvd.inc.c | 82
target/riscv
From: Bastian Koppelmann
We now utilizes argument-sets of decodetree such that no manual
decoding is necessary.
Reviewed-by: Richard Henderson
Signed-off-by: Bastian Koppelmann
Signed-off-by: Peer Adelt
Signed-off-by: Palmer Dabbelt
---
target/riscv/insn_trans/trans_rvi.inc.c | 46
From: Bastian Koppelmann
Acked-by: Alistair Francis
Reviewed-by: Richard Henderson
Signed-off-by: Bastian Koppelmann
Signed-off-by: Peer Adelt
Signed-off-by: Palmer Dabbelt
---
target/riscv/insn32.decode | 2 ++
target/riscv/insn_trans/trans_rvi.inc.c | 19
From: Bastian Koppelmann
Acked-by: Alistair Francis
Reviewed-by: Richard Henderson
Signed-off-by: Bastian Koppelmann
Signed-off-by: Peer Adelt
Signed-off-by: Palmer Dabbelt
---
target/riscv/insn32.decode | 28 ++
target/riscv/insn_trans/trans_rvd.inc.c | 360
From: Bastian Koppelmann
Reviewed-by: Richard Henderson
Signed-off-by: Bastian Koppelmann
Signed-off-by: Peer Adelt
Signed-off-by: Palmer Dabbelt
---
target/riscv/Makefile.objs | 9 ++-
target/riscv/insn16.decode | 55 ++
target/riscv/insn_trans
From: Bastian Koppelmann
Acked-by: Alistair Francis
Reviewed-by: Richard Henderson
Signed-off-by: Bastian Koppelmann
Signed-off-by: Peer Adelt
Signed-off-by: Palmer Dabbelt
---
target/riscv/insn32.decode | 35 +++
target/riscv/insn_trans/trans_rvf.inc.c | 379
: Peer Adelt
Signed-off-by: Palmer Dabbelt
---
target/riscv/Makefile.objs | 8 +---
target/riscv/insn32-64.decode | 25 +
target/riscv/insn_trans/trans_rvi.inc.c | 20
target/riscv/translate.c| 7 ---
4
From: Bastian Koppelmann
Acked-by: Alistair Francis
Reviewed-by: Richard Henderson
Signed-off-by: Bastian Koppelmann
Signed-off-by: Peer Adelt
Signed-off-by: Palmer Dabbelt
---
target/riscv/insn32-64.decode | 7 ++
target/riscv/insn32.decode | 10 +++
target/riscv
From: Bastian Koppelmann
Acked-by: Alistair Francis
Reviewed-by: Richard Henderson
Signed-off-by: Bastian Koppelmann
Signed-off-by: Peer Adelt
Signed-off-by: Palmer Dabbelt
---
target/riscv/insn32-64.decode | 13 +++
target/riscv/insn_trans/trans_rva.inc.c | 58
From: Bastian Koppelmann
Acked-by: Alistair Francis
Reviewed-by: Richard Henderson
Signed-off-by: Bastian Koppelmann
Signed-off-by: Peer Adelt
Signed-off-by: Palmer Dabbelt
---
target/riscv/insn32.decode| 15 +++
.../riscv/insn_trans/trans_privileged.inc.c | 110
The following changes since commit 377b155bde451d5ac545fbdcdfbf6ca17a4228f5:
Merge remote-tracking branch 'remotes/bonzini/tags/for-upstream' into staging
(2019-03-11 18:26:37 +)
are available in the Git repository at:
git://github.com/palmer-dabbelt/qemu.git tags/riscv-for-
From: Bastian Koppelmann
Acked-by: Alistair Francis
Reviewed-by: Richard Henderson
Signed-off-by: Bastian Koppelmann
Signed-off-by: Peer Adelt
Signed-off-by: Palmer Dabbelt
---
target/riscv/insn32.decode | 8 +++
target/riscv/insn_trans/trans_rvi.inc.c | 79
From: Bastian Koppelmann
we cannot remove the call to gen_arith() in decode_RV32_64G() since it
is used to translate multiply instructions.
Acked-by: Alistair Francis
Reviewed-by: Richard Henderson
Signed-off-by: Bastian Koppelmann
Signed-off-by: Peer Adelt
Signed-off-by: Palmer Dabbelt
From: Bastian Koppelmann
for now only LUI & AUIPC are decoded and translated. If decodetree fails, we
fall back to the old decoder.
Reviewed-by: Richard Henderson
Acked-by: Alistair Francis
Signed-off-by: Bastian Koppelmann
Signed-off-by: Peer Adelt
Signed-off-by: Palmer Dab
From: Bastian Koppelmann
Acked-by: Alistair Francis
Reviewed-by: Richard Henderson
Signed-off-by: Bastian Koppelmann
Signed-off-by: Peer Adelt
Signed-off-by: Palmer Dabbelt
---
target/riscv/insn32.decode | 17 +++
target/riscv/insn_trans/trans_rva.inc.c | 160
From: Bastian Koppelmann
Acked-by: Alistair Francis
Reviewed-by: Richard Henderson
Signed-off-by: Bastian Koppelmann
Signed-off-by: Peer Adelt
Signed-off-by: Palmer Dabbelt
---
target/riscv/insn32.decode | 10 ++
target/riscv/insn_trans/trans_rvi.inc.c | 48
From: Bastian Koppelmann
Acked-by: Alistair Francis
Reviewed-by: Palmer Dabbelt
Reviewed-by: Richard Henderson
Signed-off-by: Bastian Koppelmann
Signed-off-by: Peer Adelt
Signed-off-by: Palmer Dabbelt
---
target/riscv/insn32.decode | 19 ++
target/riscv/insn_trans
On Tue, 12 Mar 2019 10:36:05 PDT (-0700), arm...@redhat.com wrote:
Machines with no maintainer, but at least one supporter:
[...]
= hw/riscv/sifive_e.c =
Palmer Dabbelt (supporter:RISC-V)
Alistair Francis (supporter:RISC-V)
Sagar Karandikar (supporter:RISC-V)
Bastian
From: Bastian Koppelmann
gen_arith_imm() does a lot of decoding manually, which was hard to read
in case of the shift instructions and is not necessary anymore with
decodetree.
Reviewed-by: Richard Henderson
Signed-off-by: Bastian Koppelmann
Signed-off-by: Peer Adelt
---
target/riscv/insn32.
From: Bastian Koppelmann
decodetree handles all instructions now so the fallback is not necessary
anymore.
Reviewed-by: Richard Henderson
Signed-off-by: Bastian Koppelmann
Signed-off-by: Peer Adelt
---
target/riscv/translate.c | 21 +
1 file changed, 1 insertion(+), 20 de
From: Bastian Koppelmann
manual decoding in gen_arith() is not necessary with decodetree. For now
the function is called trans_arith as the original gen_arith still
exists. The former will be renamed to gen_arith as soon as the old
gen_arith can be removed.
Reviewed-by: Richard Henderson
Signed
From: Bastian Koppelmann
With decodetree we don't need to convert RISC-V opcodes into to MemOps
as the old gen_store() did.
Reviewed-by: Richard Henderson
Signed-off-by: Bastian Koppelmann
Signed-off-by: Peer Adelt
---
target/riscv/insn_trans/trans_rvi.inc.c | 27 +
t
From: Bastian Koppelmann
We now utilizes argument-sets of decodetree such that no manual
decoding is necessary.
Reviewed-by: Richard Henderson
Signed-off-by: Bastian Koppelmann
Signed-off-by: Peer Adelt
---
target/riscv/insn_trans/trans_rvi.inc.c | 46 +---
target/riscv/t
From: Bastian Koppelmann
Reviewed-by: Richard Henderson
Signed-off-by: Bastian Koppelmann
Signed-off-by: Peer Adelt
---
target/riscv/insn_trans/trans_rvm.inc.c | 55 ++--
target/riscv/translate.c| 320 ++--
2 files changed, 164 insertions(+), 211 deletions
From: Bastian Koppelmann
Reviewed-by: Richard Henderson
Signed-off-by: Bastian Koppelmann
Signed-off-by: Peer Adelt
---
target/riscv/insn16.decode | 31
target/riscv/insn_trans/trans_rvc.inc.c | 101
target/riscv/translate.c| 83
From: Bastian Koppelmann
with all 16 bit insns moved to decodetree no path is falling back to
gen_system(), so we can remove it.
Reviewed-by: Richard Henderson
Signed-off-by: Bastian Koppelmann
Signed-off-by: Peer Adelt
---
target/riscv/translate.c | 34 --
1
From: Bastian Koppelmann
Acked-by: Alistair Francis
Reviewed-by: Richard Henderson
Signed-off-by: Bastian Koppelmann
Signed-off-by: Peer Adelt
---
target/riscv/insn32.decode | 28 ++
target/riscv/insn_trans/trans_rvd.inc.c | 360
target/riscv/translate.
From: Bastian Koppelmann
Reviewed-by: Richard Henderson
Signed-off-by: Bastian Koppelmann
Signed-off-by: Peer Adelt
---
target/riscv/insn_trans/trans_rvi.inc.c | 93 +
target/riscv/translate.c| 59 +---
2 files changed, 81 insertions(+), 71
From: Bastian Koppelmann
Reviewed-by: Richard Henderson
Signed-off-by: Bastian Koppelmann
---
target/riscv/insn_trans/trans_rvi.inc.c | 18 +-
target/riscv/insn_trans/trans_rvm.inc.c | 14 +++---
target/riscv/translate.c| 4 ++--
3 files changed, 18 ins
From: Bastian Koppelmann
Reviewed-by: Richard Henderson
Signed-off-by: Bastian Koppelmann
Signed-off-by: Peer Adelt
---
target/riscv/Makefile.objs | 9 ++-
target/riscv/insn16.decode | 55 ++
target/riscv/insn_trans/trans_rvc.inc.c | 75 +
From: Bastian Koppelmann
With decodetree we don't need to convert RISC-V opcodes into to MemOps
as the old gen_load() did.
Reviewed-by: Richard Henderson
Signed-off-by: Bastian Koppelmann
Signed-off-by: Peer Adelt
---
target/riscv/insn_trans/trans_rvi.inc.c | 35 +++--
ta
From: Bastian Koppelmann
Acked-by: Alistair Francis
Reviewed-by: Richard Henderson
Signed-off-by: Bastian Koppelmann
Signed-off-by: Peer Adelt
---
target/riscv/insn32.decode | 35 +++
target/riscv/insn_trans/trans_rvf.inc.c | 379
target/riscv/translate
From: Bastian Koppelmann
Acked-by: Alistair Francis
Reviewed-by: Richard Henderson
Signed-off-by: Bastian Koppelmann
Signed-off-by: Peer Adelt
---
target/riscv/insn32-64.decode | 8 +
target/riscv/insn_trans/trans_rvd.inc.c | 82
target/riscv/translate.c| 60
From: Bastian Koppelmann
trans_jalr() is the only caller, so move the code into trans_jalr().
Acked-by: Alistair Francis
Reviewed-by: Richard Henderson
Signed-off-by: Bastian Koppelmann
Signed-off-by: Peer Adelt
---
target/riscv/insn_trans/trans_rvi.inc.c | 28 +-
target/ris
From: Bastian Koppelmann
Acked-by: Alistair Francis
Reviewed-by: Richard Henderson
Signed-off-by: Bastian Koppelmann
Signed-off-by: Peer Adelt
---
target/riscv/insn32-64.decode | 6 +++
target/riscv/insn_trans/trans_rvf.inc.c | 60 +
2 files changed, 66 ins
From: Bastian Koppelmann
Acked-by: Alistair Francis
Reviewed-by: Richard Henderson
Signed-off-by: Bastian Koppelmann
Signed-off-by: Peer Adelt
---
target/riscv/insn32.decode| 15 +++
.../riscv/insn_trans/trans_privileged.inc.c | 110 ++
target/riscv/tra
From: Bastian Koppelmann
Acked-by: Alistair Francis
Reviewed-by: Richard Henderson
Signed-off-by: Bastian Koppelmann
Signed-off-by: Peer Adelt
---
target/riscv/insn32-64.decode | 7 ++
target/riscv/insn32.decode | 10 +++
target/riscv/insn_trans/trans_rvm.inc.c | 11
From: Bastian Koppelmann
Acked-by: Alistair Francis
Reviewed-by: Richard Henderson
Signed-off-by: Bastian Koppelmann
Signed-off-by: Peer Adelt
---
target/riscv/insn32-64.decode | 13 +++
target/riscv/insn_trans/trans_rva.inc.c | 58 ++
target/riscv/translate.c
From: Bastian Koppelmann
Acked-by: Alistair Francis
Reviewed-by: Richard Henderson
Signed-off-by: Bastian Koppelmann
Signed-off-by: Peer Adelt
---
target/riscv/insn32.decode | 8 +++
target/riscv/insn_trans/trans_rvi.inc.c | 79 +
target/riscv/translate.
From: Bastian Koppelmann
Acked-by: Alistair Francis
Reviewed-by: Richard Henderson
Signed-off-by: Bastian Koppelmann
Signed-off-by: Peer Adelt
---
target/riscv/insn32.decode | 17 +++
target/riscv/insn_trans/trans_rva.inc.c | 160
target/riscv/translate
From: Bastian Koppelmann
Acked-by: Alistair Francis
Reviewed-by: Richard Henderson
Signed-off-by: Bastian Koppelmann
Signed-off-by: Peer Adelt
---
target/riscv/insn32.decode | 2 ++
target/riscv/insn_trans/trans_rvi.inc.c | 19 +++
target/riscv/translate.c
From: Bastian Koppelmann
for now only LUI & AUIPC are decoded and translated. If decodetree fails, we
fall back to the old decoder.
Reviewed-by: Richard Henderson
Acked-by: Alistair Francis
Signed-off-by: Bastian Koppelmann
Signed-off-by: Peer Adelt
---
target/riscv/Makefile.objs
From: Bastian Koppelmann
we cannot remove the call to gen_arith() in decode_RV32_64G() since it
is used to translate multiply instructions.
Acked-by: Alistair Francis
Reviewed-by: Richard Henderson
Signed-off-by: Bastian Koppelmann
Signed-off-by: Peer Adelt
---
target/riscv/insn32-64.decode
From: Bastian Koppelmann
this splits the 64-bit only instructions into its own decode file such
that we generate the decoder for these instructions only for the RISC-V
64 bit target.
Acked-by: Alistair Francis
Reviewed-by: Richard Henderson
Signed-off-by: Bastian Koppelmann
Signed-off-by: Pee
From: Bastian Koppelmann
Acked-by: Alistair Francis
Reviewed-by: Palmer Dabbelt
Reviewed-by: Richard Henderson
Signed-off-by: Bastian Koppelmann
Signed-off-by: Peer Adelt
---
target/riscv/insn32.decode | 19 ++
target/riscv/insn_trans/trans_rvi.inc.c | 49
From: Bastian Koppelmann
Acked-by: Alistair Francis
Reviewed-by: Richard Henderson
Signed-off-by: Bastian Koppelmann
Signed-off-by: Peer Adelt
---
target/riscv/insn32.decode | 10 ++
target/riscv/insn_trans/trans_rvi.inc.c | 48 +
2 files changed, 58
staging (2019-03-12
21:06:26 +)
are available in the Git repository at:
git://github.com/palmer-dabbelt/qemu.git tags/riscv-for-master-4.0-sf4
for you to fetch changes up to 25e6ca30c668783cd72ff97080ff44e141b99f9b:
target/riscv: Remove decode_RV32_64G() (2019-
On Thu, 14 Mar 2019 10:30:20 PDT (-0700), alistai...@gmail.com wrote:
On Thu, Mar 14, 2019 at 10:09 AM Michael S. Tsirkin wrote:
On Thu, Mar 14, 2019 at 03:30:30PM +0100, Paolo Bonzini wrote:
> RISC-V targets did not include PCIe ports before the Kconfig transition,
> and grew them afterwards,
On Thu, 14 Mar 2019 13:28:37 PDT (-0700), alistai...@gmail.com wrote:
On Wed, Mar 13, 2019 at 7:53 AM Palmer Dabbelt wrote:
From: Bastian Koppelmann
Reviewed-by: Richard Henderson
Signed-off-by: Bastian Koppelmann
Signed-off-by: Peer Adelt
This commit is the first bad commit in
On Thu, 14 Mar 2019 21:57:37 PDT (-0700), alistai...@gmail.com wrote:
On Thu, Mar 14, 2019 at 8:59 PM Palmer Dabbelt wrote:
On Thu, 14 Mar 2019 13:28:37 PDT (-0700), alistai...@gmail.com wrote:
> On Wed, Mar 13, 2019 at 7:53 AM Palmer Dabbelt wrote:
>>
>> From: Bas
On Fri, 15 Mar 2019 02:06:07 PDT (-0700), Bastian Koppelmann wrote:
Hi Alistair
On 3/14/19 9:28 PM, Alistair Francis wrote:
On Wed, Mar 13, 2019 at 7:53 AM Palmer Dabbelt wrote:
From: Bastian Koppelmann
Reviewed-by: Richard Henderson
Signed-off-by: Bastian Koppelmann
Signed-off-by: Peer
STORE:
cs->exception_index = RISCV_EXCP_STORE_PAGE_FAULT;
break;
+default:
+g_assert_not_reached();
}
+env->badaddr = address;
cpu_loop_exit_restore(cs, retaddr);
#endif
}
Reviewed-by: Palmer Dabbelt
I fixed up your Author tag and added this to for-master. Thanks!
On Mon, 07 Oct 2019 11:05:33 PDT (-0700), alistai...@gmail.com wrote:
On Thu, Oct 3, 2019 at 8:53 AM Palmer Dabbelt wrote:
On Fri, 23 Aug 2019 16:38:47 PDT (-0700), Alistair Francis wrote:
> Signed-off-by: Alistair Francis
> ---
> target/riscv/cpu_help
On Tue, 08 Oct 2019 15:04:18 PDT (-0700), Alistair Francis wrote:
Instead of relying on atomics to access the MIP register let's update
our helper function to instead just lock the IO mutex thread before
writing. This follows the same concept as used in PPC for handling
interrupts
Signed-off-by:
On Mon, 14 Oct 2019 10:59:07 PDT (-0700), alistai...@gmail.com wrote:
On Mon, Oct 14, 2019 at 4:20 AM Alex Bennée wrote:
From: "Emilio G. Cota"
Signed-off-by: Emilio G. Cota
Reviewed-by: Richard Henderson
Signed-off-by: Alex Bennée
Reviewed-by: Alistair Francis
and
Acked-
On Mon, 14 Oct 2019 08:45:26 PDT (-0700), jonat...@fintelia.io wrote:
This series adds a new "priv" virtual register that reports the current
privilege mode. This is helpful for debugging purposes because that information
is not actually available in any of the real CSRs.
The third patch in thi
On Tue, 15 Oct 2019 01:35:31 PDT (-0700), Anup Patel wrote:
This patch adds model for Google Goldfish virtual platform RTC device.
We will be adding Goldfish RTC device to the QEMU RISC-V virt machine
for providing real date-time to Guest Linux. The corresponding Linux
driver for Goldfish RTC de
UART0_IRQ = 10,
+RTC_IRQ = 11,
VIRTIO_IRQ = 1, /* 1 to 8 */
VIRTIO_COUNT = 8,
PCIE_IRQ = 0x20, /* 32 to 35 */
This is a wacky enum, but it's already there. I'm going to assume this patch
will get merged and then fix it later.
--
2.17.1
Reviewed-by: Palmer Dabbelt
On Tue, 15 Oct 2019 10:04:32 PDT (-0700), day...@berkeley.edu wrote:
Hi,
Could this patch go through?
If not please let me know so that I can fix.
Thank you!
Sorry, I dropped this one. It's in the patch queue now. We should also check
for size==0 in pmp_hart_has_privs(), as that won't work.
On Thu, 17 Oct 2019 05:08:39 PDT (-0700), Peter Maydell wrote:
Ping? It would be nice to see this patch get into master
to silence the coverity errors.
Sorry, it looks like I dropped this. It's in my queue, I hope to submit a PR
soon.
thanks
-- PMM
On Thu, 3 Oct 2019 at 18:05, Alistair F
On Tue, 22 Oct 2019 14:21:29 PDT (-0700), day...@berkeley.edu wrote:
riscv_cpu_tlb_fill() uses the `size` parameter to check PMP violation
using pmp_hart_has_privs().
However, if the size is unknown (=0), the ending address will be
`addr - 1` as it is `addr + size - 1` in `pmp_hart_has_privs()`.
(env, 0);
+if (riscv_cpu_fp_enabled(env)) {
+*flags |= env->mstatus & MSTATUS_FS;
+}
#endif
}
Reviewed-by: Palmer Dabbelt
riscv_cpu_fp_enabled(CPURISCVState *env)
{
if (env->mstatus & MSTATUS_FS) {
+if (riscv_cpu_virt_enabled(env) && !(env->mstatus_hs & MSTATUS_FS)) {
+return false;
+}
return true;
}
Reviewed-by: Palmer Dabbelt
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