hi,
On 24/01/2023 11:27, Thomas Huth wrote:
On 24/01/2023 10.20, Thomas Huth wrote:
[...]
On Thu, Jan 19, 2023 at 12:31 PM Thomas Huth
wrote:
Hi all,
in some spare minutes, I started playing with a patch to try to
remove the
dtc submodule from the QEMU git repository - according to
ht
In section 7.4.3 of the 82574 datasheet it states that
"In systems that do not support MSI-X, reading the ICR
register clears it's bits..."
Some OSes rely on this.
Signed-off-by: Nick Hudson
---
hw/net/e1000e_core.c | 5 +
hw/net/trace-events | 1 +
2 files change
In section 7.4.3 of the 82574 datasheet it states that
"In systems that do not support MSI-X, reading the ICR
register clears it's bits..."
Some OSes rely on this.
Signed-off-by: Nick Hudson
---
hw/net/e1000e_core.c | 5 +
hw/net/trace-events | 1 +
2 files change
have occupied.
Clarify the load_uimage API to state the passing of a load address when an
image doesn't specify one, or when loading a ramdisk is expected.
Adjust callers of load_uimage, etc.
Signed-off-by: Nick Hudson
---
hw/arm/boot.c | 8 +---
hw/core/loader.c
noload kernels are loaded with the u-boot image header and as a result
the header size needs adding to the entry point. Fake up a hdr so the
kernel image is loaded at the right address and the entry point is
adjusted appropriately
Signed-off-by: Nick Hudson
---
hw/arm/boot.c | 8
ping
On 07/11/2018 13:19, Nick Hudson wrote:
noload kernels are loaded with the u-boot image header and as a result
the header size needs adding to the entry point. Fake up a hdr so the
kernel image is loaded at the right address and the entry point is
adjusted appropriately
Signed-off-by
On 16/11/2018 14:34, Peter Maydell wrote:
On 7 November 2018 at 13:19, Nick Hudson wrote:
noload kernels are loaded with the u-boot image header and as a result
the header size needs adding to the entry point. Fake up a hdr so the
kernel image is loaded at the right address and the entry
have occupied.
Update the load_uimage API to allow passing of load address when an image
doesn't specify one.
Signed-off-by: Nick Hudson
---
hw/arm/boot.c | 8 +---
hw/core/loader.c | 15 ---
hw/core/uboot_image.h | 1 +
include/hw/loader.h | 3 ++-
4 files ch
On 30/11/2018 17:18, Peter Maydell wrote:
On Thu, 29 Nov 2018 at 20:22, Nick Hudson wrote:
noload kernels are loaded with the u-boot image header and as a result
the header size needs adding to the entry point. Fake up a hdr so the
kernel image is loaded at the right address and the entry
ping
On 11/12/2018 12:27, Nick Hudson wrote:
noload kernels are loaded with the u-boot image header and as a result
the header size needs adding to the entry point. Fake up a hdr so the
kernel image is loaded at the right address and the entry point is
adjusted appropriately.
The bootloader
On 03/01/2019 16:20, Peter Maydell wrote:
> On Tue, 11 Dec 2018 at 12:27, Nick Hudson wrote:
>>
>>
>> noload kernels are loaded with the u-boot image header and as a result
>> the header size needs adding to the entry point. Fake up a hdr so the
>> kernel ima
On 03/01/2019 17:27, Peter Maydell wrote:
On Thu, 3 Jan 2019 at 16:50, Nick Hudson wrote:
On 03/01/2019 16:20, Peter Maydell wrote:
On Tue, 11 Dec 2018 at 12:27, Nick Hudson wrote:
--- a/hw/arm/boot.c
+++ b/hw/arm/boot.c
@@ -30,8 +30,9 @@
* Documentation/arm/Booting and
noload kernels are loaded with the u-boot image header and as a result
the header size needs adding to the entry point. Fake up a hdr so the
kernel image is loaded at the right address and the entry point is
adjusted appropriately.
The default location for the uboot file is 32MiB above bottom o
On 06/01/2019 22:56, no-re...@patchew.org wrote:
Patchew URL:
https://patchew.org/QEMU/d19529f5-841e-ea06-fe7d-86ccfd528...@gmail.com/
Hi,
This series seems to have some coding style problems. See output below for
more information:
The files being touched have lots of coding style probl
Thanks for the comments.
On 07/01/2019 00:33, BALATON Zoltan wrote:
On Sun, 6 Jan 2019, Nick Hudson wrote:
noload kernels are loaded with the u-boot image header and as a result
the header size needs adding to the entry point. Fake up a hdr so the
kernel image is loaded at the right address
of DRAM.
This matches the recommendation in Documentation/arm/Booting.
Clarify the load_uimage API to state the passing of a load address when an
image doesn't specify one, or when loading a ramdisk is expected.
Adjust callers of load_uimage, etc.
Signed-off-by: Nick Hudson
---
hw/arm/b
Fix building on NetBSD/arm by extracting the FSR value from the
correct siginfo_t field.
Signed-off-by: Nick Hudson
---
accel/tcg/user-exec.c | 10 ++
1 file changed, 10 insertions(+)
diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c
index 52359949df..3637626456 100644
--- a
Fix building on NetBSD/arm by extracting the FSR value from the
correct siginfo_t field.
Signed-off-by: Nick Hudson
---
accel/tcg/user-exec.c | 16 +---
1 file changed, 13 insertions(+), 3 deletions(-)
diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c
index 52359949df
Fix qemu build on NetBSD/evbarm-aarch64 by providing a NetBSD specific
cpu_signal_handler.
Signed-off-by: Nick Hudson
---
accel/tcg/user-exec.c | 26 ++
1 file changed, 26 insertions(+)
diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c
index 4be78eb9b3
Fix qemu build on NetBSD/evbarm-aarch64 by providing a NetBSD specific
cpu_signal_handler.
Signed-off-by: Nick Hudson
---
accel/tcg/user-exec.c | 26 ++
1 file changed, 26 insertions(+)
diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c
index 4be78eb9b3
> On 29 Jun 2021, at 10:49, Peter Maydell wrote:
>
> On Tue, 29 Jun 2021 at 09:27, wrote:
>>
>> Signed-off-by: Nick Hudson
>> ---
>> target/arm/helper.c | 2 +-
>> 1 file changed, 1 insertion(+), 1 deletion(-)
>>
>> diff --git a/target/arm
Signed-off-by: Nick Hudson
---
target/arm/helper.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/arm/helper.c b/target/arm/helper.c
index a66c1f0b9e..7267af7924 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -6330,7 +6330,7 @@ static const ARMCPRegInfo
> On 29 Jun 2021, at 12:50, Peter Maydell wrote:
>
> On Tue, 29 Jun 2021 at 11:41, Nick Hudson wrote:
>>
>>
>>
>>> On 29 Jun 2021, at 10:49, Peter Maydell wrote:
>>>
>>> On Tue, 29 Jun 2021 at 09:27, wrote:
>>>>
>
> On 29 Jun 2021, at 12:50, Peter Maydell wrote:
>
> On Tue, 29 Jun 2021 at 11:41, Nick Hudson wrote:
>>
>>
>>
>>> On 29 Jun 2021, at 10:49, Peter Maydell wrote:
>>>
>>> On Tue, 29 Jun 2021 at 09:27, wrote:
>>>>
>
Hi,
Here are the required changes to allow qemu to emulate NetBSD/hppa.
Nick Hudson (2):
Implement the pcxl and pcxl2 Fast TLB Insert instructions as used by
NetBSD (and OpenBSD)
Always return EXCP_DMAR for protection id trap as EXCP_DMP is
considered legacy.
target/hppa
Always return EXCP_DMAR for protection id trap as EXCP_DMP is considered legacy.
"In PA-RISC 1.1 (Second Edition) and later revisions, processors must
use traps 26, 27,and 28 which provide equivalent functionality"
Signed-off-by: Nick Hudson
---
target/hppa/mem_helper.c | 3 +--
1 fi
Implement the pcxl and pcxl2 Fast TLB Insert instructions as used by NetBSD
(and OpenBSD)
See
https://parisc.wiki.kernel.org/images-parisc/a/a9/Pcxl2_ers.pdf
page 13-9 (195/206)
Signed-off-by: Nick Hudson
---
target/hppa/insns.decode | 3 +++
target/hppa/translate.c | 54
From: Nick Hudson
See
https://parisc.wiki.kernel.org/images-parisc/a/a9/Pcxl2_ers.pdf
page 13-9 (195/206)
Signed-off-by: Nick Hudson
---
target/hppa/insns.decode | 3 +++
target/hppa/translate.c | 52
2 files changed, 55 insertions(+)
diff
From: Nick Hudson
Here are the required changes to allow qemu to emulate NetBSD/hppa.
v2 changes:
- remove old debug code
Nick Hudson (2):
Implement the pcxl and pcxl2 Fast TLB Insert instructions as used by
NetBSD (and OpenBSD)
Always return EXCP_DMAR for protection id trap as
From: Nick Hudson
"In PA-RISC 1.1 (Second Edition) and later revisions, processors must use
traps 26, 27,and 28 which provide equivalent functionality"
Signed-off-by: Nick Hudson
---
target/hppa/mem_helper.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/t
v3 changes:
- Don't use C99 comments and fix a typo in the comment
v2 changes:
- remove old debug code
*** BLURB HERE ***
Nick Hudson (2):
Implement the pcxl and pcxl2 Fast TLB Insert instructions as used by
NetBSD (and OpenBSD)
Always return EXCP_DMAR for protection id tr
From: Nick Hudson
See
https://parisc.wiki.kernel.org/images-parisc/a/a9/Pcxl2_ers.pdf
page 13-9 (195/206)
Signed-off-by: Nick Hudson
---
target/hppa/insns.decode | 3 +++
target/hppa/translate.c | 52
2 files changed, 55 insertions(+)
diff
From: Nick Hudson
"In PA-RISC 1.1 (Second Edition) and later revisions, processors must use
traps 26, 27,and 28 which provide equivalent functionality"
Signed-off-by: Nick Hudson
---
target/hppa/mem_helper.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/t
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