> On 29 Jun 2021, at 10:49, Peter Maydell <peter.mayd...@linaro.org> wrote:
>
> On Tue, 29 Jun 2021 at 09:27, <hn...@vmware.com> wrote:
>>
>> Signed-off-by: Nick Hudson <hn...@vmware.com>
>> ---
>> target/arm/helper.c | 2 +-
>> 1 file changed, 1 insertion(+), 1 deletion(-)
>>
>> diff --git a/target/arm/helper.c b/target/arm/helper.c
>> index a66c1f0b9e..7267af7924 100644
>> --- a/target/arm/helper.c
>> +++ b/target/arm/helper.c
>> @@ -6330,7 +6330,7 @@ static const ARMCPRegInfo debug_cp_reginfo[] = {
>> * We don't implement the configurable EL0 access.
>> */
>> { .name = "MDCCSR_EL0", .state = ARM_CP_STATE_BOTH,
>> - .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 0,
>> + .cp = 14, .opc0 = 2, .opc1 = 3, .crn = 0, .crm = 1, .opc2 = 0,
>> .type = ARM_CP_ALIAS,
>> .access = PL1_R, .accessfn = access_tda,
>> .fieldoffset = offsetof(CPUARMState, cp15.mdscr_el1), },
>
> This fixes the encoding for AArch64, but breaks it for AArch32,
> where it is cp=14 opc1=0 crn=0 crm=1 opc2=0. Because this is one of
> those system registers where the AArch64 and AArch32 encodings
> don't match up, to fix the AArch64 encoding we need to replace
> this ARM_CP_STATE_BOTH reginfo with separate reginfo for
> ARM_CP_STATE_AA32 and ARM_CP_STATE_AA64, something like this:
>
> { .name = "MDCCSR_EL0", .state = ARM_CP_STATE_AA64,
> .opc0 = 2, .opc1 = 3, .crn = 0, .crm = 1, .opc2 = 0,
> .type = ARM_CP_ALIAS,
> .access = PL1_R, .accessfn = access_tda,
> .fieldoffset = offsetof(CPUARMState, cp15.mdscr_el1), },
> { .name = "DBGDSCRint", .state = ARM_CP_STATE_AA32,
> .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 0,
> .type = ARM_CP_ALIAS,
> .access = PL1_R, .accessfn = access_tda,
> .fieldoffset = offsetoflow32(CPUARMState, cp15.mdscr_el1), },
>
Ah, yes.
As MDCCSR_EL0[30:29] only maps to DBGDSCRint[30:29] maybe it should be all RAZ?
Thanks,
Nick
