[Qemu-devel] [PATCH v31 3/8] target/avr: Add instruction decoding

This includes: - encoding of all 16 bit instructions - encoding of all 32 bit instructions Signed-off-by: Michael Rolnik --- target/avr/insn.decode | 175 + 1 file changed, 175 insertions(+) create mode 100644 target/avr/insn.decode diff --git a/target

[Qemu-devel] [PATCH v31 6/8] target/avr: Add example board configuration

0,0 +1,282 @@ +/* + * QEMU AVR CPU + * + * Copyright (c) 2019 Michael Rolnik + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2.1 of the L

[Qemu-devel] [PATCH v31 7/8] target/avr: Register AVR support with the rest of QEMU, the build system, and the MAINTAINERS file

Signed-off-by: Michael Rolnik --- MAINTAINERS | 6 +++ arch_init.c | 2 + configure | 89 ++--- default-configs/avr-softmmu.mak | 5 ++ include/disas/dis-asm.h | 6 +++ include/sysemu

[Qemu-devel] [PATCH v31 8/8] target/avr: Add tests

#x27;T' through serial port Signed-off-by: Michael Rolnik Reviewed-by: Philippe Mathieu-Daudé Tested-by: Philippe Mathieu-Daudé Acked-by: Thomas Huth --- tests/Makefile.include | 2 ++ tests/acceptance/machine_avr6.py | 36 tests/boot-serial

[Qemu-devel] [PATCH v31 4/8] target/avr: Add instruction translation

This includes: - TCG translations for each instruction Signed-off-by: Michael Rolnik --- target/avr/translate.c | 2888 1 file changed, 2888 insertions(+) create mode 100644 target/avr/translate.c diff --git a/target/avr/translate.c b/target/avr

Re: [PATCH v31 0/8] QEMU AVR 8 bit cores

Hi all, is there any hope this will be ever pulled? regards, Michael On Sun, Sep 15, 2019 at 3:20 PM Michael Rolnik wrote: > This series of patches adds 8bit AVR cores to QEMU. > All instruction, except BREAK/DES/SPM/SPMX, are implemented. Not fully > tested yet. > However I

Re: [PATCH v31 0/8] QEMU AVR 8 bit cores

Hi all, Is there any hope this will be pulled any time soon? Regards, Michael Rolnik On Sun, Sep 15, 2019 at 3:20 PM Michael Rolnik wrote: > This series of patches adds 8bit AVR cores to QEMU. > All instruction, except BREAK/DES/SPM/SPMX, are implemented. Not fully > tested yet. &g

Re: [PATCH v31 0/8] QEMU AVR 8 bit cores

Thanks Philippe. On Mon, Sep 23, 2019 at 6:29 PM Philippe Mathieu-Daudé wrote: > Hi Michael, > > On 9/23/19 5:21 PM, Michael Rolnik wrote: > > Hi all, > > > > Is there any hope this will be pulled any time soon? > > I have your v28 tagged for review/test, but I

Re: [PATCH v35 05/13] target/avr: Add instruction translation - Arithmetic and Logic Instructions

t; > > > Or, perhaps, > > > > > > TCGv Rd = cpu_r[a->rd]; > > > > > > should be > > > > > > TCGv Rd = cpu_r[a->rd + 16]; > > > > > > (and the same for rs) > > > > This happens during decode: > > > > +%rd_b 4:3 !function=to_B > > +%rr_b 0:3 !function=to_B > > +@fmul . ... . ... &rd_rr rd=%rd_b rr=%rr_b > > +FMUL 0011 0 ... 1 ... @fmul > > +FMULS 0011 1 ... 0 ... @fmul > > +FMULSU 0011 1 ... 1 ... @fmul > > > > This means that a->rd = to_B(extract32(insn, 4, 3)), and > > > > > +static int to_B(DisasContext *ctx, int indx) { return 16 + (indx % 8); } > > > > et voila. > > > > OK. Thanks for clarification. > > > > > r~ -- Best Regards, Michael Rolnik

Re: [PATCH v35 05/13] target/avr: Add instruction translation - Arithmetic and Logic Instructions

Sounds good, thanks! On Tue, Nov 19, 2019 at 11:18 PM Aleksandar Markovic wrote: > > On Tue, Nov 19, 2019 at 9:09 PM Michael Rolnik wrote: > > > > Hi Aleksandar et al. > > > > how is it going? should I rebase or not? > > > > Michael > > > >

Re: [Qemu-devel] [PATCH for 4.2 v28 0/8] QEMU AVR 8 bit cores

ping On Mon, Aug 5, 2019 at 5:14 PM Michael Rolnik wrote: > This series of patches adds 8bit AVR cores to QEMU. > All instruction, except BREAK/DES/SPM/SPMX, are implemented. Not fully > tested yet. > However I was able to execute simple code with functions. e.g fibonacci > calc

[Qemu-devel] [PATCH v29 6/8] target/avr: Add example board configuration

PU testing Signed-off-by: Michael Rolnik --- hw/Kconfig | 1 + hw/avr/Kconfig | 6 + hw/avr/Makefile.objs | 1 + hw/avr/sample.c | 282 +++ 4 files changed, 290 insertions(+) create mode 100644 hw/avr/Kconfig create mode 100

[Qemu-devel] [PATCH v29 0/8] QEMU AVR 8 bit cores

late prr0/prr1 changes since v26 1. add avocado acceptence test 2. add boot serial test changes since v27 1. list atmel2560 devices as unimplemented 2. fix sram base/size changes since v28 1. rebase 2. fix includes & build Michael Rolnik (4): target/avr: Add instruction decoding targ

[Qemu-devel] [PATCH v29 2/8] target/avr: Add instruction helpers

wake interrupts. Memory access instructions are implemented here because some address ranges actually refer to CPU registers. Signed-off-by: Michael Rolnik --- target/avr/helper.c | 354 target/avr/helper.h | 29 2 files changed, 383 insertions

[Qemu-devel] [PATCH v29 1/8] target/avr: Add outward facing interfaces and core CPU logic

From: Sarah Harris This includes: - CPU data structures - object model classes and functions - migration functions - GDB hooks Signed-off-by: Michael Rolnik Acked-by: Igor Mammedov --- gdb-xml/avr-cpu.xml| 49 target/avr/cpu-param.h | 37 +++ target/avr/cpu-qom.h | 54

[Qemu-devel] [PATCH v29 8/8] target/avr: Add tests

#x27;T' through serial port Signed-off-by: Michael Rolnik Reviewed-by: Philippe Mathieu-Daudé Tested-by: Philippe Mathieu-Daudé --- tests/Makefile.include | 2 ++ tests/acceptance/machine_avr6.py | 36 tests/boot-serial-test.c | 10 +

[Qemu-devel] [PATCH v29 4/8] target/avr: Add instruction translation

This includes: - TCG translations for each instruction Signed-off-by: Michael Rolnik --- target/avr/translate.c | 2888 1 file changed, 2888 insertions(+) create mode 100644 target/avr/translate.c diff --git a/target/avr/translate.c b/target/avr

[Qemu-devel] [PATCH v29 3/8] target/avr: Add instruction decoding

This includes: - encoding of all 16 bit instructions - encoding of all 32 bit instructions Signed-off-by: Michael Rolnik --- target/avr/insn.decode | 175 + 1 file changed, 175 insertions(+) create mode 100644 target/avr/insn.decode diff --git a/target

[Qemu-devel] [PATCH v29 7/8] target/avr: Register AVR support with the rest of QEMU, the build system, and the MAINTAINERS file

Signed-off-by: Michael Rolnik --- MAINTAINERS | 6 ++ arch_init.c | 2 ++ configure | 7 +++ default-configs/avr-softmmu.mak | 5 + include/disas/dis-asm.h | 6 ++ include/sysemu/arch_init.h | 1

[Qemu-devel] [PATCH v29 5/8] target/avr: Add limited support for USART and 16 bit timer peripherals

-off-by: Michael Rolnik --- hw/char/Kconfig| 3 + hw/char/Makefile.objs | 1 + hw/char/avr_usart.c| 324 ++ hw/misc/Kconfig| 3 + hw/misc/Makefile.objs | 2 + hw/misc/avr_mask.c | 112 ++ hw/timer

Re: [Qemu-devel] [PATCH v29 0/8] QEMU AVR 8 bit cores

e- > > From: Michael Rolnik [mailto:mrol...@gmail.com] > > Sent: Saturday, August 24, 2019 9:46 PM > > To: qemu-devel@nongnu.org > > Cc: richard.hender...@linaro.org; phi...@redhat.com; th...@redhat.com; > dovga...@ispras.ru; > > imamm...@redhat.com; Michael

Re: [Qemu-devel] [PATCH v29 1/8] target/avr: Add outward facing interfaces and core CPU logic

the commit was originally mine. Then Sarah rearranged it, signed and submitted. She no longer maintains it. So' I believe I can remove her sob. what do you think?. Michael On Mon, Aug 26, 2019 at 10:21 AM Thomas Huth wrote: > On 24/08/2019 20.46, Michael Rolnik wrote: > > From

[PATCH v34 03/13] target/avr: Add instruction decoding

This includes: - encoding of all 16 bit instructions - encoding of all 32 bit instructions Signed-off-by: Michael Rolnik --- target/avr/insn.decode | 175 + 1 file changed, 175 insertions(+) create mode 100644 target/avr/insn.decode diff --git a/target

[PATCH v34 00/13] QEMU AVR 8 bit cores

#x27;Add instruction translation - CPU main translation funcions' commit changes since v32 1. modify cpu_get_sreg to treat sreg C as other flags, except sreg Z changes since v33 1. ensure flag C is always calculated as one bit 2. calculate flag Z as one bit, without using inverse

[PATCH v34 12/13] target/avr: Register AVR support with the rest of QEMU, the build system, and the WMAINTAINERS file

Signed-off-by: Michael Rolnik --- MAINTAINERS | 9 + arch_init.c | 2 ++ configure | 7 +++ default-configs/avr-softmmu.mak | 5 + include/disas/dis-asm.h | 6 ++ include/sysemu/arch_init.h | 1

[PATCH v34 06/13] target/avr: Add instruction translation - Branch Instructions

This includes: - RJMP, IJMP, EIJMP, JMP - RCALL, ICALL, EICALL, CALL - RET, RETI - CPSE, CP, CPC, CPI - SBRC, SBRS, SBIC, SBIS - BRBC, BRBS Signed-off-by: Michael Rolnik --- target/avr/translate.c | 549 - 1 file changed, 546

[PATCH v34 02/13] target/avr: Add instruction helpers

access instructions are implemented here because some address ranges actually refer to CPU registers. Signed-off-by: Michael Rolnik --- target/avr/helper.c | 354 target/avr/helper.h | 29 2 files changed, 383 insertions(+) create mode 100644

[PATCH v34 01/13] target/avr: Add outward facing interfaces and core CPU logic

This includes: - CPU data structures - object model classes and functions - migration functions - GDB hooks Co-developed-by: Michael Rolnik Co-developed-by: Sarah Harris Signed-off-by: Michael Rolnik Signed-off-by: Sarah Harris Signed-off-by: Michael Rolnik Acked-by: Igor Mammedov --- gdb

[PATCH v34 04/13] target/avr: Add instruction translation - Registers definition

Signed-off-by: Michael Rolnik --- target/avr/translate.c | 132 + 1 file changed, 132 insertions(+) create mode 100644 target/avr/translate.c diff --git a/target/avr/translate.c b/target/avr/translate.c new file mode 100644 index 00..53c9892a60

[PATCH v34 07/13] target/avr: Add instruction translation - Bit and Bit-test Instructions

This includes: - LSR, ROR - ASR - SWAP - SBI, CBI - BST, BLD - BSET, BCLR Signed-off-by: Michael Rolnik --- target/avr/translate.c | 1123 1 file changed, 1123 insertions(+) diff --git a/target/avr/translate.c b/target/avr

[PATCH v34 11/13] target/avr: Add example board configuration

0,0 +1,282 @@ +/* + * QEMU AVR CPU + * + * Copyright (c) 2019 Michael Rolnik + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2.1 of the L

[PATCH v34 05/13] target/avr: Add instruction translation - Arithmetic and Logic Instructions

This includes: - ADD, ADC, ADIW - SBIW, SUB, SUBI, SBC, SBCI - AND, ANDI - OR, ORI, EOR - COM, NEG - INC, DEC - MUL, MULS, MULSU - FMUL, FMULS, FMULSU - DES Signed-off-by: Michael Rolnik --- target/avr/translate.c | 822 + 1 file changed, 822 insertions

[PATCH v34 13/13] target/avr: Add tests

#x27;T' through serial port Signed-off-by: Michael Rolnik Reviewed-by: Philippe Mathieu-Daudé Tested-by: Philippe Mathieu-Daudé Acked-by: Thomas Huth --- tests/Makefile.include | 2 ++ tests/acceptance/machine_avr6.py | 36 tests/boot-serial

[PATCH v34 10/13] target/avr: Add limited support for USART and 16 bit timer peripherals

config UNIMP bool +config AVR_MASK +bool + source macio/Kconfig diff --git a/hw/misc/Makefile.objs b/hw/misc/Makefile.objs index a150680966..946bfc396d 100644 --- a/hw/misc/Makefile.objs +++ b/hw/misc/Makefile.objs @@ -80,3 +80,5 @@ common-obj-$(CONFIG_MSF2) += msf2-sysreg.o common-

[PATCH v34 09/13] target/avr: Add instruction translation - CPU main translation function

Co-developed-by: Richard Henderson Co-developed-by: Michael Rolnik Signed-off-by: Michael Rolnik --- target/avr/translate.c | 234 + 1 file changed, 234 insertions(+) diff --git a/target/avr/translate.c b/target/avr/translate.c index 30ba13bdd7

[PATCH v34 08/13] target/avr: Add instruction translation - MCU Control Instructions

This includes: - BREAK - NOP - SLEEP - WDR Signed-off-by: Michael Rolnik --- target/avr/translate.c | 174 + 1 file changed, 174 insertions(+) diff --git a/target/avr/translate.c b/target/avr/translate.c index f2ec2e2d2f..30ba13bdd7

[PATCH v35 03/13] target/avr: Add instruction decoding

This includes: - encoding of all 16 bit instructions - encoding of all 32 bit instructions Signed-off-by: Michael Rolnik --- target/avr/insn.decode | 175 + 1 file changed, 175 insertions(+) create mode 100644 target/avr/insn.decode diff --git a/target

[PATCH v35 04/13] target/avr: Add instruction translation - Registers definition

Signed-off-by: Michael Rolnik --- target/avr/translate.c | 132 + 1 file changed, 132 insertions(+) create mode 100644 target/avr/translate.c diff --git a/target/avr/translate.c b/target/avr/translate.c new file mode 100644 index 00..53c9892a60

[PATCH v35 05/13] target/avr: Add instruction translation - Arithmetic and Logic Instructions

This includes: - ADD, ADC, ADIW - SBIW, SUB, SUBI, SBC, SBCI - AND, ANDI - OR, ORI, EOR - COM, NEG - INC, DEC - MUL, MULS, MULSU - FMUL, FMULS, FMULSU - DES Signed-off-by: Michael Rolnik --- target/avr/translate.c | 822 + 1 file changed, 822 insertions

[PATCH v35 02/13] target/avr: Add instruction helpers

access instructions are implemented here because some address ranges actually refer to CPU registers. Signed-off-by: Michael Rolnik --- target/avr/helper.c | 354 target/avr/helper.h | 29 2 files changed, 383 insertions(+) create mode 100644

[PATCH v35 00/13] QEMU AVR 8 bit cores

#x27;Add instruction translation - CPU main translation funcions' commit changes since v32 1. modify cpu_get_sreg to treat sreg C as other flags, except sreg Z changes since v33 1. ensure flag C is always calculated as one bit 2. calculate flag Z as one bit, without using inverse logi

[PATCH v35 08/13] target/avr: Add instruction translation - MCU Control Instructions

This includes: - BREAK - NOP - SLEEP - WDR Signed-off-by: Michael Rolnik --- target/avr/translate.c | 174 + 1 file changed, 174 insertions(+) diff --git a/target/avr/translate.c b/target/avr/translate.c index f2ec2e2d2f..30ba13bdd7

[PATCH v35 06/13] target/avr: Add instruction translation - Branch Instructions

This includes: - RJMP, IJMP, EIJMP, JMP - RCALL, ICALL, EICALL, CALL - RET, RETI - CPSE, CP, CPC, CPI - SBRC, SBRS, SBIC, SBIS - BRBC, BRBS Signed-off-by: Michael Rolnik --- target/avr/translate.c | 549 - 1 file changed, 546

[PATCH v35 09/13] target/avr: Add instruction translation - CPU main translation function

Co-developed-by: Richard Henderson Co-developed-by: Michael Rolnik Signed-off-by: Michael Rolnik --- target/avr/translate.c | 234 + 1 file changed, 234 insertions(+) diff --git a/target/avr/translate.c b/target/avr/translate.c index 30ba13bdd7

[PATCH v35 01/13] target/avr: Add outward facing interfaces and core CPU logic

This includes: - CPU data structures - object model classes and functions - migration functions - GDB hooks Co-developed-by: Michael Rolnik Co-developed-by: Sarah Harris Signed-off-by: Michael Rolnik Signed-off-by: Sarah Harris Signed-off-by: Michael Rolnik Acked-by: Igor Mammedov --- gdb

[PATCH v35 07/13] target/avr: Add instruction translation - Bit and Bit-test Instructions

This includes: - LSR, ROR - ASR - SWAP - SBI, CBI - BST, BLD - BSET, BCLR Signed-off-by: Michael Rolnik --- target/avr/translate.c | 1123 1 file changed, 1123 insertions(+) diff --git a/target/avr/translate.c b/target/avr

[PATCH v35 13/13] target/avr: Add tests

#x27;T' through serial port Signed-off-by: Michael Rolnik Reviewed-by: Philippe Mathieu-Daudé Tested-by: Philippe Mathieu-Daudé Acked-by: Thomas Huth --- tests/Makefile.include | 2 ++ tests/acceptance/machine_avr6.py | 36 tests/boot-serial

[PATCH v35 12/13] target/avr: Register AVR support with the rest of QEMU, the build system, and the WMAINTAINERS file

Signed-off-by: Michael Rolnik --- MAINTAINERS | 9 + arch_init.c | 2 ++ configure | 7 +++ default-configs/avr-softmmu.mak | 5 + include/disas/dis-asm.h | 6 ++ include/sysemu/arch_init.h | 1

[PATCH v35 11/13] target/avr: Add example board configuration

0,0 +1,282 @@ +/* + * QEMU AVR CPU + * + * Copyright (c) 2019 Michael Rolnik + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2.1 of the L

[PATCH v35 10/13] target/avr: Add limited support for USART and 16 bit timer peripherals

config MAC_VIA select MOS6522 select ADB +config AVR_MASK +bool + source macio/Kconfig diff --git a/hw/misc/Makefile.objs b/hw/misc/Makefile.objs index ba898a5781..3a8093be6a 100644 --- a/hw/misc/Makefile.objs +++ b/hw/misc/Makefile.objs @@ -82,3 +82,5 @@ common-obj-$(CONFIG_NRF51_SOC

Re: [PATCH v35 00/13] QEMU AVR 8 bit cores

Hi Aleksandar. I appreciate it. Regards, Michael On Tue, Oct 29, 2019 at 11:43 PM Aleksandar Markovic wrote: > > > > On Tuesday, October 29, 2019, Michael Rolnik wrote: >> >> This series of patches adds 8bit AVR cores to QEMU. > > > Hi Michael, > > I

Re: [PATCH v41 01/21] target/avr: Add outward facing interfaces and core CPU logic

hi all. are there any news / updates about AVR support? On Mon, Mar 23, 2020 at 10:14 PM Michael Rolnik wrote: > thanks Philippe. > > On Mon, Mar 23, 2020 at 9:20 PM Philippe Mathieu-Daudé > wrote: > >> On 3/23/20 7:03 PM, Richard Henderson wrote: >> > On 3/

Re: [PATCH rc3 02/30] target/avr: Introduce AVR CPU class object

Hi all. As for now I have no plans to add support for AVR 32 bit CPU. If there are requests I might consider it. When I started to implement AVR 8 bit CPU I added that `#ifndef CONFIG_USER_ONLY` as other CPUs did, so I guess they could be removed. Regards, Michael Rolnik On Mon, Jan 27, 2020 at

Re: [PATCH rc3 01/30] target/avr: Add basic parameters for new AVR platform

Thanks for you help guys. On Mon, Jan 27, 2020 at 12:55 AM Aleksandar Markovic < aleksandar.marko...@rt-rk.com> wrote: > From: Michael Rolnik > > This includes definitions of various basic parameters needed > for integration of a new platform into QEMU. > > Co-developed-

Re: [PATCH rc2 01/25] target/avr: Add outward facing interfaces and core CPU logic

Hi Joaquin. `AVR_FEATURE_1_BYTE_PC` is used in `gen_push_ret` function (target/avr/translate.c) Regards, Michael Rolnik On Sun, Jan 26, 2020 at 2:15 PM Joaquin de Andres wrote: > Hi! In this mail I only checked the general code and one of the listed > features for the different types

Re: [PATCH rc2 01/25] target/avr: Add outward facing interfaces and core CPU logic

/config/avr/avr-devices.c Have a look here https://github.com/gcc-mirror/gcc/blob/master/gcc/config/avr/avr-mcus.def. you can see that not all xmega support RMW instructions. so whenever QEMU has atxmega128d4 implemented, atxmega128d4 model it will have to remove RMW feature. Regards, Michael Rolnik

Re: [PATCH rc3 01/30] target/avr: Add basic parameters for new AVR platform

Hi all. I am totally lost in the email. Are there any action items for me / someone else ? Regards, Michael Rolnik On Mon, Jan 27, 2020 at 10:54 AM Michael Rolnik wrote: > Thanks for you help guys. > > On Mon, Jan 27, 2020 at 12:55 AM Aleksandar Markovic < > aleksandar.mar

Re: [PATCH rc3 01/30] target/avr: Add basic parameters for new AVR platform

Sounds good to me. On Tue, Jan 28, 2020 at 3:49 PM Aleksandar Markovic < aleksandar.m.m...@gmail.com> wrote: > > > On Tuesday, January 28, 2020, Michael Rolnik wrote: > >> Hi all. >> >> I am totally lost in the email. >> Are there any action i

Re: [PATCH rc3 02/30] target/avr: Introduce AVR CPU class object

Sounds good. Sent from my cell phone, please ignore typos On Wed, Jan 29, 2020, 5:12 PM Aleksandar Markovic < aleksandar.m.m...@gmail.com> wrote: > On Wed, Jan 29, 2020 at 1:20 PM Sarah Harris wrote: > > > > Hi, > > > > I think I've found a minor bug: the stack pointer should be initialised > t

Re: [PATCH rc4 00/29] target/avr merger

ures is nor 64 bit long > >> - Other minor fixes > >> > >> Since v2: > >> > >> - First patch is split into six smaller logical units (net result > >>remains the same) > >> - Patch "hw/core/loader: Let load_elf populate the pro

Re: [PATCH rc4 06/29] target/avr: Add defintions of AVR core types

On Fri, Feb 21, 2020 at 5:31 PM Aleksandar Markovic < aleksandar.m.m...@gmail.com> wrote: > On Fri, Feb 21, 2020 at 12:04 PM Michael Rolnik wrote: > > > > Hi all. > > > > How is it going? > > > > Regards, > > Michael. > > > > Michael

Re: [PATCH v40 00/21] QEMU AVR 8 bit cores

Hi all, any news? Regards, Michael Rolnik On Sun, Dec 29, 2019 at 1:52 PM Michael Rolnik wrote: > This series of patches adds 8bit AVR cores to QEMU. > All instruction, except BREAK/DES/SPM/SPMX, are implemented. Not fully > tested yet. > However I was able to execute simp

[PATCH v39 06/22] target/avr: Add instruction translation - Branch Instructions

This includes: - RJMP, IJMP, EIJMP, JMP - RCALL, ICALL, EICALL, CALL - RET, RETI - CPSE, CP, CPC, CPI - SBRC, SBRS, SBIC, SBIS - BRBC, BRBS Signed-off-by: Michael Rolnik Tested-by: Philippe Mathieu-Daudé --- target/avr/translate.c | 530

[PATCH v39 09/22] target/avr: Add instruction translation - MCU Control Instructions

This includes: - BREAK - NOP - SLEEP - WDR Signed-off-by: Michael Rolnik --- target/avr/translate.c | 68 ++ 1 file changed, 68 insertions(+) diff --git a/target/avr/translate.c b/target/avr/translate.c index e303a1f4cc..46cbcc9305 100644

[PATCH v39 08/22] target/avr: Add instruction translation - Bit and Bit-test Instructions

This includes: - LSR, ROR - ASR - SWAP - SBI, CBI - BST, BLD - BSET, BCLR Signed-off-by: Michael Rolnik --- target/avr/translate.c | 235 + 1 file changed, 235 insertions(+) diff --git a/target/avr/translate.c b/target/avr

[PATCH v39 13/22] target/avr: Add limited support for 16 bit timer peripheral

These were designed to facilitate testing but should provide enough function to be useful in other contexts. Only a subset of the functions of each peripheral is implemented, mainly due to the lack of a standard way to handle electrical connections (like GPIO pins). Signed-off-by: Sarah Harris

[PATCH v39 17/22] target/avr: Register AVR support with the rest of QEMU

Add AVR related definitions into QEMU Signed-off-by: Michael Rolnik Tested-by: Philippe Mathieu-Daudé Reviewed-by: Aleksandar Markovic include/disas/dis-asm.h --- qapi/machine.json | 3 ++- include/disas/dis-asm.h| 19 +++ include/sysemu/arch_init.h | 1

[PATCH v39 10/22] target/avr: Add instruction translation - CPU main translation function

Co-developed-by: Richard Henderson Co-developed-by: Michael Rolnik Signed-off-by: Michael Rolnik Tested-by: Philippe Mathieu-Daudé --- target/avr/translate.c | 234 + 1 file changed, 234 insertions(+) diff --git a/target/avr/translate.c b/target/avr

[PATCH v39 07/22] target/avr: Add instruction translation - Data Transfer Instructions

This includes: - MOV, MOVW - LDI, LDS LDX LDY LDZ - LDDY, LDDZ - STS, STX STY STZ - STDY, STDZ - LPM, LPMX - ELPM, ELPMX - SPM, SPMX - IN, OUT - PUSH, POP - XCH - LAS, LAC LAT Signed-off-by: Michael Rolnik --- target/avr/translate.c | 986

[PATCH v39 12/22] target/avr: Add limited support for USART peripheral

These were designed to facilitate testing but should provide enough function to be useful in other contexts. Only a subset of the functions of each peripheral is implemented, mainly due to the lack of a standard way to handle electrical connections (like GPIO pins). Signed-off-by: Sarah Harris

[PATCH v39 18/22] target/avr: Add machine none test

Signed-off-by: Michael Rolnik Tested-by: Philippe Mathieu-Daudé Reviewed-by: Aleksandar Markovic --- tests/machine-none-test.c | 1 + 1 file changed, 1 insertion(+) diff --git a/tests/machine-none-test.c b/tests/machine-none-test.c index 5953d31755..3e5c74e73e 100644 --- a/tests/machine-none

[PATCH v39 14/22] target/avr: Add dummy mask device

Signed-off-by: Michael Rolnik --- include/hw/misc/avr_mask.h | 47 hw/misc/avr_mask.c | 112 + hw/misc/Kconfig| 3 + hw/misc/Makefile.objs | 2 + 4 files changed, 164 insertions(+) create mode 100644 include/hw

[PATCH v39 11/22] target/avr: Add instruction disassembly function

, r24 0x04c2: RET ... ``` Signed-off-by: Michael Rolnik Suggested-by: Richard Henderson Suggested-by: Philippe Mathieu-Daudé Suggested-by: Aleksandar Markovic Reviewed-by: Philippe Mathieu-Daudé Tested-by: Philippe Mathieu-Daudé --- target/avr/cpu.h | 1 + target/avr/cpu.c

[PATCH v39 20/22] target/avr: Add boot serial test

Print out 'T' through serial port Signed-off-by: Michael Rolnik Reviewed-by: Philippe Mathieu-Daudé Tested-by: Philippe Mathieu-Daudé Acked-by: Thomas Huth --- tests/boot-serial-test.c | 10 ++ tests/Makefile.include | 2 ++ 2 files changed, 12 insertions(+) diff --g

[PATCH v39 19/22] target/avr: Update build system

Make AVR support buildable Signed-off-by: Michael Rolnik Tested-by: Philippe Mathieu-Daudé Reviewed-by: Aleksandar Markovic --- configure | 7 +++ default-configs/avr-softmmu.mak | 5 + target/avr/Makefile.objs| 34 + 3

[PATCH v39 15/22] target/avr: Add example board configuration

data_swab, AddressSpace *as, bool load_rom, symbol_fn_t sym_cb); /** load_elf_ram: diff --git a/hw/avr/sample.c b/hw/avr/sample.c new file mode 100644 index 00..4fdbc17f1c --- /dev/null +++ b/hw/avr/sample.c @@ -0,0 +1,293 @@ +/* + * QEMU AVR CPU + * + * Copyright (c) 2019 Michael Rolnik +

[PATCH v39 21/22] target/avr: Add Avocado test

The test is based on https://github.com/seharris/qemu-avr-tests/tree/master/free-rtos/Demo demo which. If working correctly, prints 'ABCDEFGHIJKLMNOPQRSTUVWX' out. it also demostrates that timer and IRQ are working Signed-off-by: Michael Rolnik Reviewed-by: Philippe Mathieu-Daudé

[PATCH v39 16/22] target/avr: Add section about AVR into QEMU documentation

Signed-off-by: Michael Rolnik --- qemu-doc.texi | 51 +++ 1 file changed, 51 insertions(+) diff --git a/qemu-doc.texi b/qemu-doc.texi index eea91a2d1e..c169ab9357 100644 --- a/qemu-doc.texi +++ b/qemu-doc.texi @@ -1742,6 +1742,7 @@ differences are

[PATCH v39 22/22] target/avr: Update MAINTAINERS file

Include AVR maintaners in MAINTAINERS file Signed-off-by: Michael Rolnik --- MAINTAINERS | 21 + 1 file changed, 21 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 740401bcbb..9ed886106a 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -163,6 +163,27 @@ S

[PATCH v39 01/22] target/avr: Add outward facing interfaces and core CPU logic

This includes: - CPU data structures - object model classes and functions - migration functions - GDB hooks Co-developed-by: Michael Rolnik Co-developed-by: Sarah Harris Signed-off-by: Michael Rolnik Signed-off-by: Sarah Harris Signed-off-by: Michael Rolnik Acked-by: Igor Mammedov Tested-by

[PATCH v39 02/22] target/avr: Add instruction helpers

access instructions are implemented here because some address ranges actually refer to CPU registers. Signed-off-by: Michael Rolnik Tested-by: Philippe Mathieu-Daudé --- target/avr/helper.h | 29 target/avr/helper.c | 347 2 files changed, 376

[PATCH v39 04/22] target/avr: Add instruction translation - Registers definition

Signed-off-by: Michael Rolnik Reviewed-by: Philippe Mathieu-Daudé Tested-by: Philippe Mathieu-Daudé --- target/avr/translate.c | 143 + 1 file changed, 143 insertions(+) create mode 100644 target/avr/translate.c diff --git a/target/avr/translate.c b

[PATCH v39 05/22] target/avr: Add instruction translation - Arithmetic and Logic Instructions

This includes: - ADD, ADC, ADIW - SBIW, SUB, SUBI, SBC, SBCI - AND, ANDI - OR, ORI, EOR - COM, NEG - INC, DEC - MUL, MULS, MULSU - FMUL, FMULS, FMULSU - DES Signed-off-by: Michael Rolnik Tested-by: Philippe Mathieu-Daudé --- target/avr/translate.c | 714

[PATCH v39 03/22] target/avr: Add instruction decoding

This includes: - encoding of all 16 bit instructions - encoding of all 32 bit instructions Signed-off-by: Michael Rolnik Tested-by: Philippe Mathieu-Daudé --- target/avr/insn.decode | 183 + 1 file changed, 183 insertions(+) create mode 100644 target

[PATCH v39 00/22] QEMU AVR 8 bit cores

ncludes from target/avr/helper.c file 8. remove empty lines from target/avr/translate.c file 9. set number of interrupt lines to 64 10. determine cpu type by reading ELF flags 11. update license of all new files to be LGPL 12. udpate QEMU documentation changes since v38 1. rebase 2. add examples of A

Re: [PATCH v39 15/22] target/avr: Add example board configuration

Hi Igor. I don't find where machine->ram is defined. Regards, Michael Rolnik On Fri, Dec 20, 2019 at 11:51 AM Igor Mammedov wrote: > On Wed, 18 Dec 2019 23:03:22 +0200 > Michael Rolnik wrote: > > > A simple board setup that configures an AVR CPU to run a given firmwa

Re: [PATCH v39 03/22] target/avr: Add instruction decoding

Hi Aleksandar. please explain. On Sat, Dec 21, 2019 at 1:18 PM Aleksandar Markovic < aleksandar.m.m...@gmail.com> wrote: > > > On Wednesday, December 18, 2019, Michael Rolnik wrote: > >> This includes: >> - encoding of all 16 bit instructions >> -

Re: [PATCH v39 00/22] QEMU AVR 8 bit cores

Hi Aleksandar. FreeRTOS demo we use uses avr6, that's why we use avr6. Regards. Michael Rolnik On Mon, Dec 23, 2019 at 11:13 AM Aleksandar Markovic < aleksandar.m.m...@gmail.com> wrote: > > > On Wednesday, December 18, 2019, Michael Rolnik wrote: > >> This se

Re: [PATCH v39 14/22] target/avr: Add dummy mask device

...@gmail.com> wrote: > > > On Wednesday, December 18, 2019, Michael Rolnik wrote: > >> Signed-off-by: Michael Rolnik >> --- > > > Hi, Michael. > > Please avoid empty commit messages. > > At the very beginning, there is a line: > > + * AVR Powe

Re: [PATCH v39 03/22] target/avr: Add instruction decoding

ndar.m.m...@gmail.com> wrote: > >> >> >> On Saturday, December 21, 2019, Michael Rolnik wrote: >> >>> Hi Aleksandar. >>> >>> please explain. >>> >>>> >>>> >> Hi, Michael. >> >> I wanted to say: &g

Re: [PATCH v39 00/22] QEMU AVR 8 bit cores

but this is a sample board that has some ATmega2560 devices and its avr6 core On Sat, Dec 28, 2019 at 9:38 PM Aleksandar Markovic < aleksandar.m.m...@gmail.com> wrote: > > > On Saturday, December 28, 2019, Michael Rolnik wrote: > >> Hi Aleksandar. >> >> Fr

[PATCH v40 00/21] QEMU AVR 8 bit cores

s of AVR emulator invokation into the QEMU doc 3. reorder instructions to match AVR documentation 4. fix elf loader function bug introduced by prev version changes since v39 1. rename target/avr to hw/avr for hw related commits 2. spread instruction decoding commit 3. add frequency parameter to AVR

[PATCH v40 06/21] target/avr: Add instruction translation - Data Transfer Instructions

This includes: - MOV, MOVW - LDI, LDS LDX LDY LDZ - LDDY, LDDZ - STS, STX STY STZ - STDY, STDZ - LPM, LPMX - ELPM, ELPMX - SPM, SPMX - IN, OUT - PUSH, POP - XCH - LAS, LAC LAT Signed-off-by: Michael Rolnik --- target/avr/translate.c | 986

[PATCH v40 03/21] target/avr: Add instruction translation - Registers definition

Signed-off-by: Michael Rolnik Reviewed-by: Philippe Mathieu-Daudé Tested-by: Philippe Mathieu-Daudé --- target/avr/translate.c | 172 + 1 file changed, 172 insertions(+) create mode 100644 target/avr/translate.c diff --git a/target/avr/translate.c b

[PATCH v40 02/21] target/avr: Add instruction helpers

access instructions are implemented here because some address ranges actually refer to CPU registers. Signed-off-by: Michael Rolnik Tested-by: Philippe Mathieu-Daudé --- target/avr/helper.h | 29 target/avr/helper.c | 347 2 files changed, 376

[PATCH v40 01/21] target/avr: Add outward facing interfaces and core CPU logic

This includes: - CPU data structures - object model classes and functions - migration functions - GDB hooks Co-developed-by: Michael Rolnik Co-developed-by: Sarah Harris Signed-off-by: Michael Rolnik Signed-off-by: Sarah Harris Signed-off-by: Michael Rolnik Acked-by: Igor Mammedov Tested-by

[PATCH v40 04/21] target/avr: Add instruction translation - Arithmetic and Logic Instructions

This includes: - ADD, ADC, ADIW - SBIW, SUB, SUBI, SBC, SBCI - AND, ANDI - OR, ORI, EOR - COM, NEG - INC, DEC - MUL, MULS, MULSU - FMUL, FMULS, FMULSU - DES Signed-off-by: Michael Rolnik Tested-by: Philippe Mathieu-Daudé --- target/avr/translate.c | 751

[PATCH v40 07/21] target/avr: Add instruction translation - Bit and Bit-test Instructions

This includes: - LSR, ROR - ASR - SWAP - SBI, CBI - BST, BLD - BSET, BCLR Signed-off-by: Michael Rolnik --- target/avr/translate.c | 241 + target/avr/insn.decode | 14 +++ 2 files changed, 255 insertions(+) diff --git a/target

[PATCH v40 10/21] target/avr: Add instruction disassembly function

, r24 0x04c2: RET ... ``` Signed-off-by: Michael Rolnik Suggested-by: Richard Henderson Suggested-by: Philippe Mathieu-Daudé Suggested-by: Aleksandar Markovic Reviewed-by: Philippe Mathieu-Daudé Tested-by: Philippe Mathieu-Daudé --- target/avr/cpu.h | 1 + target/avr/cpu.c

[PATCH v40 09/21] target/avr: Add instruction translation - CPU main translation function

Co-developed-by: Richard Henderson Co-developed-by: Michael Rolnik Signed-off-by: Michael Rolnik Tested-by: Philippe Mathieu-Daudé --- target/avr/translate.c | 234 + 1 file changed, 234 insertions(+) diff --git a/target/avr/translate.c b/target/avr

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