ate target frequency: 12500 Hz
Signed-off-by: Edgar E. Iglesias
Reviewed-by: Luc Michel
---
hw/arm/xlnx-versal-virt.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/arm/xlnx-versal-virt.c b/hw/arm/xlnx-versal-virt.c
index 4b3152ee77..43d74b850f 100644
--- a/hw/arm/x
to a fixed set of colors.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Luc Michel
---
include/hw/misc/led.h | 84 +
hw/misc/led.c | 142 ++
MAINTAINERS | 6 ++
hw/misc/Kconfig | 3 +
hw
GpioPolarity gpio_polarity,
You could go with a boolean here also and name the parameter
gpio_active_low, but I don't have a strong opinion on this.
So with or without those modifications:
Reviewed-by: Luc Michel
LEDColor color,
On 9/10/20 10:54 PM, Philippe Mathieu-Daudé wrote:
Track the LED intensity, and emit a trace event when it changes.
Reviewed-by: Richard Henderson
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Luc Michel
---
hw/misc/led.c| 4
hw/misc/trace-events | 1 +
2 files
hieu-Daudé
Reviewed-by: Luc Michel
---
hw/arm/tosa.c | 40 +++-
hw/arm/Kconfig | 1 +
2 files changed, 16 insertions(+), 25 deletions(-)
diff --git a/hw/arm/tosa.c b/hw/arm/tosa.c
index 90eef1f14dd..f23651fd775 100644
--- a/hw/arm/tosa.c
+++ b/hw/
ed_change_intensity LED desc:'front-power-3' color:green
intensity 0% -> 100%
We notice the front-power LED starts to blink at a ~2Hz rate.
Reviewed-by: Richard Henderson
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Luc Michel
---
hw/arm/aspeed.c | 20 +
Hi Phil,
On 9/10/20 10:54 PM, Philippe Mathieu-Daudé wrote:
Per the 'ARM MPS2 and MPS2+ FPGA Prototyping Boards Technical
Reference Manual' (100112_0200_07_en):
2.1 Overview of the MPS2 and MPS2+ hardware
The MPS2 and MPS2+ FPGA Prototyping Boards contain the
following comp
On 9/10/20 10:54 PM, Philippe Mathieu-Daudé wrote:
Per the 'ARM MPS2 and MPS2+ FPGA Prototyping Boards Technical
Reference Manual' (100112_0200_07_en):
2.1 Overview of the MPS2 and MPS2+ hardware
The MPS2 and MPS2+ FPGA Prototyping Boards contain the
following components and
the
GPIO (which can be inverted).
Declare the GpioPolarity type to model the polarity.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Luc Michel
---
include/hw/misc/led.h | 10 ++
include/hw/qdev-core.h | 16
hw/misc/led.c | 17 -
3
places the 'mps2_scc_leds' trace events by the generic
'led_set_intensity' event.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
Reviewed-by: Luc Michel
---
include/hw/misc/mps2-scc.h | 2 ++
hw/misc/mps2-scc.c | 27 ---
h
places the 'mps2_fpgaio_leds' trace events by the generic
'led_set_intensity' event.
Reviewed-by: Richard Henderson
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Luc Michel
---
include/hw/misc/mps2-fpgaio.h | 2 ++
hw/misc/mps2-fpgaio.c | 23 +++
will trigger an update of
the PLL and all its channels, while a write to an a2w_ctrl channel
register will update the required channel only.
Signed-off-by: Luc Michel
---
include/hw/misc/bcm2835_cprman.h | 44 ++
include/hw/misc/bcm2835_cprman_internals.h | 146
Signed-off-by: Luc Michel
---
include/hw/clock.h | 5 +
1 file changed, 5 insertions(+)
diff --git a/include/hw/clock.h b/include/hw/clock.h
index d357594df9..c93e6113cd 100644
--- a/include/hw/clock.h
+++ b/include/hw/clock.h
@@ -79,10 +79,15 @@ struct Clock {
extern const
pwm 00 0
hsm 00 0
It shows small differences with real hardware due other missing
peripherals for which the driver turn the clock off (like tsens).
Luc Michel (14):
hw/core/clock: provide the
register
reports which PLL is currently locked. We consider a PLL has being
locked as soon as it is enabled (on real hardware, there is a delay
after turning a PLL on, for it to stabilise).
Signed-off-by: Luc Michel
---
include/hw/misc/bcm2835_cprman_internals.h | 8 +++
hw/misc/bcm2835_cprman.c
tween 500MHz+ and 1GHz will be displayed as
1ns. Beyond 1GHz, it will show up as 0ns.
Replace nanosecond periods traces with frequencies in the Hz unit
to have more dynamic range in the trace output.
Signed-off-by: Luc Michel
---
hw/core/clock.c | 6 +++---
hw/core/trace-events | 4 ++--
2
oscillator (xosc) from
which all the clocks will be derived.
Signed-off-by: Luc Michel
---
include/hw/arm/bcm2835_peripherals.h | 3 +-
include/hw/misc/bcm2835_cprman.h | 37 +
include/hw/misc/bcm2835_cprman_internals.h | 24 +++
hw/arm/bcm2835_peripherals.c | 11
A clock mux can be configured to select one of its 10 sources through
the cm_ctl register. It also embeds yet another clock divider, composed
of an integer part and a fractionnal part. The number of bits of each
part is mux dependant.
Signed-off-by: Luc Michel
---
hw/misc/bcm2835_cprman.c | 43
This simple mux sits between the PLL channels and the DSI0E and DSI0P
clock muxes. This mux selects between PLLA-DSI0 and PLLD-DSI0 channel
and outputs the selected signal to source number 4 of DSI0E/P clock
muxes. It is controlled by the cm_dsi0hsck register.
Signed-off-by: Luc Michel
reg = <0x7e101000 0x2000>;
[...]
};
Signed-off-by: Luc Michel
---
include/hw/arm/bcm2835_peripherals.h | 2 +-
include/hw/arm/raspi_platform.h | 5 ++---
hw/arm/bcm2835_peripherals.c | 4 ++--
3 files changed, 5 insertions(+), 6 deletions(-)
diff --git a/include/hw/arm/bcm2835
Add a clock input to the PL011 UART so we can compute the current baud
rate and trace it. This is intended for developers who wish to use QEMU
to e.g. debug their firmware or to figure out the baud rate configured
by an unknown/closed source binary.
Signed-off-by: Luc Michel
---
include/hw/char
A PLL channel is able to further divide the generated PLL frequency. The
divider is given in the ctrl_a2w register. Some channels have a
additional fixed divider which is always applied to the signal.
Signed-off-by: Luc Michel
---
hw/misc/bcm2835_cprman.c | 33
has 6 registers : cm, a2w_ctrl, a2w_ana[0,1,2,3], a2w_frac. A
write to any of them triggers a call to the (not yet implemented)
pll_update function. If the main oscillator changes frequency, an update
is also triggered.
Signed-off-by: Luc Michel
---
include/hw/misc/bcm2835_cprman.h
Connect the 'uart-out' clock from the cprman to the PL011 instance.
Signed-off-by: Luc Michel
---
hw/arm/bcm2835_peripherals.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/hw/arm/bcm2835_peripherals.c b/hw/arm/bcm2835_peripherals.c
index 958aadeeb9..9e4e85c3ad 100644
--
t is exported by the cprman at the qdev level,
adding the suffix '-out' to the mux name to form the output clock name.
(E.g. the 'uart' mux sees its output exported as 'uart-out' at the
cprman level.)
Signed-off-by: Luc Michel
---
include/hw/misc/bcm2
wn and left to 0 which implies a
disabled output.
Once booted in QEMU, the final clock tree is very similar to the one
visible on real hardware. The differences come from some unimplemented
devices for which the driver simply disable the corresponding clock.
Signed-off-by: Lu
Hi Philippe,
On 11:08 Sun 27 Sep , Philippe Mathieu-Daudé wrote:
> Introduce freq_to_str() to convert frequency values in human
> friendly units using the SI units for Hertz.
>
> Signed-off-by: Philippe Mathieu-Daudé
> ---
> include/qemu/cutils.h | 12
> util/cutils.c |
dev: xilinx,zynq_slcr, id ""
> clock-in "ps_clk" freq_hz=33.3 MHz
> mmio f800/1000
>
> Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Luc Michel
> ---
> qdev-monitor.c | 8 +---
> 1 file changed, 5 insertions(+), 3 d
e Mathieu-Daudé
Reviewed-by: Luc Michel
> ---
> hw/core/qdev-clock.c | 11 +++
> 1 file changed, 11 insertions(+)
>
> diff --git a/hw/core/qdev-clock.c b/hw/core/qdev-clock.c
> index 47ecb5b4fae..33bd4a9d520 100644
> --- a/hw/core/qdev-clock.c
> +++
On 23:05 Sat 26 Sep , Philippe Mathieu-Daudé wrote:
> On 9/25/20 12:17 PM, Luc Michel wrote:
> > The BCM2835 cprman is the clock manager of the SoC. It is composed of a
>
> Can we use CPRMAN in caps?
>
> > main oscillator, and several sub-components (PLLs, multiplexe
ned-off-by: Philippe Mathieu-Daudé
Reviewed-by: Luc Michel
---
include/hw/arm/bcm2835_peripherals.h | 2 ++
hw/arm/bcm2835_peripherals.c | 2 ++
2 files changed, 4 insertions(+)
diff --git a/include/hw/arm/bcm2835_peripherals.h
b/include/hw/arm/bcm2835_peripherals.h
index b4d3ae121ac
).
Document various blocks we might use later.
Reviewed-by: Alex Bennée
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Luc Michel
---
include/hw/arm/raspi_platform.h | 51 +++--
1 file changed, 43 insertions(+), 8 deletions(-)
diff --git a/include/hw/arm
Hi Phil,
On 9/21/20 5:52 AM, Philippe Mathieu-Daudé wrote:
This peripheral has 1 free-running timer and 4 compare registers.
Only the free-running timer is implemented. Add support the
COMPARE registers (each register is wired to an IRQ).
Reference: "BCM2835 ARM Peripherals" datasheet [*]
On 9/21/20 5:52 AM, Philippe Mathieu-Daudé wrote:
Use the BCM2835_SYSTIMER_COUNT definition instead of the
magic '4' value.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Luc Michel
---
include/hw/timer/bcm2835_systmr.h | 4 +++-
hw/timer/bcm2835_systmr.c | 3 ++-
On 9/21/20 5:52 AM, Philippe Mathieu-Daudé wrote:
The variable holding the CTRL_STATUS register is misnamed
'status'. Rename it 'ctrl_status' to make it more obvious
this register is also used to control the peripheral.
Signed-off-by: Philippe Mathieu-Daudé
Rev
On 9/21/20 5:52 AM, Philippe Mathieu-Daudé wrote:
Add trace events for GPU and CPU IRQs.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Luc Michel
---
hw/intc/bcm2835_ic.c | 4 +++-
hw/intc/trace-events | 4
2 files changed, 7 insertions(+), 1 deletion(-)
diff --git a/hw
(revision 1.1)
raspi3 Raspberry Pi 3B (revision 1.2)
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Luc Michel
---
hw/arm/raspi.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/hw/arm/raspi.c b/hw/arm/raspi.c
index 811eaf52ff5..46d9ed7f054 100644
On 9/21/20 9:56 AM, Philippe Mathieu-Daudé wrote:
The arm_boot_info structure belong to the machine,
move it to RaspiMachineState.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Luc Michel
---
hw/arm/raspi.c | 30 +++---
1 file changed, 15 insertions(+), 15
eviewed-by: Luc Michel
---
hw/arm/raspi.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/hw/arm/raspi.c b/hw/arm/raspi.c
index 46d9ed7f054..8716a80a75e 100644
--- a/hw/arm/raspi.c
+++ b/hw/arm/raspi.c
@@ -205,6 +205,7 @@ static void reset_secondary(ARMCPU *cpu, co
On 9/21/20 5:52 AM, Philippe Mathieu-Daudé wrote:
The SYS_timer is not directly wired to the ARM core, but to the
SoC (peripheral) interrupt controller.
Fixes: 0e5bbd74064 ("hw/arm/bcm2835_peripherals: Use the SYS_timer")
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by:
Hi Phil,
Just two small typos in the commit message.
On 9/21/20 9:56 AM, Philippe Mathieu-Daudé wrote:
The firmware load address depends of the SoC ("processor id") used,
"depends on"
not of the version of the board.
"not on"
Otherwise:
Reviewed-by: Luc Miche
uates to 7).
>
> Note, the biggest input value freq_to_str() can accept is UINT64_MAX,
> which is ~18.446 EHz, less than 1000 EHz.
>
> Reported-by: Eduardo Habkost
> Suggested-by: Peter Maydell
> Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Luc Michel
> ---
> v3
aintenance interrupt line.
>
> Instead, since the GICv3CPUState has a pointer to the CPUState, make
> the dereference at the point where we want to raise the interrupt, to
> avoid an implicit requirement on board code to wire things up in a
> particular order.
>
> Reported-by: Jos
On 18:43 Thu 01 Oct , Philippe Mathieu-Daudé wrote:
> Introduce freq_to_str() to convert frequency values in human
> friendly units using the SI units for Hertz.
>
> Suggested-by: Luc Michel
> Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Luc Michel
> ---
>
On 16:37 Fri 02 Oct , Philippe Mathieu-Daudé wrote:
[snip]
> >>> +struct BCM2835CprmanState {
> >>> +/*< private >*/
> >>> +SysBusDevice parent_obj;
> >>> +
> >>> +/*< public >*/
> >>> +MemoryRegion iomem;
> >>> +
> >>> +uint32_t regs[CPRMAN_NUM_REGS];
> >>> +uint32_t
On 16:51 Fri 02 Oct , Philippe Mathieu-Daudé wrote:
> On 9/26/20 11:40 PM, Philippe Mathieu-Daudé wrote:
> > On 9/25/20 12:17 PM, Luc Michel wrote:
> >> A clock mux can be configured to select one of its 10 sources through
> >> the cm_ctl register. It also embed
On 16:42 Fri 02 Oct , Philippe Mathieu-Daudé wrote:
> On 9/25/20 12:17 PM, Luc Michel wrote:
> > The clock multiplexers are the last clock stage in the cprman. Each mux
> > outputs one clock signal that goes out of the cprman to the SoC
> > peripherals.
> >
> >
On 20:37 Sun 04 Oct , Luc Michel wrote:
> On 16:51 Fri 02 Oct , Philippe Mathieu-Daudé wrote:
> > On 9/26/20 11:40 PM, Philippe Mathieu-Daudé wrote:
> > > On 9/25/20 12:17 PM, Luc Michel wrote:
> > >> A clock mux can be configured to select one of its 10 sou
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Damien Hedde
Signed-off-by: Luc Michel
---
include/hw/clock.h | 5 +
1 file changed, 5 insertions(+)
diff --git a/include/hw/clock.h b/include/hw/clock.h
index d357594df9..c93e6113cd 100644
--- a/include/hw/clock.h
+++ b/include/hw/clock.h
ces with real hardware due other missing
peripherals for which the driver turn the clock off (like tsens).
Luc Michel (15):
hw/core/clock: provide the VMSTATE_ARRAY_CLOCK macro
hw/core/clock: trace clock values in Hz instead of ns
hw/core/clock: add the clock_new helper function
hw/arm/ra
t is exported by the CPRMAN at the qdev level,
adding the suffix '-out' to the mux name to form the output clock name.
(E.g. the 'uart' mux sees its output exported as 'uart-out' at the
CPRMAN level.)
Tested-by: Philippe Mathieu-Daudé
Signed-off-by: Luc Michel
---
ed-by: Philippe Mathieu-Daudé
Signed-off-by: Luc Michel
---
include/hw/clock.h | 26 ++
1 file changed, 26 insertions(+)
diff --git a/include/hw/clock.h b/include/hw/clock.h
index c93e6113cd..a67c4c008b 100644
--- a/include/hw/clock.h
+++ b/include/hw/clock.h
@@ -93,10 +
reg = <0x7e101000 0x2000>;
[...]
};
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Luc Michel
---
include/hw/arm/bcm2835_peripherals.h | 2 +-
include/hw/arm/raspi_platform.h | 5 ++---
hw/arm/bcm2835_peripherals.c | 4 ++--
3 files changed, 5 insertions(+), 6 deletions
Tested-by: Philippe Mathieu-Daudé
Signed-off-by: Luc Michel
---
include/hw/misc/bcm2835_cprman.h | 15 +
include/hw/misc/bcm2835_cprman_internals.h | 6 ++
hw/misc/bcm2835_cprman.c | 74 +-
3 files changed, 94 insertions(+), 1 deletion
will trigger an update of
the PLL and all its channels, while a write to an A2W_CTRL channel
register will update the required channel only.
Reviewed-by: Philippe Mathieu-Daudé
Tested-by: Philippe Mathieu-Daudé
Signed-off-by: Luc Michel
---
include/hw/misc/bcm2835_cprman.h | 44
A clock mux can be configured to select one of its 10 sources through
the CM_CTL register. It also embeds yet another clock divider, composed
of an integer part and a fractional part. The number of bits of each
part is mux dependent.
Tested-by: Philippe Mathieu-Daudé
Signed-off-by: Luc Michel
tween 500MHz+ and 1GHz will be displayed as
1ns. Beyond 1GHz, it will show up as 0ns.
Replace nanosecond periods traces with frequencies in the Hz unit
to have more dynamic range in the trace output.
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Damien Hedde
Signed-off-by: Luc Michel
---
hw
-by: Luc Michel
---
include/hw/char/pl011.h | 1 +
hw/char/pl011.c | 45 +
hw/char/trace-events| 1 +
3 files changed, 47 insertions(+)
diff --git a/include/hw/char/pl011.h b/include/hw/char/pl011.h
index a91ea50e11..33e5e5317b 100644
--- a
oscillator (xosc) from
which all the clocks will be derived.
Reviewed-by: Philippe Mathieu-Daudé
Tested-by: Philippe Mathieu-Daudé
Signed-off-by: Luc Michel
---
include/hw/arm/bcm2835_peripherals.h | 3 +-
include/hw/misc/bcm2835_cprman.h | 37 +
include/hw/misc
wn and left to 0 which implies a
disabled output.
Once booted in QEMU, the final clock tree is very similar to the one
visible on real hardware. The differences come from some unimplemented
devices for which the driver simply disable the corresponding clock.
Tested-by: Philippe Mathieu-Da
Signed-off-by: Luc Michel
---
include/hw/misc/bcm2835_cprman.h | 29 +
include/hw/misc/bcm2835_cprman_internals.h | 144 +
hw/misc/bcm2835_cprman.c | 108
3 files changed, 281 insertions(+)
diff --git a/include/hw/misc
Connect the 'uart-out' clock from the CPRMAN to the PL011 instance.
Signed-off-by: Luc Michel
---
hw/arm/bcm2835_peripherals.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/hw/arm/bcm2835_peripherals.c b/hw/arm/bcm2835_peripherals.c
index 9d6190042d..d8f28b1ae2 100644
--
register
reports which PLL is currently locked. We consider a PLL has being
locked as soon as it is enabled (on real hardware, there is a delay
after turning a PLL on, for it to stabilize).
Reviewed-by: Philippe Mathieu-Daudé
Tested-by: Philippe Mathieu-Daudé
Signed-off-by: Luc Michel
---
include/hw
A PLL channel is able to further divide the generated PLL frequency.
The divider is given in the CTRL_A2W register. Some channels have an
additional fixed divider which is always applied to the signal.
Tested-by: Philippe Mathieu-Daudé
Signed-off-by: Luc Michel
---
hw/misc/bcm2835_cprman.c
esias
Reviewed-by: Luc Michel
---
target/microblaze/op_helper.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/target/microblaze/op_helper.c b/target/microblaze/op_helper.c
index f3b17a95b3..13ac476199 100644
--- a/target/microblaze/op_helper.c
+++ b/target/mi
On 8/28/20 1:39 PM, Edgar E. Iglesias wrote:
From: "Edgar E. Iglesias"
When the CPU has exceptions disabled, avoid unwinding CPU
state and clobbering registers if we're not going to raise
any exception.
Signed-off-by: Edgar E. Iglesias
Reviewed-by: Luc Michel
---
ta
splay a warning when this occurs.
>
> Reviewed-by: Richard Henderson
> Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Luc Michel
> ---
> hw/char/pl011.c | 9 +
> 1 file changed, 9 insertions(+)
>
> diff --git a/hw/char/pl011.c b/hw/char/pl011.c
> in
On 22:08 Wed 19 Feb , Philippe Mathieu-Daudé wrote:
> Introduce 'fifo_depth' and 'fifo_available' local variables
> to better express the 'r' variable use.
>
> Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Luc Michel
> ---
> hw/char/p
On 22:08 Wed 19 Feb , Philippe Mathieu-Daudé wrote:
> Log FIFO use (availability and depth).
>
> Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Luc Michel
> ---
> hw/char/pl011.c | 10 ++
> hw/char/trace-events | 7 ---
> 2 files changed
On 22:08 Wed 19 Feb , Philippe Mathieu-Daudé wrote:
> While we model a 32-elements RX FIFO since the PL011 model was
> introduced in commit 988f2442971 ("hw/char/imx_serial: Implement
> receive FIFO and ageing timer") we only read 1 char at a time!
"the IMX serial m
On 22:08 Wed 19 Feb , Philippe Mathieu-Daudé wrote:
> Defines FIFO_DEPTH and use it, fixing coding style.
>
> Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Luc Michel
> ---
> hw/char/mcf_uart.c | 10 +++---
> 1 file changed, 7 insertions(+), 3 deletions(-)
&g
troduced in commit 20dcee94833 ("MCF5208 emulation"),
> we only read 1 char at a time!
"the MCF UART model"
Reviewed-by: Luc Michel
>
> Have the IOCanReadHandler handler return how many elements are
> available, and use that in the IOReadHandler handler.
>
>
1_can_receive LCR 0x70, RX FIFO used 0/16, can_receive 16 chars
> pl011_can_receive LCR 0x70, RX FIFO used 0/16, can_receive 16 chars
> pl011_read addr 0x018 value 0x0090 reg FR
> pl011_write addr 0x000 value 0x0072 reg DR
>
> Inspired-by: Peter Maydell
> Signed-off
Hi Phil,
On 22:08 Wed 19 Feb , Philippe Mathieu-Daudé wrote:
> We shouldn't receive characters when the full UART or its
> receiver is disabled. However we don't want to break the
> possibly incomplete "my first bare metal assembly program"s,
> so we choose to simply display a warning when thi
patch and the subsequent ones you keep
mentioning the PL011 model while you modify other UARTs. I guess you
mean "the BCM2835 AUX model" here?
In any case:
Reviewed-by: Luc Michel
>
> Have the IOCanReadHandler handler return how many elements are
> available, and use that in th
es: 63242a007a1 ("SH4: Serial controller improvement")
> Signed-off-by: Philippe Mathieu-Daudé
nice one :)
Reviewed-by: Luc Michel
> ---
> hw/char/sh_serial.c | 30 ++
> 1 file changed, 14 insertions(+), 16 deletions(-)
>
> diff --git a/h
Refactor the creation of virtio devices. Use the accessors provided by
the Versal SoC to retrieve the reserved MMIO and IRQ space. Those are
defined in the VersalMap structure.
Signed-off-by: Luc Michel
---
include/hw/arm/xlnx-versal.h | 3 +++
hw/arm/xlnx-versal-virt.c| 31
Refactor the DDR aperture regions creation using the VersalMap
structure. Device creation and FDT node creation are split into two
functions because the later must happen during ARM virtual bootloader
modify_dtb callback.
Signed-off-by: Luc Michel
---
include/hw/arm/xlnx-versal.h | 7 +---
hw
Add the versal_get_num_cpu accessor to the Versal SoC to retrieve the
number of CPUs in the SoC. Use it in the xlnx-versal-virt machine.
Signed-off-by: Luc Michel
---
include/hw/arm/xlnx-versal.h | 1 +
hw/arm/xlnx-versal-virt.c| 7 ---
hw/arm/xlnx-versal.c | 8
3 files
Split the TYPE_XLNX_VERSAL_CRL type into base and concrete classes. This
is in preparation for the versal2 version of the CRL.
Signed-off-by: Luc Michel
---
include/hw/misc/xlnx-versal-crl.h | 31 ++--
hw/misc/xlnx-versal-crl.c | 48 +++
2
Add a note in the DTB section explaining how to dump the generated DTB
using the dumpdtb machine option.
Signed-off-by: Luc Michel
---
docs/system/arm/xlnx-versal-virt.rst | 8 +++-
1 file changed, 7 insertions(+), 1 deletion(-)
diff --git a/docs/system/arm/xlnx-versal-virt.rst
b/docs
on the CRL.
Signed-off-by: Luc Michel
---
hw/arm/xlnx-versal.c | 31 ++-
1 file changed, 30 insertions(+), 1 deletion(-)
diff --git a/hw/arm/xlnx-versal.c b/hw/arm/xlnx-versal.c
index 5151822ad56..796b4911a02 100644
--- a/hw/arm/xlnx-versal.c
+++ b/hw/arm/xlnx
Refactor the USB controller creation using the VersalMap structure.
Note that the connection to the CRL is removed for now and will be
re-added by next commits.
Signed-off-by: Luc Michel
---
include/hw/arm/xlnx-versal.h | 5 ---
hw/arm/xlnx-versal-virt.c| 56
only creates the two clock nodes. The ones from the
xlnx-versal virt machine are renamed with a `old-' prefix and will be
removed once they are not referenced anymore.
Signed-off-by: Luc Michel
---
include/hw/arm/xlnx-versal.h | 12
hw/arm/xlnx-versal-virt.c| 11 +++---
Refactor the GEM ethernet controllers creation using the VersalMap
structure.
Note that the connection to the CRL is removed for now and will be
re-added by next commits.
Signed-off-by: Luc Michel
---
include/hw/arm/xlnx-versal.h | 3 -
hw/arm/xlnx-versal-virt.c| 54 -
hw
Update the list of supported devices in the Versal SoCs.
Signed-off-by: Luc Michel
---
docs/system/arm/xlnx-versal-virt.rst | 7 +--
1 file changed, 5 insertions(+), 2 deletions(-)
diff --git a/docs/system/arm/xlnx-versal-virt.rst
b/docs/system/arm/xlnx-versal-virt.rst
index 2c63fbf519f
Split the xlnx-versal-virt machine type into a base abstract type and a
concrete type. There is no functional change. This is in preparation for
versal2 machine.
Signed-off-by: Luc Michel
---
hw/arm/xlnx-versal-virt.c | 74 +++
1 file changed, 52 insertions
-by: Luc Michel
---
include/hw/arm/xlnx-versal.h | 2 -
hw/arm/xlnx-versal-virt.c| 36 +
hw/arm/xlnx-versal.c | 142 ---
3 files changed, 117 insertions(+), 63 deletions(-)
diff --git a/include/hw/arm/xlnx-versal.h b/include/hw/arm/xlnx
Refactor the XRAM devices creation using the VersalMap structure.
Signed-off-by: Luc Michel
---
include/hw/arm/xlnx-versal.h | 6
hw/arm/xlnx-versal.c | 59 +---
2 files changed, 35 insertions(+), 30 deletions(-)
diff --git a/include/hw/arm/xlnx
Refactor the TRNG device creation using the VersalMap structure.
Signed-off-by: Luc Michel
---
include/hw/arm/xlnx-versal.h | 2 --
hw/arm/xlnx-versal.c | 18 ++
2 files changed, 10 insertions(+), 10 deletions(-)
diff --git a/include/hw/arm/xlnx-versal.h b/include/hw
Split the xlnx-versal device into two classes, a base, abstract class
and the existing concrete one. Introduce a VersalVersion type that will
be used across several device models when versal2 implementation is
added.
This is in preparation for versal2 implementation.
Signed-off-by: Luc Michel
The gem_init_register_masks function was called at init time but it
relies on the num-priority-queues property. Call it at realize time
instead.
Fixes: 4c70e32f05f ("net: cadence_gem: Define access permission for interrupt
registers")
Signed-off-by: Luc Michel
---
hw/net/cadence
Refactor the CRL device creation using the VersalMap structure. The
connections to the RPU CPUs are temporarily removed and will be
reintroduced with next refactoring commits.
Signed-off-by: Luc Michel
---
include/hw/arm/xlnx-versal.h | 3 ---
hw/arm/xlnx-versal.c | 36
almost fully describe the implemented parts of
versal2.
The versal2 eFuse device differs quite a lot from the versal one and is
left as future work.
Signed-off-by: Luc Michel
---
include/hw/arm/xlnx-versal.h | 17 ++-
hw/arm/xlnx-versal.c | 212 ---
2 files
Refactor the BBRAM device creation using the VersalMap structure.
Note that the corresponding FDT node is removed. It does not correspond
to any real node in standard Versal DTBs. No matching drivers exist for
it.
Signed-off-by: Luc Michel
---
include/hw/arm/xlnx-versal.h | 3 +--
hw/arm/xlnx
Remove now unused macros in xlnx-versal.[ch]. Those macros have been
replaced by the VersalMap structure that serves as a central description
for the SoC. The ones still in use in the versal_unimp function are
inlined.
Signed-off-by: Luc Michel
---
include/hw/arm/xlnx-versal.h | 204
Refactor the CFU device creation using the VersalMap structure. All
users of the APB IRQ OR gate have now been converted. The OR gate device
can be dropped.
Signed-off-by: Luc Michel
---
include/hw/arm/xlnx-versal.h | 14 --
hw/arm/xlnx-versal.c | 258
devices. An OR gate is
created to connect the devices to the actual IRQ pin.
Signed-off-by: Luc Michel
---
hw/arm/xlnx-versal.c | 62 +++-
1 file changed, 61 insertions(+), 1 deletion(-)
diff --git a/hw/arm/xlnx-versal.c b/hw/arm/xlnx-versal.c
index
Add the per_cluster_gic switch to the VersalCpuClusterMap structure.
When set, this indicates that a GIC instance should by created
per-cluster instead of globaly for the whole RPU or APU. This is in
preparation for versal2.
Signed-off-by: Luc Michel
---
hw/arm/xlnx-versal.c | 15
Add the versal2 version of the CRL device. For the implemented part, it
is similar to the versal version but drives reset line of more devices.
Signed-off-by: Luc Michel
---
include/hw/arm/xlnx-versal-version.h | 1 +
include/hw/misc/xlnx-versal-crl.h| 329 ++
hw/misc
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