generation.
Signed-off-by: Luc Michel
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Peter Maydell
---
hw/intc/arm_gic.c| 31 +--
hw/intc/trace-events | 12 ++--
2 files changed, 35 insertions(+), 8 deletions(-)
diff --git a/hw/intc/arm_gic.c b/hw
Add the register definitions for the virtual interface of the GICv2.
Signed-off-by: Luc Michel
---
hw/intc/gic_internal.h | 65 ++
1 file changed, 65 insertions(+)
diff --git a/hw/intc/gic_internal.h b/hw/intc/gic_internal.h
index c85427c8e3..1aa888a576
Some functions are now only used in arm_gic.c, put them static. Some of
them where only used by the NVIC implementation and are not used
anymore, so remove them.
Signed-off-by: Luc Michel
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Peter Maydell
---
hw/intc/arm_gic.c | 23
Add support for GICv2 virtualization extensions by mapping the necessary
I/O regions and connecting the maintenance IRQ lines.
Declare those additions in the device tree and in the ACPI tables.
Signed-off-by: Luc Michel
---
hw/arm/virt-acpi-build.c | 4
hw/arm/virt.c| 50
case in gic_clear_pending_sgi() to enhance
code readability as the virtualization extensions support adds a if-else
level.
Signed-off-by: Luc Michel
---
hw/intc/arm_gic.c | 52 ++-
1 file changed, 33 insertions(+), 19 deletions(-)
diff --git a/hw/intc
In preparation for the virtualization extensions implementation,
refactor the name of the functions and macros that act on the GIC
distributor to make that fact explicit. It will be useful to
differentiate them from the ones that will act on the virtual
interfaces.
Signed-off-by: Luc Michel
Provide a VMSTATE_UINT16_SUB_ARRAY macro to save a uint16_t sub-array in
a VMState.
Signed-off-by: Luc Michel
Reviewed-by: Peter Maydell
---
include/migration/vmstate.h | 3 +++
1 file changed, 3 insertions(+)
diff --git a/include/migration/vmstate.h b/include/migration/vmstate.h
index
virtual interface, in h_apr.
Signed-off-by: Luc Michel
---
hw/intc/arm_gic.c | 45 -
1 file changed, 36 insertions(+), 9 deletions(-)
diff --git a/hw/intc/arm_gic.c b/hw/intc/arm_gic.c
index d55a88bb33..d61c2dd557 100644
--- a/hw/intc/arm_gic.c
+++ b/hw
TIVERn and GICD_ICACTIVERn because KVM uses them.
Luc Michel (20):
intc/arm_gic: Implement write to GICD_ISACTIVERn and GICD_ICACTIVERn
registers
intc/arm_gic: Refactor operations on the distributor
intc/arm_gic: Remove some dead code and put some functions static
vmstate.h: Provide VMSTATE_UINT16
effect on the distributor, even in the
vCPU case, when the correponding LR has the HW field set.
Use those functions in the CPU interface code path to prepare for the
vCPU interface implementation.
Signed-off-by: Luc Michel
---
hw/intc/arm_gic.c | 32 -
hw/intc/gic_internal.h
The main difference between CPU and vCPU is the way we select the best
IRQ. This part has been split into the gic_get_best_(v)irq functions.
For the virt case, the LRs are iterated to find the best candidate.
Signed-off-by: Luc Michel
---
hw/intc/arm_gic.c
Implement the read and write functions for the virtual interface of the
virtualization extensions in the GICv2.
Signed-off-by: Luc Michel
---
hw/intc/arm_gic.c | 161 +-
1 file changed, 159 insertions(+), 2 deletions(-)
diff --git a/hw/intc/arm_gic.c
this information.
Signed-off-by: Luc Michel
---
hw/arm/xlnx-zynqmp.c | 92
include/hw/arm/xlnx-zynqmp.h | 4 +-
2 files changed, 86 insertions(+), 10 deletions(-)
diff --git a/hw/arm/xlnx-zynqmp.c b/hw/arm/xlnx-zynqmp.c
index 29df35fb75..42c29b8d06
distributor is not
exposed to vCPUs at all.
Signed-off-by: Luc Michel
---
hw/intc/arm_gic.c | 39 ++-
1 file changed, 22 insertions(+), 17 deletions(-)
diff --git a/hw/intc/arm_gic.c b/hw/intc/arm_gic.c
index f25d1b1270..8ab3025901 100644
--- a/hw/intc/arm_gic
implement
the virtualization extensions, we report an error if the corresponding
property is set to true.
Signed-off-by: Luc Michel
---
hw/intc/arm_gic.c| 2 +-
hw/intc/arm_gic_common.c | 148 ++-
hw/intc/arm_gic_kvm.c| 8 +
On 8/14/18 2:42 PM, Peter Maydell wrote:
> We implement the HAMAIR1 register as RAZ/WI; we had a typo in the
> regdef, though, and were incorrectly naming it HMAIR1 (which is
> a different register which we also implement as RAZ/WI).
>
> Signed-off-by: Peter Maydell
Reviewed
to explicitly set .cp = 15 for the HMAIR1 and
> HAMAIR1 regdefs, which meant they would UNDEF when the guest
> tried to access them under cp15.
>
> Signed-off-by: Peter Maydell
Reviewed-By: Luc Michel
> ---
> A quick grep suggests these are the only ones we got wrong.
> -
On 8/14/18 2:42 PM, Peter Maydell wrote:
> The AArch32 HACTLR2 register maps to bits [63:32] of ACTLR_EL2.
> We implement ACTLR_EL2 as RAZ/WI, so make HACTLR2 also RAZ/WI.
> (We put the regdef next to ACTLR_EL2 as a reminder in case we
> ever make ACTLR_EL2 something other than RAZ/WI).
Putting thi
On 8/14/18 2:42 PM, Peter Maydell wrote:
> Implement the AArch32 HVBAR register; we can do this just by
> making the existing VBAR_EL2 regdefs be STATE_BOTH.
>
> Signed-off-by: Peter Maydell
Reviewed-By: Luc Michel
> ---
> target/arm/helper.c | 4 ++--
> 1 file change
nked_exc_checks() had the
"we"
> correct code in it, but never got there because of the earlier
> "currmode == tgtmode" check. Special case ELR_Hyp.
>
> Signed-off-by: Peter Maydell
Reviewed-By: Luc Michel
> ---
> target/arm/op_helper.c | 22
t; "SUBS PC, LR, #" instruction.
>
> Signed-off-by: Peter Maydell
Reviewed-By: Luc Michel
> ---
> target/arm/translate.c | 31 +--
> 1 file changed, 29 insertions(+), 2 deletions(-)
>
> diff --git a/target/arm/translate.c b/target/ar
On 8/14/18 2:42 PM, Peter Maydell wrote:
> The AArch32 HCR and HCR2 registers alias HCR_EL2
> bits [31:0] and [63:32]; implement them.
>
> Signed-off-by: Peter Maydell
> ---
> target/arm/helper.c | 39 +++
> 1 file changed, 35 insertions(+), 4 deletions(-)
>
ccessors for these. This fixes in passing a bug
> where we weren't implementing the "RES0 from EL3 if EL2 not
> implemented" behaviour for AArch64 FAR_EL2.
>
> Signed-off-by: Peter Maydell
Reviewed-By: Luc Michel
> ---
> target/arm/helper.c | 14 +++
gt; el3_no_el2_cp_reginfo.
>
> Signed-off-by: Peter Maydell
Reviewed-By: Luc Michel
> ---
> target/arm/helper.c | 6 +-
> 1 file changed, 5 insertions(+), 1 deletion(-)
>
> diff --git a/target/arm/helper.c b/target/arm/helper.c
> index d6e98e9d606..80855302089 100644
> -
* new patch: boot kernels in Hyp mode if possible
>
> (I still have the same "guest EL0 segv" issue as for v1
> if I actually enable the EL2 feature on Cortex-A15.)
>
Reviewed-By: Luc Michel
> thanks
> -- PMM
>
> Peter Maydell (6):
> target/arm: Implement
On 8/21/18 3:28 PM, Peter Maydell wrote:
> The GICv2's QEMU interface (sysbus MMIO regions, IRQs,
> etc) is now quite complicated with the addition of the
> virtualization extensions. Add a comment in the header
> file which documents it.
>
> Signed-off-by: Peter Maydell
> ---
> I needed to wri
dell
Reviewed-by: Luc Michel
> ---
> hw/arm/vexpress.c | 4
> 1 file changed, 4 insertions(+)
>
> diff --git a/hw/arm/vexpress.c b/hw/arm/vexpress.c
> index 5bfe2e43487..dc47ed84c20 100644
> --- a/hw/arm/vexpress.c
> +++ b/hw/arm/vexpress.c
> @@ -251,6 +251,10
ng them like that, so
> reduce it.
>
> Signed-off-by: Peter Maydell
Reviewed-By: Luc Michel
> ---
> hw/intc/arm_gic.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/hw/intc/arm_gic.c b/hw/intc/arm_gic.c
> index c1b35fc1ee2..542b4b93eab 1006
dell
Reviewed-by: Luc Michel
> ---
> hw/arm/fsl-imx6ul.c | 4
> 1 file changed, 4 insertions(+)
>
> diff --git a/hw/arm/fsl-imx6ul.c b/hw/arm/fsl-imx6ul.c
> index 258f4706234..4b56bfa8d16 100644
> --- a/hw/arm/fsl-imx6ul.c
> +++ b/hw/arm/fsl-imx6ul.c
> @@ -20
dell
Reviewed-by: Luc Michel
> ---
> hw/arm/fsl-imx7.c | 4
> 1 file changed, 4 insertions(+)
>
> diff --git a/hw/arm/fsl-imx7.c b/hw/arm/fsl-imx7.c
> index d5e26855a55..7663ad68610 100644
> --- a/hw/arm/fsl-imx7.c
> +++ b/hw/arm/fsl-imx7.c
> @@ -209,6 +209,1
flag in code guarded by an ARM_FEATURE_EL3 check,
> but upcoming changes for supporting booting into Hyp mode will
> change that.
>
> Signed-off-by: Peter Maydell
Reviewed-by: Luc Michel
> ---
> hw/arm/vexpress.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
&
he
> CPU has EL2 then enable it on the GIC and wire up the
> virtualization-specific memory regions and the maintenance
> interrupt.
>
> Signed-off-by: Peter Maydell
Reviewed-by: Luc Michel
> ---
> hw/cpu/a15mpcore.c | 31 ---
> 1 file ch
present.
>
> Signed-off-by: Peter Maydell
Reviewed-by: Luc Michel
> ---
> hw/arm/vexpress.c | 56 ---
> 1 file changed, 53 insertions(+), 3 deletions(-)
>
> diff --git a/hw/arm/vexpress.c b/hw/arm/vexpress.c
> index 3631f4de3a4..c
dell
Reviewed-by: Luc Michel
> ---
> hw/arm/highbank.c | 6 ++
> 1 file changed, 6 insertions(+)
>
> diff --git a/hw/arm/highbank.c b/hw/arm/highbank.c
> index 6d42fce2c37..fb9efa02c35 100644
> --- a/hw/arm/highbank.c
> +++ b/hw/arm/highbank.c
> @@ -243,6 +2
On 06/11/2018 03:38 PM, Peter Maydell wrote:
> On 6 June 2018 at 10:30, wrote:
>> From: Luc MICHEL
>>
>> Add the necessary parts of the virtualization extensions state to the
>> GIC state. We choose to increase the size of the CPU interfaces state to
>> add s
From: Luc MICHEL
Add some traces to the ARM GIC to catch register accesses (distributor,
(v)cpu interface and virtual interface), and to take into account
virtualization extensions (print `vcpu` instead of `cpu` when needed).
Also add some virtualization extensions specific traces: LR updating
From: Luc MICHEL
Provide a VMSTATE_UINT16_SUB_ARRAY macro to save a uint16_t sub-array in
a VMState.
Signed-off-by: Luc MICHEL
---
include/migration/vmstate.h | 3 +++
1 file changed, 3 insertions(+)
diff --git a/include/migration/vmstate.h b/include/migration/vmstate.h
index 42b946ce90
From: Luc MICHEL
In preparation for the virtualization extensions implementation,
refactor the name of the functions and macros that act on the GIC
distributor to make that fact explicit. It will be useful to
differentiate them from the ones that will act on the virtual
interfaces.
Signed-off
From: Luc MICHEL
Some functions are now only used in arm_gic.c, put them static. Some of
them where only used by the NVIC implementation and are not used
anymore, so remove them.
Signed-off-by: Luc MICHEL
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Peter Maydell
---
hw/intc/arm_gic.c
From: Luc MICHEL
This patch series add support for the virtualization extensions in the
ARM GICv2 interrupt controller.
The first two commits do some refactoring to prepare for the
implementation. Commits 3 and 4 are the actual implementation. The last
commit updates the ZynqMP implementation
From: Luc MICHEL
This commit improve the way the GIC is realized and connected in the
ZynqMP SoC. The security extensions are enabled only if requested in the
machine state. The same goes for the virtualization extensions.
All the GIC to APU CPU(s) IRQ lines are now connected, including FIQ
From: Luc MICHEL
This commit adds the actual implementation of the GICv2 virtualization
extensions logic.
For the vCPU interfaces, most of the existing CPU interface code is
reused. Calls to macros or functions modifying the distributor state are
replaced with equivalent generic inline
From: Luc MICHEL
Add the necessary parts of the virtualization extensions state to the
GIC state. We choose to increase the size of the CPU interfaces state to
add space for the vCPU interfaces (the GIC_NCPU_VCPU macro). This way,
we'll be able to reuse most of the CPU interface code fo
The cp15, CRn=15, opc1=0, CRm=5, opc2=0 instruction invalidates all the
data cache on the cortex-r5. Implementing it as a NOP.
Signed-off-by: Luc MICHEL
---
target/arm/cpu.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index b357aee778..47687a40c4
}
Taking exception 1 [Undefined Instruction]
...from EL1 to EL1
...with ESR 0x0/0x200
After implementation:
IN:
0x8000: ee0f1f15 mcr 15, 0, r1, cr15, cr5, {0}
0x8004: e320f003 wfi
Luc MICHEL (1):
target/arm: add data cache invalidation cp15 instruction to cortex-r5
in booke206_invalidate_ea_tlb but in my case, Linux
never triggers this code so I was not able to test.
Luc MICHEL (1):
target-ppc: Fix booke206 tlbwe TLB instruction
target/ppc/mmu_helper.c | 23 ++-
1 file changed, 18 insertions(+), 5 deletions(-)
--
2.14.3
When overwritting a valid TLB entry with a new one, the previous page
were not flushed in QEMU TLB, leading to incoherent mapping. This commit
fixes this.
Signed-off-by: Luc MICHEL
---
target/ppc/mmu_helper.c | 23 ++-
1 file changed, 18 insertions(+), 5 deletions(-)
diff
On 2/27/20 4:44 PM, Edgar E. Iglesias wrote:
> From: "Edgar E. Iglesias"
>
> Generate xlnx-versal-virt zdma FDT nodes.
>
> Signed-off-by: Edgar E. Iglesias
Reviewed-by: Luc Michel
> ---
> hw/arm/xlnx-versal-virt.c | 28
&
On 2/27/20 4:44 PM, Edgar E. Iglesias wrote:
> From: "Edgar E. Iglesias"
>
> Add support for the Versal LPD ADMAs.
>
> Signed-off-by: Edgar E. Iglesias
Reviewed-by: Luc Michel
> ---
> hw/arm/xlnx-versal.c | 24
>
On 4/27/20 8:16 PM, Edgar E. Iglesias wrote:
> From: "Edgar E. Iglesias"
>
> Move misplaced comment.
>
> Signed-off-by: Edgar E. Iglesias
Reviewed-by: Luc Michel
> ---
> hw/arm/xlnx-versal.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
>
On 4/27/20 8:16 PM, Edgar E. Iglesias wrote:
> From: "Edgar E. Iglesias"
>
> Fix typo xlnx-ve -> xlnx-versal.
>
> Signed-off-by: Edgar E. Iglesias
Reviewed-by: Luc Michel
> ---
> hw/arm/xlnx-versal-virt.c | 2 +-
> 1 file changed, 1 insertion(+), 1 dele
On 4/27/20 8:16 PM, Edgar E. Iglesias wrote:
> From: "Edgar E. Iglesias"
>
> Add support for SD.
>
> Signed-off-by: Edgar E. Iglesias
Reviewed-by: Luc Michel
> ---
> hw/arm/xlnx-versal-virt.c | 46 +++
> 1 file changed,
On 4/27/20 8:16 PM, Edgar E. Iglesias wrote:
> From: "Edgar E. Iglesias"
>
> Embedd the GEMs into the SoC type.
>
> Suggested-by: Peter Maydell
> Signed-off-by: Edgar E. Iglesias
Reviewed-by: Luc Michel
> ---
> hw/arm/xlnx-versal.c | 15
On 4/27/20 8:16 PM, Edgar E. Iglesias wrote:
> From: "Edgar E. Iglesias"
>
> Remove inclusion of arm_gicv3_common.h, this already gets
> included via xlnx-versal.h.
>
> Signed-off-by: Edgar E. Iglesias
Reviewed-by: Luc Michel
> ---
> hw/arm/xlnx-versal.c |
iff]
orderFile = scripts/git.orderfile
in your QEMU's .git/config. This way header files come first in the patches.
Reviewed-by: Luc Michel
> ---
> hw/arm/xlnx-versal.c | 12 ++--
> include/hw/arm/xlnx-versal.h | 3 ++-
> 2 files changed, 8 insertions(+), 7 deletion
On 4/27/20 8:16 PM, Edgar E. Iglesias wrote:
> From: "Edgar E. Iglesias"
>
> Embedd the APUs into the SoC type.
>
> Suggested-by: Peter Maydell
> Signed-off-by: Edgar E. Iglesias
Reviewed-by: Luc Michel
> ---
> hw/arm/xlnx-versal-virt.c| 4 ++--
&g
On 4/27/20 8:16 PM, Edgar E. Iglesias wrote:
> From: "Edgar E. Iglesias"
>
> Embedd the ADMAs into the SoC type.
>
> Suggested-by: Peter Maydell
> Signed-off-by: Edgar E. Iglesias
Reviewed-by: Luc Michel
> ---
> hw/arm/xlnx-versal.c | 14 +++
On 4/27/20 8:16 PM, Edgar E. Iglesias wrote:
> From: "Edgar E. Iglesias"
>
> hw/arm: versal: Add support for the RTC.
>
> Signed-off-by: Edgar E. Iglesias
Reviewed-by: Luc Michel
> ---
> hw/arm/xlnx-versal.c | 21 +
>
On 4/27/20 8:16 PM, Edgar E. Iglesias wrote:
> From: "Edgar E. Iglesias"
>
> Add support for SD.
>
> Signed-off-by: Edgar E. Iglesias
Reviewed-by: Luc Michel
> ---
> hw/arm/xlnx-versal.c | 31 +++
> include/hw/arm/xl
On 4/27/20 8:16 PM, Edgar E. Iglesias wrote:
> From: "Edgar E. Iglesias"
>
> Add support for the RTC.
>
> Signed-off-by: Edgar E. Iglesias
Reviewed-by: Luc Michel
> ---
> hw/arm/xlnx-versal-virt.c | 22 ++
> 1 file changed, 22 insertion
ned-off-by: Luc Michel
---
RFC because I'm really not sure this is the good place to do that since
EXCP_DEBUG are usually raised in each target translate.c. It could also
have implications with record/replay I'm not aware of.
---
accel/tcg/cpu-exec.c | 11 +++
1 file changed, 11
ned-off-by: Luc Michel
---
v2:
- remove RFC tag
- inline the recursive call to cpu_handle_exception [Richard]
---
accel/tcg/cpu-exec.c | 12
1 file changed, 12 insertions(+)
diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c
index d95c4848a4..59b1b5fe76 100644
--- a/accel/tcg/
On 7/16/20 11:08 PM, Richard Henderson wrote:
> On 7/16/20 1:12 PM, Peter Maydell wrote:
>> On Thu, 16 Jul 2020 at 11:08, Luc Michel wrote:
>>>
>>> When single-stepping with a debugger attached to QEMU, and when an
>>> exception is raised, the debugger mi
-by: Luc Michel
Tested-by: Luc Michel
---
accel/tcg/cpu-exec.c | 8 +++-
1 file changed, 7 insertions(+), 1 deletion(-)
diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c
index 6a3d3a3cfc..66d38f9d85 100644
--- a/accel/tcg/cpu-exec.c
+++ b/accel/tcg/cpu-exec.c
@@ -588,7 +588,13
Hi Philippe,
On 08:23 Fri 09 Apr , Philippe Mathieu-Daudé wrote:
> Hi Damian, Luc, Peter.
>
> I've been debugging some odd issue with the clocks:
> a clock created in the machine (IOW, not a qdev clock) isn't
> always resetted, thus propagating its value.
> "not always" is the odd part. In th
On 3/2/21 12:09 PM, Edgar E. Iglesias wrote:
From: "Edgar E. Iglesias"
Connect the support for the Versal Accelerator RAMs (XRAMs).
Signed-off-by: Edgar E. Iglesias
Reviewed-by: Luc Michel
---
docs/system/arm/xlnx-versal-virt.rst | 1 +
include/hw/arm/xlnx-versal.h
be raised
unless injected.
Signed-off-by: Edgar E. Iglesias
Reviewed-by: Luc Michel
---
include/hw/misc/xlnx-versal-xramc.h | 102 +++
hw/misc/xlnx-versal-xramc.c | 253
hw/misc/meson.build | 1 +
3 files changed, 356
On 15:53 Sat 10 Apr , Philippe Mathieu-Daudé wrote:
> Hi Luc,
>
> On 4/10/21 3:19 PM, Luc Michel wrote:
> > On 08:23 Fri 09 Apr , Philippe Mathieu-Daudé wrote:
> >> I've been debugging some odd issue with the clocks:
> >> a clock created in the
On 10:40 Tue 06 Oct , Philippe Mathieu-Daudé wrote:
> On 10/5/20 9:56 PM, Luc Michel wrote:
> > The clock multiplexers are the last clock stage in the CPRMAN. Each mux
> > outputs one clock signal that goes out of the CPRMAN to the SoC
> > peripherals.
> >
> >
On 13:33 Sat 10 Oct , Luc Michel wrote:
> On 10:40 Tue 06 Oct , Philippe Mathieu-Daudé wrote:
> > On 10/5/20 9:56 PM, Luc Michel wrote:
> > > The clock multiplexers are the last clock stage in the CPRMAN. Each mux
> > > outputs one clock signal that goes o
On 11:04 Tue 06 Oct , Philippe Mathieu-Daudé wrote:
> On 10/5/20 9:56 PM, Luc Michel wrote:
> > A clock mux can be configured to select one of its 10 sources through
> > the CM_CTL register. It also embeds yet another clock divider, composed
> > of an integer part and a
reg = <0x7e101000 0x2000>;
[...]
};
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Luc Michel
---
include/hw/arm/bcm2835_peripherals.h | 2 +-
include/hw/arm/raspi_platform.h | 5 ++---
hw/arm/bcm2835_peripherals.c | 4 ++--
3 files changed, 5 insertions(+), 6 deletions
rdware due other missing
peripherals for which the driver turn the clock off (like tsens).
Luc Michel (15):
hw/core/clock: provide the VMSTATE_ARRAY_CLOCK macro
hw/core/clock: trace clock values in Hz instead of ns
hw/core/clock: add the clock_new helper function
hw/arm/raspi: fix CPRMA
tween 500MHz+ and 1GHz will be displayed as
1ns. Beyond 1GHz, it will show up as 0ns.
Replace nanosecond periods traces with frequencies in the Hz unit
to have more dynamic range in the trace output.
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Damien Hedde
Signed-off-by: Luc Michel
---
hw
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Damien Hedde
Signed-off-by: Luc Michel
---
include/hw/clock.h | 5 +
1 file changed, 5 insertions(+)
diff --git a/include/hw/clock.h b/include/hw/clock.h
index d357594df9..c93e6113cd 100644
--- a/include/hw/clock.h
+++ b/include/hw/clock.h
ed-by: Philippe Mathieu-Daudé
Signed-off-by: Luc Michel
---
include/hw/clock.h | 13 +
hw/core/clock.c| 15 +++
2 files changed, 28 insertions(+)
diff --git a/include/hw/clock.h b/include/hw/clock.h
index c93e6113cd..81bcf3e505 100644
--- a/include/hw/clock.h
+++ b/in
Signed-off-by: Luc Michel
---
include/hw/misc/bcm2835_cprman.h | 29 +
include/hw/misc/bcm2835_cprman_internals.h | 144 +
hw/misc/bcm2835_cprman.c | 108
3 files changed, 281 insertions(+)
diff --git a/include/hw/misc
register
reports which PLL is currently locked. We consider a PLL has being
locked as soon as it is enabled (on real hardware, there is a delay
after turning a PLL on, for it to stabilize).
Reviewed-by: Philippe Mathieu-Daudé
Tested-by: Philippe Mathieu-Daudé
Signed-off-by: Luc Michel
---
include/hw
oscillator (xosc) from
which all the clocks will be derived.
Reviewed-by: Philippe Mathieu-Daudé
Tested-by: Philippe Mathieu-Daudé
Signed-off-by: Luc Michel
---
include/hw/arm/bcm2835_peripherals.h | 3 +-
include/hw/misc/bcm2835_cprman.h | 37 +
include/hw/misc
t is exported by the CPRMAN at the qdev level,
adding the suffix '-out' to the mux name to form the output clock name.
(E.g. the 'uart' mux sees its output exported as 'uart-out' at the
CPRMAN level.)
Tested-by: Philippe Mathieu-Daudé
Reviewed-by: Philippe Mathieu
will trigger an update of
the PLL and all its channels, while a write to an A2W_CTRL channel
register will update the required channel only.
Reviewed-by: Philippe Mathieu-Daudé
Tested-by: Philippe Mathieu-Daudé
Signed-off-by: Luc Michel
---
include/hw/misc/bcm2835_cprman.h | 44
-by: Luc Michel
---
include/hw/char/pl011.h | 1 +
hw/char/pl011.c | 45 +
hw/char/trace-events| 1 +
3 files changed, 47 insertions(+)
diff --git a/include/hw/char/pl011.h b/include/hw/char/pl011.h
index a91ea50e11..33e5e5317b 100644
--- a
A PLL channel is able to further divide the generated PLL frequency.
The divider is given in the CTRL_A2W register. Some channels have an
additional fixed divider which is always applied to the signal.
Tested-by: Philippe Mathieu-Daudé
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Luc
A clock mux can be configured to select one of its 10 sources through
the CM_CTL register. It also embeds yet another clock divider, composed
of an integer part and a fractional part. The number of bits of each
part is mux dependent.
Tested-by: Philippe Mathieu-Daudé
Signed-off-by: Luc Michel
Tested-by: Philippe Mathieu-Daudé
Signed-off-by: Luc Michel
---
include/hw/misc/bcm2835_cprman.h | 15 +
include/hw/misc/bcm2835_cprman_internals.h | 6 ++
hw/misc/bcm2835_cprman.c | 74 +-
3 files changed, 94 insertions(+), 1 deletion
wn and left to 0 which implies a
disabled output.
Once booted in QEMU, the final clock tree is very similar to the one
visible on real hardware. The differences come from some unimplemented
devices for which the driver simply disable the corresponding clock.
Tested-by: Philippe Mathieu-Da
Connect the 'uart-out' clock from the CPRMAN to the PL011 instance.
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Luc Michel
---
hw/arm/bcm2835_peripherals.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/hw/arm/bcm2835_peripherals.c b/hw/arm/bcm2835_peripherals.c
index
On 18:18 Sat 10 Oct , Philippe Mathieu-Daudé wrote:
> On 10/10/20 3:57 PM, Luc Michel wrote:
> > Those reset values have been extracted from a Raspberry Pi 3 model B
> > v1.2, using the 2020-08-20 version of raspios. The dump was done using
> > the debugfs interface of
is get_random() helper with timer specific
> code. Move it back to generic CP0 helpers.
>
> Reviewed-by: Aleksandar Markovic
> Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Luc Michel
> ---
> target/mips/internal.h | 2 +-
> target/mips/cp0_helper.c | 25 +
used since Linux 3.7, commit ee4af5696720
> ("ARM: bcm2835: add system timer").
>
> [*]
> https://www.raspberrypi.org/app/uploads/2012/02/BCM2835-ARM-Peripherals.pdf
>
> Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Luc Michel
> ---
> v4:
> - Fix arithmet
reference count on the aliased clock to
ensure the aliased clock stays alive during the property lifetime, and
to avoid a double-free memory error when the property get deleted.
Signed-off-by: Luc Michel
---
hw/core/qdev-clock.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/hw/core/qdev
reference count on the aliased clock to
ensure the aliased clock stays alive during the property lifetime, and
to avoid a double-free memory error when the property gets deleted.
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Luc Michel
---
hw/core/qdev-clock.c | 8
1 file changed, 8
rag in clock.h from ptimer.h we add the Clock
> type to typedefs.h.
>
> Signed-off-by: Peter Maydell
Reviewed-by: Luc Michel
> ---
> Side note, I forget why we didn't go for 64.32 fixedpoint for the
> Clock too. I kinda feel we might run into the "clocks can
period clock.
>
> Signed-off-by: Peter Maydell
Reviewed-by: Luc Michel
> ---
> docs/devel/clocks.rst | 16
> include/hw/clock.h| 15 +++
> 2 files changed, 31 insertions(+)
>
> diff --git a/docs/devel/clocks.rst b/docs/devel/clocks.rst
> index
27; hw/timer/cmsdk-apb-timer.c
> include/hw/arm/armsse.h include/hw/timer/cmsdk-apb-timer.h
>
> Signed-off-by: Peter Maydell
Reviewed-by: Luc Michel
> ---
> include/hw/arm/armsse.h| 6 +++---
> include/hw/timer/cmsdk-apb-timer.h | 4 ++--
> hw/timer/cmsdk-apb-
> mps2-an521, musca-a, musca-b1.
>
> Signed-off-by: Peter Maydell
Reviewed-by: Luc Michel
> ---
> include/hw/timer/cmsdk-apb-timer.h | 9 +
> hw/timer/cmsdk-apb-timer.c | 7 +--
> 2 files changed, 14 insertions(+), 2 deletions(-)
>
> diff --
; input, which is used only
> for the register and APB bus logic; on the SSE-200 these clocks are
> both connected together.)
>
> This is a migration compatibility break for machines mps2-an385,
> mps2-an386, mps2-an500, mps2-an511, mps2-an505, mps2-an521, musca-a,
> musca-b1.
>
ock once all the users of this
> device have been converted to wire up the Clock.
>
> This is a migration compatibility break for machines mps2-an385,
> mps2-an386, mps2-an500, mps2-an511, mps2-an505, mps2-an521, musca-a,
> musca-b1, lm3s811evb, lm3s6965evb.
>
> Signed-off-by:
ith the
> MAINCLK Clock; once the transition is complete MAINCLK_FRQ will be
> deleted.
>
> Commit created with:
> perl -p -i -e 's/MAINCLK/MAINCLK_FRQ/g' hw/arm/{armsse,mps2-tz,musca}.c
> include/hw/arm/armsse.h
>
> Signed-off-by: Peter Maydell
Reviewed-by: Lu
g,
> dualtimer and other devices, and delete the now-unused convenience
> function.
>
> Signed-off-by: Peter Maydell
Reviewed-by: Luc Michel
> ---
> include/hw/timer/cmsdk-apb-timer.h | 21 -
> hw/arm/mps2.c | 18 --
>
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