On 2/27/20 4:44 PM, Edgar E. Iglesias wrote:
> From: "Edgar E. Iglesias" <edgar.igles...@xilinx.com>
>
> Generate xlnx-versal-virt zdma FDT nodes.
>
> Signed-off-by: Edgar E. Iglesias <edgar.igles...@xilinx.com>
Reviewed-by: Luc Michel <luc.mic...@greensocs.com>
> ---
> hw/arm/xlnx-versal-virt.c | 28 ++++++++++++++++++++++++++++
> 1 file changed, 28 insertions(+)
>
> diff --git a/hw/arm/xlnx-versal-virt.c b/hw/arm/xlnx-versal-virt.c
> index e7f4ca8bf9..878a275140 100644
> --- a/hw/arm/xlnx-versal-virt.c
> +++ b/hw/arm/xlnx-versal-virt.c
> @@ -229,6 +229,33 @@ static void fdt_add_gem_nodes(VersalVirt *s)
> }
> }
>
> +static void fdt_add_zdma_nodes(VersalVirt *s)
> +{
> + const char clocknames[] = "clk_main\0clk_apb";
> + const char compat[] = "xlnx,zynqmp-dma-1.0";
> + int i;
> +
> + for (i = XLNX_VERSAL_NR_ADMAS - 1; i >= 0; i--) {
> + uint64_t addr = MM_ADMA_CH0 + MM_ADMA_CH0_SIZE * i;
> + char *name = g_strdup_printf("/dma@%" PRIx64, addr);
> +
> + qemu_fdt_add_subnode(s->fdt, name);
> +
> + qemu_fdt_setprop_cell(s->fdt, name, "xlnx,bus-width", 64);
> + qemu_fdt_setprop_cells(s->fdt, name, "clocks",
> + s->phandle.clk_25Mhz, s->phandle.clk_25Mhz);
> + qemu_fdt_setprop(s->fdt, name, "clock-names",
> + clocknames, sizeof(clocknames));
> + qemu_fdt_setprop_cells(s->fdt, name, "interrupts",
> + GIC_FDT_IRQ_TYPE_SPI, VERSAL_ADMA_IRQ_0 + i,
> + GIC_FDT_IRQ_FLAGS_LEVEL_HI);
> + qemu_fdt_setprop_sized_cells(s->fdt, name, "reg",
> + 2, addr, 2, 0x1000);
> + qemu_fdt_setprop(s->fdt, name, "compatible", compat, sizeof(compat));
> + g_free(name);
> + }
> +}
> +
> static void fdt_nop_memory_nodes(void *fdt, Error **errp)
> {
> Error *err = NULL;
> @@ -427,6 +454,7 @@ static void versal_virt_init(MachineState *machine)
> fdt_add_uart_nodes(s);
> fdt_add_gic_nodes(s);
> fdt_add_timer_nodes(s);
> + fdt_add_zdma_nodes(s);
> fdt_add_cpu_nodes(s, psci_conduit);
> fdt_add_clk_node(s, "/clk125", 125000000, s->phandle.clk_125Mhz);
> fdt_add_clk_node(s, "/clk25", 25000000, s->phandle.clk_25Mhz);
>
