On 15:28 Fri 14 Jan , Francisco Iglesias wrote:
> Add in the missing includes in the header for being able to build the DMA
> model when reusing it.
>
> Signed-off-by: Francisco Iglesias
> Reviewed-by: Peter Maydell
Reviewed-by: Luc Michel
> ---
> include/hw/d
On 15:28 Fri 14 Jan , Francisco Iglesias wrote:
> Add a model of Versal's PMC SLCR (system-level control registers).
>
> Signed-off-by: Francisco Iglesias
> Signed-off-by: Edgar E. Iglesias
> Reviewed-by: Peter Maydell
Reviewed-by: Luc Michel
> ---
Hi Francisco!
On 15:28 Fri 14 Jan , Francisco Iglesias wrote:
> An option on real hardware when embedding a DMA engine into a peripheral
> is to make the peripheral control the engine through a custom DMA control
> (hardware) interface between the two. Software drivers in this scenario
> confi
ospi_ahb_decoder_cs(s, addr);
> +
> +if (cs >= 0) {
> +for (int i = 0; i < s->num_cs; i++) {
> +qemu_set_irq(s->cs_lines[i], cs != i);
If you re-send a series, indent is off here.
Otherwise:
Reviewed-by: Luc Michel
scenario.
>
> Signed-off-by: Francisco Iglesias
Reviewed-by: Luc Michel
> ---
> include/hw/dma/xlnx_csu_dma.h | 19 +--
> hw/dma/xlnx_csu_dma.c | 17 +
> 2 files changed, 34 insertions(+), 2 deletions(-)
>
> diff --git
On 10:19 Tue 11 Jan , Dr. David Alan Gilbert (git) wrote:
> From: "Dr. David Alan Gilbert"
>
> Add the missing VMSTATE_END_OF_LIST to vmstate_muldiv
>
> Fixes: 99abcbc7600 ("clock: Provide builtin multiplier/divider")
> Signed-off-by: Dr. David
In some cases, cpu->exit_request can be false after handling the
interrupt, leading to another TB being executed instead of returning
to the main loop.
Fix this by returning true unconditionally when in single-step mode.
Fixes: ba3c35d9c4026361fd380b269dc6def9510b7166
Signed-off-by: Luc Mic
On 10:53 Mon 13 Feb , Damien Hedde wrote:
> Also update mailmap
>
> Signed-off-by: Damien Hedde
Reviewed-by: Luc Michel
> ---
> MAINTAINERS | 2 +-
> .mailmap| 1 +
> 2 files changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/MAINTAINERS b/MAI
can probably also get into this state via some odd
> corner cases involving connecting a GDB and then telling it
> to detach from all the vCPUs.
>
> Abstract out the test into a new gdb_attached() function
> which returns true only if there's actually a GDB connecte
y has a flag for handling this kind of
> "option group is setting global state": by setting
> .merge_lists = true;
> we make the machinery merge all the --semihosting-config arguments
> the user passes into a single set of options and call our
> qemu_semihosti
Use the new semihosting_exit_request instead of a call to exit when
handling a semihosted exit syscall.
Signed-off-by: Luc Michel
---
target/mips/tcg/sysemu/mips-semi.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/mips/tcg/sysemu/mips-semi.c
b/target/mips/tcg
In some cases, cpu->exit_request can be false after handling the
interrupt, leading to another TB being executed instead of returning
to the main loop.
Fix this by returning true unconditionally when in single-step mode.
Fixes: ba3c35d9c4026361fd380b269dc6def9510b7166
Signed-off-by: Luc Mic
Use the new semihosting_exit_request instead of a call to exit when
handling a semihosted exit syscall.
Signed-off-by: Luc Michel
---
target/xtensa/xtensa-semi.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/xtensa/xtensa-semi.c b/target/xtensa/xtensa-semi.c
index
because
it does not allow other CPU threads to exit properly, leading to e.g.
at_exit callbacks being called while other CPUs still run. This can lead
to strange bugs, especially in plugins with a registered at_exit function.
Signed-off-by: Luc Michel
---
qapi/run-state.json|
Add the two function qemu_set_exit_status() and qemu_get_exit_status().
Use qemu_get_exit_status() in main instead of 0 as the return value.
This is in preparation for the semihosting exit request implementation.
Signed-off-by: Luc Michel
---
include/sysemu/sysemu.h | 2 ++
softmmu/main.c
semihosting_exit_request is declared G_NORETURN).
All targets are converted to use this new function.
Thanks,
Luc
Luc Michel (7):
softmmu: add qemu_[set|get]_exit_status functions
semihosting: add the semihosting_exit_request function
semihosting/arm-compat-semi: use semihosting_exit_request
Use the new semihosting_exit_request instead of a call to exit when
handling a semihosted exit syscall.
Signed-off-by: Luc Michel
---
target/m68k/m68k-semi.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/target/m68k/m68k-semi.c b/target/m68k/m68k-semi.c
index
Use the new semihosting_exit_request instead of a call to exit when
handling a semihosted exit syscall.
Signed-off-by: Luc Michel
---
semihosting/arm-compat-semi.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/semihosting/arm-compat-semi.c b/semihosting/arm-compat-semi.c
Use the new semihosting_exit_request instead of a call to exit when
handling a semihosted exit syscall.
Signed-off-by: Luc Michel
---
target/nios2/nios2-semi.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/target/nios2/nios2-semi.c b/target/nios2/nios2-semi.c
index
On 16:24 Mon 20 Jun , Luc Michel wrote:
> In some cases, cpu->exit_request can be false after handling the
> interrupt, leading to another TB being executed instead of returning
> to the main loop.
>
> Fix this by returning true unconditionally when in single-ste
On 15:35 Mon 20 Jun , Peter Maydell wrote:
> On Mon, 20 Jun 2022 at 15:25, Luc Michel wrote:
> > This series implements a clean way for semihosted exit syscalls to
> > terminate QEMU with a given return code.
> >
> > Until now, exit syscalls implementation
On 08:59 Mon 20 Jun , Richard Henderson wrote:
> On 6/20/22 07:24, Luc Michel wrote:
> > Hi,
> >
> > This series implements a clean way for semihosted exit syscalls to
> > terminate QEMU with a given return code.
> >
> > Until now, exit syscalls im
On 09:00 Fri 28 Jun , Philippe Mathieu-Daudé wrote:
> Caution: This message originated from an External Source. Use proper caution
> when opening attachments, clicking links, or responding.
>
>
> Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Luc Michel
>
On 09:00 Fri 28 Jun , Philippe Mathieu-Daudé wrote:
> Caution: This message originated from an External Source. Use proper caution
> when opening attachments, clicking links, or responding.
>
>
> "General command" (GEN_CMD, CMD56) is described as:
>
> GEN_CMD is the same as the single blo
On 11:43 Sat 22 Jun , Inès Varhol wrote:
> This commit creates a clock in STM32L4x5 SYSCFG and wires it up to the
> corresponding clock from STM32L4x5 RCC.
>
> Signed-off-by: Inès Varhol
> Reviewed-by: Peter Maydell
> Reviewed-by: Philippe Mathieu-Daudé
Revie
On 11:43 Sat 22 Jun , Inès Varhol wrote:
> For USART, GPIO and SYSCFG devices, check that clock frequency before
> and after enabling the peripheral clock in RCC is correct.
>
> Signed-off-by: Inès Varhol
> Reviewed-by: Peter Maydell
Reviewed-by: Luc Michel
> ---
>
On 18:10 Tue 02 Jul , Philippe Mathieu-Daudé wrote:
> "General command" (GEN_CMD, CMD56) is described as:
>
> GEN_CMD is the same as the single block read or write
> commands (CMD24 or CMD17). The difference is that [...]
> the data block is not a memory payload data but has a
> vendor
uot;trace.h"
>
> @@ -158,6 +160,15 @@ bool clock_set_mul_div(Clock *clk, uint32_t multiplier,
> uint32_t divider)
> return true;
> }
>
> +static void clock_period_prop_get(Object *obj, Visitor *v, const char *name,
> +
On 21:28 Wed 06 Oct , Luc Michel wrote:
> Until now, int was used as the return type for all the ELF
> loader related functions. The returned value is the sum of all loaded
> program headers "MemSize" fields.
>
> Because of the overflow check in elf_ops.h, trying to
On 10:36 Thu 14 Oct , Stefano Garzarella wrote:
> On Wed, Oct 06, 2021 at 09:28:39PM +0200, Luc Michel wrote:
> >Until now, int was used as the return type for all the ELF
> >loader related functions. The returned value is the sum of all loaded
> >program hea
emove this limitation.
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Luc Michel
---
v2:
- Turn load_elf ret local variable to ssize_t [Stefano]
- Add Phil's R-B
---
include/hw/elf_ops.h | 27 ++--
include/hw/loader.h | 60 ++--
h
On 00:20 Fri 01 Apr , Edgar E. Iglesias wrote:
> From: "Edgar E. Iglesias"
>
> Break out header file to allow embedding of the the TTC.
>
> Signed-off-by: Edgar E. Iglesias
Reviewed-by: Luc Michel
> ---
> include/hw/timer/cadence_ttc.h | 54 +
On 00:20 Fri 01 Apr , Edgar E. Iglesias wrote:
> From: "Edgar E. Iglesias"
>
> Connect the 4 TTC timers on the ZynqMP.
>
> Signed-off-by: Edgar E. Iglesias
Reviewed-by: Luc Michel
> ---
> include/hw/arm/xlnx-zynqmp.h | 4
>
Map my old and now invalid work email addresses to my personal one.
Signed-off-by: Luc Michel
---
Please ignore v1 sent with wrong e-mail address.
---
.mailmap | 3 +++
1 file changed, 3 insertions(+)
diff --git a/.mailmap b/.mailmap
index 64ef9f4de6..49f581bafd 100644
--- a/.mailmap
+++ b
On 08:53 Wed 25 Oct , Philippe Mathieu-Daudé wrote:
> "hw/arm/boot.h" is only required on the source file.
>
> Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Luc Michel
> ---
> include/hw/arm/allwinner-a10.h | 1 -
> hw/arm/cubieboard.c
On 08:53 Wed 25 Oct , Philippe Mathieu-Daudé wrote:
> "hw/arm/boot.h" is only required on the source file.
>
> Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Luc Michel
> ---
> include/hw/arm/fsl-imx25.h | 1 -
> hw/arm/imx25_pdk.c | 1 +
> 2 f
On 08:53 Wed 25 Oct , Philippe Mathieu-Daudé wrote:
> "hw/arm/boot.h" is only required on the source file.
>
> Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Luc Michel
> ---
> include/hw/arm/allwinner-r40.h | 1 -
> hw/arm/bananapi_m2u.c
On 08:53 Wed 25 Oct , Philippe Mathieu-Daudé wrote:
> "hw/arm/boot.h" is only required on the source file.
>
> Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Luc Michel
> ---
> include/hw/arm/allwinner-h3.h | 1 -
> hw/arm/orangepi.c | 1 +
>
On 08:53 Wed 25 Oct , Philippe Mathieu-Daudé wrote:
> "hw/arm/boot.h" is only required on the source file.
>
> Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Luc Michel
> ---
> include/hw/arm/fsl-imx6.h | 1 -
> hw/arm/sabrelite.c| 1 +
> 2 f
On 08:53 Wed 25 Oct , Philippe Mathieu-Daudé wrote:
> "hw/arm/boot.h" is only required on the source file.
>
> Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Luc Michel
> ---
> include/hw/arm/fsl-imx31.h | 1 -
> hw/arm/kzm.c | 1 +
> 2 f
On 08:53 Wed 25 Oct , Philippe Mathieu-Daudé wrote:
> "hw/arm/boot.h" is only required on the source file.
>
> Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Luc Michel
> ---
> include/hw/arm/fsl-imx6ul.h | 1 -
> hw/arm/mcimx6ul-evk.c | 1 +
>
On 08:53 Wed 25 Oct , Philippe Mathieu-Daudé wrote:
> "hw/arm/boot.h" is only required on the source file.
>
> Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Luc Michel
> ---
> include/hw/arm/xlnx-versal.h | 1 -
> hw/arm/xlnx-versal-virt.c| 1 +
>
On 08:53 Wed 25 Oct , Philippe Mathieu-Daudé wrote:
> "hw/arm/boot.h" is only required on the source file.
>
> Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Luc Michel
> ---
> include/hw/arm/fsl-imx7.h | 1 -
> hw/arm/mcimx7d-sabre.c| 1 +
> 2 f
On 08:53 Wed 25 Oct , Philippe Mathieu-Daudé wrote:
> "hw/arm/boot.h" is only required on the source file.
>
> Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Luc Michel
> ---
> include/hw/arm/xlnx-zynqmp.h | 1 -
> hw/arm/xlnx-zcu102.c | 1 +
>
Hi,
On 20:13 Wed 13 Dec , Philippe Mathieu-Daudé wrote:
> Caution: This message originated from an External Source. Use proper caution
> when opening attachments, clicking links, or responding.
>
>
> Hi Arnaud,
>
> (Cc'ing Peter and Luc)
>
> On 12/12/23 14:05, Arnaud Minier wrote:
> > Hi
s process works,
> or anything else that developers might need to know about
> how to add documentation.
>
> Make the .hx files refer to this doc file, and clean
> up their header comments to be more accurate for the
> usage in each file and less cut-n-pasted.
>
> Signed-off-by:
Replace register defines with the REG32 macro from registerfields.h in
the Cadence GEM device.
Signed-off-by: Luc Michel
---
hw/net/cadence_gem.c | 527 +--
1 file changed, 261 insertions(+), 266 deletions(-)
diff --git a/hw/net/cadence_gem.c b/hw/net
Use de FIELD macro to describe the TXSTATUS and RXSTATUS register
fields.
Signed-off-by: Luc Michel
---
hw/net/cadence_gem.c | 34 +-
1 file changed, 25 insertions(+), 9 deletions(-)
diff --git a/hw/net/cadence_gem.c b/hw/net/cadence_gem.c
index 5c386adff2
Use de FIELD macro to describe the IRQ related register fields.
Signed-off-by: Luc Michel
---
hw/net/cadence_gem.c | 51 +---
1 file changed, 39 insertions(+), 12 deletions(-)
diff --git a/hw/net/cadence_gem.c b/hw/net/cadence_gem.c
index 0acee1d544
The MDIO access is done only on a write to the PHYMNTNC register. A
subsequent read is used to retrieve the result but does not trigger an
MDIO access by itself.
Refactor the PHY access logic to perform all accesses (MDIO reads and
writes) at PHYMNTNC write time.
Signed-off-by: Luc Michel
The CRC was stored in an unsigned variable in gem_receive. Change it for
a uint32_t to ensure we have the correct variable size here.
Signed-off-by: Luc Michel
---
hw/net/cadence_gem.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/net/cadence_gem.c b/hw/net
Use de FIELD macro to describe the DMACFG register fields.
Signed-off-by: Luc Michel
---
hw/net/cadence_gem.c | 48
1 file changed, 31 insertions(+), 17 deletions(-)
diff --git a/hw/net/cadence_gem.c b/hw/net/cadence_gem.c
index 09f570b6fb
write to the
PHYMNTNC register (as the real hardware does).
Patch 11 fixes a potential bug on hosts where unsigned would not be 32
bits.
Thanks,
--
Luc
Luc Michel (11):
hw/net/cadence_gem: use REG32 macro for register definitions
hw/net/cadence_gem: use FIELD for screening registers
hw/net
Use de FIELD macro to describe the NWCFG register fields.
Signed-off-by: Luc Michel
---
hw/net/cadence_gem.c | 60
1 file changed, 39 insertions(+), 21 deletions(-)
diff --git a/hw/net/cadence_gem.c b/hw/net/cadence_gem.c
index 2864f0940e
Use the FIELD macro to describe the DESCONF6 register fields.
Signed-off-by: Luc Michel
---
hw/net/cadence_gem.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/hw/net/cadence_gem.c b/hw/net/cadence_gem.c
index 6d084a3b31..955a8da134 100644
--- a/hw/net/cadence_gem.c
Use the FIELD macro to describe the NWCTRL register fields.
Signed-off-by: Luc Michel
---
hw/net/cadence_gem.c | 53 +---
1 file changed, 40 insertions(+), 13 deletions(-)
diff --git a/hw/net/cadence_gem.c b/hw/net/cadence_gem.c
index f01c81de97
Describe screening registers fields using the FIELD macros.
Signed-off-by: Luc Michel
---
hw/net/cadence_gem.c | 92 ++--
1 file changed, 47 insertions(+), 45 deletions(-)
diff --git a/hw/net/cadence_gem.c b/hw/net/cadence_gem.c
index 0e5744ecd7
Use the FIELD macro to describe the PHYMNTNC register fields.
Signed-off-by: Luc Michel
---
hw/net/cadence_gem.c | 27 ++-
1 file changed, 14 insertions(+), 13 deletions(-)
diff --git a/hw/net/cadence_gem.c b/hw/net/cadence_gem.c
index 955a8da134..4c5fe10316 100644
On 19:58 Tue 14 Nov , Michael Tokarev wrote:
> Fixes: c755c943aa2e "hw/net/cadence_gem: use REG32 macro for register
> definitions"
> Cc: Luc Michel
> Cc: Peter Maydell
> Signed-off-by: Michael Tokarev
Reviewed-by: Luc Michel
> ---
> hw/net/cadence_gem.c
On 5/4/21 5:34 PM, Lukas Jünger wrote:
Signed-off-by: Lukas Jünger
Reviewed-by: Luc Michel
---
hw/char/sifive_uart.c | 14 +++---
1 file changed, 7 insertions(+), 7 deletions(-)
diff --git a/hw/char/sifive_uart.c b/hw/char/sifive_uart.c
index 3a00ba7f00..cb70374ead 100644
--- a
On 5/4/21 5:34 PM, Lukas Jünger wrote:
Signed-off-by: Lukas Jünger
Reviewed-by: Luc Michel
---
include/hw/char/sifive_uart.h | 6 +--
hw/char/sifive_uart.c | 72 ++-
2 files changed, 65 insertions(+), 13 deletions(-)
diff --git a/include/hw
Public bug reported:
When trying to access ARM GIC CPU registers through a target GDB
connected to QEMU, QEMU crashes with a SIGSEGV.
Reproducible on last master revision (74e1b78 at the time of writing):
$ ./configure --target-list=arm-softmmu --python=python2 --enable-debug
$ make
$ gdb --args
ping
The patchwork link: https://patchwork.ozlabs.org/patch/756408/
Thanks,
--
Luc
On 04/28/2017 02:56 PM, Luc MICHEL wrote:
> This patch adds the cp15, CRn=15, opc1=0, CRm=5, opc2=0 coprocessor
> instruction
> to the cortex-r5. As stated in the TRM, this instruction invalidates
On 11/06/2017 07:16 AM, David Gibson wrote:
> On Thu, Nov 02, 2017 at 11:35:59AM +0100, Luc MICHEL wrote:
>> When overwritting a valid TLB entry with a new one, the previous page
>> were not flushed in QEMU TLB, leading to incoherent mapping. This commit
>> fixes this.
>
v1 is here: https://lists.gnu.org/archive/html/qemu-devel/2017-11/msg00140.html
v2:
- Add a comment with a cite from the "PowerPC e500 Core Family Reference
Manual,
Rev. 1", as advised by David.
Thanks.
Luc MICHEL (1):
target-ppc: Fix booke206 tlbwe TLB instruction
When overwritting a valid TLB entry with a new one, the previous page
were not flushed in QEMU TLB, leading to incoherent mapping. This commit
fixes this.
Signed-off-by: Luc MICHEL
---
target/ppc/mmu_helper.c | 32 +++-
1 file changed, 27 insertions(+), 5 deletions
From: Luc MICHEL
In the GIC, when an IRQ is acknowledged, its state goes from "pending"
to:
- "active" if the corresponding IRQ pin has been de-asserted
- "active and pending" otherwise.
The GICv2 manual states that when a IRQ becomes active (or active and
p
From: Luc MICHEL
Hi,
Here is a patch set for issues I found in the GIC. I found those by
writing unitary tests for the GIC, and compared the result against
real hardware (a Zynq UltraScale+ board with a GICv2).
The first patch prevents the GIC from signaling an IRQ that is in the
"activ
From: Luc MICHEL
When determining the group priority of a group 1 IRQ, if C_CTRL.CBPR is
0, the non-secure BPR value is used. However, this value must be
incremented by one so that it matches the secure world number of
implemented priority bits (NS world has one less priority bit compared
to the
From: Luc MICHEL
When C_CTRL.CBPR is 1, the Non-Secure view of C_BPR is altered:
- A Non-Secure read of C_BPR should return the BPR value plus 1,
saturated to 7,
- A Non-Secure write should be ignored.
Signed-off-by: Luc MICHEL
---
hw/intc/arm_gic.c | 16 +---
1 file changed
From: Luc MICHEL
When there is no active interrupts in the GIC, a read to the C_RPR
register should return the value of the "Idle priority", which is either
the maximum value an IRQ priority field can be set to, or 0xff.
Since the QEMU GIC model implements all the 8 priority bits
On 01/22/2018 04:19 PM, Peter Maydell wrote:
> On 19 January 2018 at 14:57, wrote:
>> From: Luc MICHEL
>>
>> When C_CTRL.CBPR is 1, the Non-Secure view of C_BPR is altered:
>> - A Non-Secure read of C_BPR should return the BPR value plus 1,
>> saturate
On 12/4/18 7:24 PM, Peter Maydell wrote:
> On Tue, 4 Dec 2018 at 18:06, Eduardo Habkost wrote:
>> In either case, I'm still missing a clear description of what a
>> cluster is supposed to represent, exactly (see my previous reply
>> on this thread).
>
> Here's my attempt:
>
> A cluster is a grou
On 12/4/18 7:06 PM, Eduardo Habkost wrote:
> On Mon, Dec 03, 2018 at 03:09:14PM +0100, Luc Michel wrote:
>>
>>
>> On 12/3/18 12:23 PM, Peter Maydell wrote:
>>> On Mon, 3 Dec 2018 at 11:21, Luc Michel wrote:
>>>>
>>>> On 11/30/18 5:52 PM, Pet
On 12/4/18 8:45 PM, Eduardo Habkost wrote:
> On Tue, Dec 04, 2018 at 07:16:39PM +, Peter Maydell wrote:
>> On Tue, 4 Dec 2018 at 19:05, Eduardo Habkost wrote:
>>> On Tue, Dec 04, 2018 at 06:24:19PM +, Peter Maydell wrote:
A cluster is a group of CPUs which are all identical and have
>
On 11/25/18 10:22 PM, Philippe Mathieu-Daudé wrote:
> Hi Luc,
>
> On 23/11/18 10:17, Luc Michel wrote:
>> The gdb_get_cpu_pid() function does the PID lookup for the given CPU. It
>> checks if the CPU is a direct child of a CPU cluster. If it is, the
>> returned PID
by the peer.
This function supports the multiprocess extension thread-id syntax. The
return value specifies if the parsing failed, or if a special case was
encountered (all processes or all threads).
Use them in 'H' and 'T' packets handling to support the multiprocess
extension.
Change the thread info related packets handling to support multiprocess
extension.
Add the CPUs class name in the extra info to help differentiate
them in multiprocess mode.
Signed-off-by: Luc Michel
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Edgar E. Iglesias
---
gdbstub.c | 37
Change the sC packet handling to support the multiprocess extension.
Instead of returning the first thread, we return the first thread of the
current process.
Signed-off-by: Luc Michel
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Alistair Francis
Reviewed-by: Edgar E. Iglesias
Create two separate CPU clusters for APUs and RPUs.
Signed-off-by: Luc Michel
Reviewed-by: Edgar E. Iglesias
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Alistair Francis
---
include/hw/arm/xlnx-zynqmp.h | 3 +++
hw/arm/xlnx-zynqmp.c | 23 +++
2 files changed
hanks the Xilinx's QEMU team who sponsored this work for
their collaboration and their prototype implementation.
Luc Michel (16):
hw/cpu: introduce CPU clusters
gdbstub: introduce GDB processes
gdbstub: add multiprocess support to '?' packets
gdbstub: add multiprocess su
.
Signed-off-by: Luc Michel
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Edgar E. Iglesias
Acked-by: Alistair Francis
---
gdbstub.c | 117 +++---
1 file changed, 102 insertions(+), 15 deletions(-)
diff --git a/gdbstub.c b/gdbstub.c
index
'D' packets are used by GDB to detach from a process. In multiprocess
mode, the PID to detach from is sent in the request.
Signed-off-by: Luc Michel
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Edgar E. Iglesias
Acked-by: Alistair Francis
---
gdbs
Add support for the vAttach packets. In multiprocess mode, GDB sends
them to attach to additional processes.
Signed-off-by: Luc Michel
Reviewed-by: Edgar E. Iglesias
Acked-by: Alistair Francis
Reviewed-by: Philippe Mathieu-Daudé
---
gdbstub.c | 35 +++
1 file
Add support for multiprocess extension in gdb_vm_state_change()
function.
Signed-off-by: Luc Michel
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Edgar E. Iglesias
Acked-by: Alistair Francis
---
gdbstub.c | 15 ---
1 file changed, 12 insertions(+), 3 deletions(-)
diff --git a
Add multiprocess extension support by enabling multiprocess mode when
the peer requests it, and by replying that we actually support it in the
qSupported reply packet.
Signed-off-by: Luc Michel
Reviewed-by: Philippe Mathieu-Daudé
Acked-by: Alistair Francis
Reviewed-by: Edgar E. Iglesias
Signed-off-by: Luc Michel
Acked-by: Alistair Francis
Reviewed-by: Edgar E. Iglesias
---
gdbstub.c | 65 +--
1 file changed, 63 insertions(+), 2 deletions(-)
diff --git a/gdbstub.c b/gdbstub.c
index 2a3aa0f07e..07508c2e6b 100644
--- a/
process PID + 1.
Signed-off-by: Luc Michel
Acked-by: Alistair Francis
Reviewed-by: Edgar E. Iglesias
Reviewed-by: Philippe Mathieu-Daudé
---
gdbstub.c | 96 +++
1 file changed, 96 insertions(+)
diff --git a/gdbstub.c b/gdbstub.c
index
a
parameter, and use a buffer in the process structure to store the
generated description.
It takes the first CPU of the process to generate the description.
Signed-off-by: Luc Michel
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Edgar E. Iglesias
Reviewed-by: Alistair Francis
When a new connection is established, we set the first process to be
attached, and the others detached. The first CPU of the first process
is selected as the current CPU.
Signed-off-by: Luc Michel
Reviewed-by: Alistair Francis
Reviewed-by: Edgar E. Iglesias
Reviewed-by: Philippe Mathieu-Daudé
This commit adds the cpu-cluster type. It aims at gathering CPUs from
the same cluster in a machine.
For now it only has a `cluster-id` property.
Documentation in cluster.h written with the help of Peter Maydell.
Signed-off-by: Luc Michel
Reviewed-by: Alistair Francis
Reviewed-by: Philippe
When gdb_set_stop_cpu() is called with a CPU associated to a process
currently not attached by the GDB client, return without modifying the
stop CPU. Otherwise, GDB gets confused if it receives packets with a
thread-id it does not know about.
Signed-off-by: Luc Michel
Acked-by: Alistair Francis
Add support for the '!' extended mode packet. This is required for the
multiprocess extension.
Signed-off-by: Luc Michel
Reviewed-by: Edgar E. Iglesias
Acked-by: Alistair Francis
---
gdbstub.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/gdbstub.c b/gdbstub.c
index
is also the case when compiled
in user mode, where multi-processes do not make much sense for now.
Signed-off-by: Luc Michel
Acked-by: Alistair Francis
---
gdbstub.c | 76 +++
1 file changed, 76 insertions(+)
diff --git a/gdbstub.c b/gdbstub.c
'D' packets are used by GDB to detach from a process. In multiprocess
mode, the PID to detach from is sent in the request.
Signed-off-by: Luc Michel
Reviewed-by: Philippe Mathieu-Daudé
---
gdbstub.c | 60 ---
1 file changed, 53
Change the thread info related packets handling to support multiprocess
extension.
Add the CPUs class name in the extra info to help differentiate
them in multiprocess mode.
Signed-off-by: Luc Michel
Reviewed-by: Philippe Mathieu-Daudé
---
gdbstub.c | 35 +--
1
Add support for multiprocess extension in gdb_vm_state_change()
function.
Signed-off-by: Luc Michel
Reviewed-by: Philippe Mathieu-Daudé
---
gdbstub.c | 15 ---
1 file changed, 12 insertions(+), 3 deletions(-)
diff --git a/gdbstub.c b/gdbstub.c
index aae3cce01a..decf56c610 100644
Change the sC packet handling to support the multiprocess extension.
Instead of returning the first thread, we return the first thread of the
current process.
Signed-off-by: Luc Michel
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Alistair Francis
---
gdbstub.c | 11 ---
1 file
This commit adds the cpu-cluster type. It aims at gathering CPUs from
the same cluster in a machine.
For now it only has a `cluster-id` property.
Signed-off-by: Luc Michel
Reviewed-by: Alistair Francis
---
include/hw/cpu/cluster.h | 38 ++
hw/cpu/cluster.c | 59
by the peer.
This function supports the multiprocess extension thread-id syntax. The
return value specifies if the parsing failed, or if a special case was
encountered (all processes or all threads).
Use them in 'H' and 'T' packets handling to support the multiprocess
extension.
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