Enable XPA in MIPS32R5-generic and LPA in MIPS64R6-generic.
Signed-off-by: Leon Alrae
---
target-mips/translate_init.c | 15 +--
1 file changed, 9 insertions(+), 6 deletions(-)
diff --git a/target-mips/translate_init.c b/target-mips/translate_init.c
index 05a02eb..836b7bf 100644
MIPS64 (this also fixes the issue
with missing ri/xi masking off)
* take into account CP0_LLAddr_shift (James)
* improve commit message for removing the comments in patch #6 (James)
Leon Alrae (7):
target-mips: correct MFC0 for CP0.EntryLo in MIPS64
target-mips: extend selected CP0 registers to 64
Update tlb->PFN to contain PFN concatenated with PFNX. PFNX is 0 if large
physical address is not supported.
Signed-off-by: Leon Alrae
---
target-mips/op_helper.c | 32 ++--
1 file changed, 26 insertions(+), 6 deletions(-)
diff --git a/target-mips/op_helper.
PABITS are not hardcoded to 36 bits and we do not model 59 PABITS (which is
the architectural limit) in QEMU.
Signed-off-by: Leon Alrae
---
target-mips/translate_init.c | 9 -
1 file changed, 9 deletions(-)
diff --git a/target-mips/translate_init.c b/target-mips/translate_init.c
index
and XI, which were shifted to bits
63:62 by MTC0 to EntryLo0 or EntryLo1. Therefore creating separate
functions for EntryLo0 and EntryLo1.
Signed-off-by: Leon Alrae
---
disas/mips.c| 2 +
target-mips/cpu.h | 1 +
target-mips/translate.c | 224
Hi Hervé,
On 03/06/2015 21:45, Hervé Poussineau wrote:
> This fixes Windows NT 4.0/MIPS, which was always bugchecking with
> IRQL_NOT_LESS_OR_EQUAL.
>
> Signed-off-by: Hervé Poussineau
> ---
> hw/dma/rc4030.c | 14 --
> 1 file changed, 12 insertions(+), 2 deletions(-)
>
> diff --gi
save support
net/dp8393x: correctly reset in_use field
net/dp8393x: fix hardware reset
Leon Alrae (10):
target-mips: move group of functions above gen_load_fpr32()
target-mips: add Config5.FRE support allowing Status.FR=0 emulation
target-mips: add ERETNC instruction and Con
Reviewed-by: Leon Alrae
Signed-off-by: Leon Alrae
---
target-mips/translate.c | 39 +++
target-mips/translate_init.c | 2 +-
2 files changed, 28 insertions(+), 13 deletions(-)
diff --git a/target-mips/translate.c b/target-mips/translate.c
index 8bf08c8
From: Hervé Poussineau
Signed-off-by: Hervé Poussineau
Reviewed-by: Aurelien Jarno
Signed-off-by: Leon Alrae
---
hw/dma/rc4030.c| 115 ++---
hw/mips/mips_jazz.c| 37 ++--
include/hw/mips/mips.h | 4 +-
3 files changed
for this access.
Signed-off-by: Yongbok Kim
Reviewed-by: Leon Alrae
Signed-off-by: Leon Alrae
---
include/exec/exec-all.h | 2 ++
softmmu_template.h | 22 ++
2 files changed, 24 insertions(+)
diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h
index 2f7a4f1
Move the "Tests" group of functions so that gen_load_fpr32() and
gen_store_fpr32() can use generate_exception().
Signed-off-by: Leon Alrae
---
target-mips/translate.c | 118
1 file changed, 58 insertions(+), 60 deletions(-)
diff --gi
From: Hervé Poussineau
Remove now useless device models from other MIPS configurations
We're now compiling 12 files less than before.
Signed-off-by: Hervé Poussineau
Reviewed-by: Aurelien Jarno
Signed-off-by: Leon Alrae
---
default-configs/mips-softmmu.mak | 5 -
default-co
From: Hervé Poussineau
Signed-off-by: Hervé Poussineau
Reviewed-by: Aurelien Jarno
Signed-off-by: Leon Alrae
---
hw/net/dp8393x.c | 114 ++-
1 file changed, 29 insertions(+), 85 deletions(-)
diff --git a/hw/net/dp8393x.c b/hw/net/dp8393x.c
From: Hervé Poussineau
Signed-off-by: Hervé Poussineau
Reviewed-by: Aurelien Jarno
Signed-off-by: Leon Alrae
---
hw/dma/rc4030.c | 112
1 file changed, 16 insertions(+), 96 deletions(-)
diff --git a/hw/dma/rc4030.c b/hw/dma/rc4030.c
ng to manually specifying its size
& location.
Signed-off-by: Paul Burton
Cc: Aurelien Jarno
Cc: Leon Alrae
Reviewed-by: Leon Alrae
Reviewed-by: Aurelien Jarno
Signed-off-by: Leon Alrae
---
hw/mips/mips_malta.c | 15 +--
1 file changed, 9 insertions(+), 6 deletions(-)
diff --git
From: Hervé Poussineau
Signed-off-by: Hervé Poussineau
Reviewed-by: Aurelien Jarno
Signed-off-by: Leon Alrae
---
hw/dma/rc4030.c | 16
1 file changed, 8 insertions(+), 8 deletions(-)
diff --git a/hw/dma/rc4030.c b/hw/dma/rc4030.c
index 96f796b..bf82eed 100644
--- a/hw/dma
Update tlb->PFN to contain PFN concatenated with PFNX. PFNX is 0 if large
physical address is not supported.
Signed-off-by: Leon Alrae
Reviewed-by: Aurelien Jarno
---
target-mips/op_helper.c | 32 ++--
1 file changed, 26 insertions(+), 6 deletions(-)
diff --gi
Instructions
exception.
Config5.UFE: Allows user to write/read Config5.FRE using CTC1/CFC1
instructions.
Enable the feature in MIPS64R6-generic CPU.
Signed-off-by: Leon Alrae
---
target-mips/cpu.h| 13 +-
target-mips/op_helper.c | 34 +
target-mips
ERETNC is identical to ERET except that an ERETNC will not clear the LLbit
that is set by execution of an LL instruction, and thus when placed between
an LL and SC sequence, will never cause the SC to fail.
Presence of ERETNC is denoted by the Config5.LLB.
Signed-off-by: Leon Alrae
Reviewed-by
CP0.EntryLo bits 31:30 have to be cleared.
Signed-off-by: Leon Alrae
Reviewed-by: Aurelien Jarno
---
target-mips/translate.c | 12 ++--
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/target-mips/translate.c b/target-mips/translate.c
index f6ae0d3..2cc5875 100644
--- a
From: Hervé Poussineau
Signed-off-by: Hervé Poussineau
Reviewed-by: Aurelien Jarno
Signed-off-by: Leon Alrae
---
hw/net/dp8393x.c | 12 +---
1 file changed, 1 insertion(+), 11 deletions(-)
diff --git a/hw/net/dp8393x.c b/hw/net/dp8393x.c
index 2297231..093f0cc 100644
--- a/hw/net
From: Hervé Poussineau
Don't write more than the field width, which is always 16 bit.
Fixes network in NetBSD 5.1/arc
Signed-off-by: Hervé Poussineau
Reviewed-by: Aurelien Jarno
Signed-off-by: Leon Alrae
---
hw/net/dp8393x.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff
each data format as format is known in
translation.
To use mmu_idx from cpu_mmu_index() instead of calculating it from hflag.
Removing save_cpu_state() call in translation because it is able to use
cpu_restore_state() on fault as GETRA() is passed.
Signed-off-by: Yongbok Kim
Reviewed-by: Leon Alrae
From: Hervé Poussineau
Remove also unneeded debug logs.
Signed-off-by: Hervé Poussineau
Reviewed-by: Aurelien Jarno
Signed-off-by: Leon Alrae
---
hw/dma/rc4030.c | 81 -
trace-events| 6 +
2 files changed, 22 insertions(+), 65
From: Hervé Poussineau
Signed-off-by: Laurent Vivier
Signed-off-by: Hervé Poussineau
Reviewed-by: Aurelien Jarno
Signed-off-by: Leon Alrae
---
hw/mips/mips_jazz.c| 12 ++--
hw/net/dp8393x.c | 83 ++
include/hw/mips/mips.h | 5
From: Hervé Poussineau
Signed-off-by: Hervé Poussineau
Reviewed-by: Aurelien Jarno
Signed-off-by: Leon Alrae
---
hw/net/dp8393x.c | 80 +---
1 file changed, 41 insertions(+), 39 deletions(-)
diff --git a/hw/net/dp8393x.c b/hw/net/dp8393x.c
From: Hervé Poussineau
Documentation is not clear of what happens when doing a hardware reset,
but firmware expect all registers to be zero unless specified otherwise.
This fixes reboot on MIPS Magnum.
Signed-off-by: Hervé Poussineau
Reviewed-by: Aurelien Jarno
Signed-off-by: Leon Alrae
Enable XPA in MIPS32R5-generic and LPA in MIPS64R6-generic.
Signed-off-by: Leon Alrae
Reviewed-by: Aurelien Jarno
---
target-mips/translate_init.c | 16 ++--
1 file changed, 10 insertions(+), 6 deletions(-)
diff --git a/target-mips/translate_init.c b/target-mips/translate_init.c
From: Hervé Poussineau
Add a new memory region in system address space where DMA address space
definition (the 'translation table') belongs, so we can update on the fly
the DMA address space.
Signed-off-by: Hervé Poussineau
Reviewed-by: Aurelien Jarno
Signed-off-by: Leon Alrae
-
Extend EntryLo0, EntryLo1, LLAddr and TagLo from 32 to 64 bits in MIPS32.
Introduce gen_move_low32() function which moves low 32 bits from 64-bit
temp to GPR; it sign extends 32-bit value on MIPS64 and truncates on
MIPS32.
Signed-off-by: Leon Alrae
Reviewed-by: Aurelien Jarno
---
target-mips
-by: Leon Alrae
---
hw/dma/rc4030.c| 15 -
hw/mips/mips_jazz.c| 6 ++---
hw/net/dp8393x.c | 61 +-
include/hw/mips/mips.h | 10 -
4 files changed, 42 insertions(+), 50 deletions(-)
diff --git a/hw/dma/rc4030.c
PABITS are not hardcoded to 36 bits and we do not model 59 PABITS (which is
the architectural limit) in QEMU.
Signed-off-by: Leon Alrae
Reviewed-by: Aurelien Jarno
---
target-mips/translate_init.c | 9 -
1 file changed, 9 deletions(-)
diff --git a/target-mips/translate_init.c b/target
From: Hervé Poussineau
Signed-off-by: Hervé Poussineau
Reviewed-by: Aurelien Jarno
Signed-off-by: Leon Alrae
---
hw/net/dp8393x.c | 12
1 file changed, 12 insertions(+)
diff --git a/hw/net/dp8393x.c b/hw/net/dp8393x.c
index ef1fb0e..4184045 100644
--- a/hw/net/dp8393x.c
+++ b
and XI, which were shifted to bits
63:62 by MTC0 to EntryLo0 or EntryLo1. Therefore creating separate
functions for EntryLo0 and EntryLo1.
Signed-off-by: Leon Alrae
Reviewed-by: Aurelien Jarno
---
disas/mips.c| 2 +
target-mips/cpu.h | 1 +
target-mips/translate.c | 226
.
Signed-off-by: Leon Alrae
Reviewed-by: Aurelien Jarno
---
target-mips/cpu.h | 27 +--
target-mips/machine.c | 1 +
target-mips/mips-defs.h | 4 ++--
target-mips/op_helper.c | 19 ---
target-mips/translate.c | 3 ++-
5 files changed, 42 insertio
From: Hervé Poussineau
Signed-off-by: Laurent Vivier
Signed-off-by: Hervé Poussineau
Reviewed-by: Aurelien Jarno
Signed-off-by: Leon Alrae
---
hw/mips/mips_jazz.c | 1 +
hw/net/dp8393x.c| 18 ++
2 files changed, 19 insertions(+)
diff --git a/hw/mips/mips_jazz.c b/hw
On 14/09/15 20:21, Aurelien Jarno wrote:
> Note that this patch conflicts with the following one, that we might
> want to merge, even if the whole series is not ready:
>
> https://lists.gnu.org/archive/html/qemu-devel/2015-07/msg01171.html
Indeed, we should merge that patch as well.
Thanks,
Leon
On 06/07/15 07:14, Serge Vakulenko wrote:
> The LFSR algorithm, used for generating random TLB indexes for TLBWR
> instruction,
> was inclined to produce a degenerate sequence in some cases.
> For example, for 16-entry TLB size and Wired=1, it gives: 15, 6, 7, 2,
> 7, 2, 7, 2, 7, 2, 7, 2, 7, 2, 7,
On 15/09/2015 11:58, Aurelien Jarno wrote:
> On 2015-09-14 15:55, Richard Henderson wrote:
>> On 07/10/2015 02:56 AM, Pavel Dovgalyuk wrote:
>>> Pavel Dovgalyuk (11):
>>> softmmu: add helper function to pass through retaddr
>>> softmmu: remove now unused functions
>>> cpu-exec: in
On 28/08/2015 10:08, Pavel Dovgaluk wrote:
>> From: Aurelien Jarno [mailto:aurel...@aurel32.net]
>> On 2015-08-13 14:12, Leon Alrae wrote:
>>> On 10/07/2015 10:57, Pavel Dovgalyuk wrote:
>>>> @@ -2364,14 +2363,12 @@ static void gen_st_cond (DisasContext *ctx,
>
On 16/09/15 06:27, Aurelien Jarno wrote:
> Independently of your patch, I do wonder if we shouldn't change the
> return type of cpu_mips_get_count to int32_t. With your patch, there
> are now 2 calls to this functions, and both cast the value to int32_t.
Yes, I think that will make more sense if t
On 16/09/15 19:14, Richard Henderson wrote:
> On 09/14/2015 05:45 AM, Leon Alrae wrote:
>> -static inline void gen_mfc0_load64 (TCGv arg, target_ulong off)
>> -{
>> -tcg_gen_ld_tl(arg, cpu_env, off);
>> -tcg_gen_ext32s_tl(arg, arg);
>> -}
>> -
>&g
On 18/09/2015 09:24, Daniel P. Berrange wrote:
> On Thu, Sep 17, 2015 at 07:38:53PM +0100, Peter Maydell wrote:
>> On 17 September 2015 at 19:21, Steve Ellcey wrote:
>>>
>>> Following up to my own email. Apparently the reason I get this error is
>>> that I am building with "--disable-tools --disa
icount
Alex Smith (1):
target-mips: Fix RDHWR on CP0.Count
Aurelien Jarno (2):
target-mips: get rid of MIPS_DEBUG
target-mips: get rid of MIPS_DEBUG_SIGN_EXTENSIONS
Leon Alrae (3):
target-mips: fix corner
From: Alex Smith
For RDHWR on the CP0.Count register, env->CP0_Count was being returned.
This value is a delta against the QEMU_CLOCK_VIRTUAL clock, not the
correct current value of CP0.Count. Use cpu_mips_get_count() instead.
Signed-off-by: Alex Smith
Cc: Aurelien Jarno
Cc: Leon Al
stuck in the loop infinitely as we always
generate the same index.
Signed-off-by: Leon Alrae
Reviewed-by: Aurelien Jarno
---
hw/mips/cputimer.c | 9 +++--
1 file changed, 7 insertions(+), 2 deletions(-)
diff --git a/hw/mips/cputimer.c b/hw/mips/cputimer.c
index 1603600..ba9264b 100644
--- a
rs cannot be the zero register, Reserved Instruction exception must be
signalled for this case.
Signed-off-by: Leon Alrae
Reviewed-by: Aurelien Jarno
---
target-mips/translate.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/target-mips/translate.c b/target-mips
: Aurelien Jarno
Reviewed-by: Leon Alrae
[leon.al...@imgtec.com: avoid retranslation in linux-user SC, break lines
which are over 80 chars, remove v3 changelog from the commit message]
Signed-off-by: Leon Alrae
---
target-mips/cpu.h| 24
target-mips/helper.h | 1 +
target-mips
MTC0 on a 64-bit processor should move entire 64-bit GPR content to CP0
register.
Signed-off-by: Leon Alrae
Reviewed-by: Aurelien Jarno
---
target-mips/translate.c | 18 +++---
1 file changed, 7 insertions(+), 11 deletions(-)
diff --git a/target-mips/translate.c b/target-mips
From: Aurelien Jarno
MIPS_DEBUG_SIGN_EXTENSIONS was used sometimes ago to verify that 32-bit
instructions correctly sign extend their results. It's now not need
anymore, remove it.
Cc: Leon Alrae
Signed-off-by: Aurelien Jarno
Reviewed-by: Leon Alrae
Signed-off-by: Leon Alrae
---
t
From: Petar Jovanovic
Instructions recip.{s|d} and rsqrt.{s|d} do not require 64-bit FPU neither
they require any particular mode for its FPU. This patch removes the checks
that may break a program that uses these instructions.
Signed-off-by: Petar Jovanovic
Reviewed-by: Leon Alrae
Signed-off
From: Richard Henderson
We can tidy gen_load_fpr32h, as well as introduce a helper
to cleanup the MACC instructions.
Signed-off-by: Richard Henderson
Reviewed-by: Leon Alrae
Signed-off-by: Leon Alrae
---
target-mips/translate.c | 48 ++--
1 file
, 7, 2, 7, 2...
When replaced with LCG algorithm from ISO/IEC 9899 standard, the sequence
looks much better, with about the same computational effort needed.
Signed-off-by: Serge Vakulenko
Reviewed-by: Aurelien Jarno
Reviewed-by: Leon Alrae
Signed-off-by: Leon Alrae
---
hw/mips/cputimer.c | 9
code, which
clutters translate.c.
Cc: Leon Alrae
Signed-off-by: Aurelien Jarno
Reviewed-by: Leon Alrae
Signed-off-by: Leon Alrae
---
target-mips/translate.c | 624 ++--
1 file changed, 19 insertions(+), 605 deletions(-)
diff --git a/target
I've been testing target mips on the tcg-search-2 branch -- I haven't
spotted any obvious regressions and performance gain was visible in some
of my tests. On qemu-system-mips64el the Linux kernel build time went
down from 465m to 305m. And in a virtual memory torture test I can see
slightly above
On 02/09/2015 23:50, Richard Henderson wrote:
> @@ -8821,102 +8840,126 @@ static void gen_cp1 (DisasContext *ctx, uint32_t
> opc, int rt, int fs)
> tcg_temp_free(t0);
> }
>
> -static void gen_movci (DisasContext *ctx, int rd, int rs, int cc, int tf)
> +static void gen_movci(DisasContext *c
; 1 file changed, 22 insertions(+), 26 deletions(-)
Reviewed-by: Leon Alrae
: Alex Smith
> Cc: Aurelien Jarno
> Cc: Leon Alrae
> ---
> target-mips/op_helper.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/target-mips/op_helper.c b/target-mips/op_helper.c
> index 809a061e296b..6fe00201c10d 100644
> --- a/target-mip
: Alex Smith
> Cc: Aurelien Jarno
> Cc: Leon Alrae
> ---
> Changes in v2:
> - Fix build breakage for user builds.
> - Correct existing code to follow QEMU coding style.
> ---
> target-mips/op_helper.c | 9 +++--
> 1 file changed, 7 insertions(+), 2 deletions(-)
Reviewed-by: Leon Alrae
er.c | 19 ---
> 1 file changed, 8 insertions(+), 11 deletions(-)
Reviewed-by: Leon Alrae
SIONS
>
> target-mips/translate.c | 663
> ++--
> 1 file changed, 19 insertions(+), 644 deletions(-)
>
Reviewed-by: Leon Alrae
Thanks,
Leon
stuck in the loop infinitely as we always
generate the same index.
Signed-off-by: Leon Alrae
---
hw/mips/cputimer.c | 8 +++-
1 file changed, 7 insertions(+), 1 deletion(-)
diff --git a/hw/mips/cputimer.c b/hw/mips/cputimer.c
index 577c9ae..c55d102 100644
--- a/hw/mips/cputimer.c
+++ b/hw
() with single tcg_gen_ld32s_tl().
Leon Alrae (2):
target-mips: correct MTC0 instruction on MIPS64
target-mips: remove gen_mfc0_load64() and use tcg_gen_ld32s_tl()
target-mips/translate.c | 61 +++--
1 file changed, 24 insertions(+), 37 deletions
Remove misleading gen_mfc0_load64() which actually loads 32 or 64 bits
depending whether MIPS32 or MIPS64 and also replace the pair of
tcg_gen_ld_tl() + tcg_gen_ext32s_tl() with single tcg_gen_ld32s_tl().
Signed-off-by: Leon Alrae
---
target-mips/translate.c | 43
MTC0 on a 64-bit processor should move entire 64-bit GPR content to CP0
register.
Signed-off-by: Leon Alrae
---
target-mips/translate.c | 18 +++---
1 file changed, 7 insertions(+), 11 deletions(-)
diff --git a/target-mips/translate.c b/target-mips/translate.c
index cd0cf8b
rs cannot be the zero register, Reserved Instruction exception must be
signalled for this case.
Signed-off-by: Leon Alrae
---
target-mips/translate.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/target-mips/translate.c b/target-mips/translate.c
index 7fb7c01..a8fd4a3
Implement the relationship between CP0.Status.KX, SX and UX. It should not
be possible to set UX bit if SX is 0, the same applies for setting SX if
KX is 0.
Signed-off-by: Leon Alrae
---
target-mips/cpu.h | 7 ++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/target-mips
) function.
Second patch allows the R6 CPU to resume the execution regardless of
cpu_mips_hw_interrupts_enabled().
Leon Alrae (2):
target-mips: move the test for enabled interrupts to a separate
function
target-mips: implement the CPU wake-up on non-enabled interrupts in R6
target-mips/cpu
In Release 6, the behaviour of WAIT has been modified to make it a
requirement that a processor that has disabled operation as a result of
executing a WAIT will resume operation on arrival of an interrupt even if
interrupts are not enabled.
Signed-off-by: Leon Alrae
---
target-mips/cpu.c | 7
Signed-off-by: Leon Alrae
---
target-mips/cpu.c| 4 +++-
target-mips/cpu.h| 29 +++--
target-mips/helper.c | 3 ++-
3 files changed, 20 insertions(+), 16 deletions(-)
diff --git a/target-mips/cpu.c b/target-mips/cpu.c
index 4027d0f..144eea9 100644
--- a/target
:
/usr/include/sys/types.h:46: error: conflicting types for ‘loff_t’
/usr/include/linux/types.h:30: error: previous declaration of ‘loff_t’ was here
In file included from /usr/include/sys/types.h:133,
from /work/qemu/hw/vfio/pci.c:25:
...
Signed-off-by: Leon Alrae
---
hw/vfio
On 18/08/2015 18:35, Petar Jovanovic wrote:
> From: Petar Jovanovic
>
> Instructions recip.{s|d} and rsqrt.{s|d} do not require 64-bit FPU neither
> they require any particular mode for its FPU. This patch removes the checks
> that may break a program that uses these instructions.
This seems to
On 25/08/2015 23:40, Petar Jovanovic wrote:
>> @@ -9839,7 +9837,6 @@ static void gen_farith (DisasContext *ctx, enum
> fopcode op1,
>> opn = "movn.d";
>> break;
>> case OPC_RECIP_D:
>> -check_cp1_64bitmode(ctx);
>
>> I think this needs check_cp1_registers() now, i.e.
On 26/08/2015 13:12, Petar Jovanovic wrote:
> From: Petar Jovanovic
>
> Instructions recip.{s|d} and rsqrt.{s|d} do not require 64-bit FPU neither
> they require any particular mode for its FPU. This patch removes the checks
> that may break a program that uses these instructions.
>
> Signed-off
On 01/07/2015 14:59, Aurelien Jarno wrote:
> When syncing the task ASID with EntryHi, correctly or the value instead
> of assigning it.
>
> Reported-by: "Dr. David Alan Gilbert"
> Signed-off-by: Aurelien Jarno
> Cc: Leon Alrae
> ---
> target-mips/op_he
On 30/06/2015 16:33, Yongbok Kim wrote:
> In the Release 6 of the MIPS Architecture, LL, SC, LLD, SCD, PREF
> and CACHE instructions have 9 bits offsets.
>
> Signed-off-by: Yongbok Kim
> ---
> disas/mips.c | 12 ++--
> 1 files changed, 6 insertions(+), 6 deletions(-)
Applied this and
On 08/07/2015 16:22, Paolo Bonzini wrote:
> -BEGIN PGP SIGNED MESSAGE-
> Hash: SHA256
>
>
>
> On 08/07/2015 17:03, James Hogan wrote:
>> Hi Paolo,
>>
>> On 24/04/15 11:26, James Hogan wrote:
>>> A couple of small fixes for accessing 32-bit KVM registers on
>>> big endian, and to sign ext
h newer MIPS KVM headers
>
> target-mips/kvm.c | 15 ++-
> tcg/mips/tcg-target.c | 4 ++--
> 2 files changed, 4 insertions(+), 15 deletions(-)
Reviewed-by: Leon Alrae
Peter, since these are build fixes, could they be squeezed into rc0?
Thanks,
Leon
On 10/07/2015 01:51, arei.gong...@huawei.com wrote:
> From: Gonglei
>
> Failing to save or free storage allocated
> by "g_strdup(cmd)" leaks it. Let's use a
> variable to storage it.
>
> Signed-off-by: Gonglei
> ---
> vl.c | 5 -
> 1 file changed, 4 insertions(+), 1 deletion(-)
>
> diff -
On 12/07/2015 03:00, Peter Crosthwaite wrote:
> From: Peter Crosthwaite
>
> Move the target_disas() mips specifics to the QOM disas_set_info hook
> and delete the #ifdef specific code in disas.c.
>
> Cc: Aurelien Jarno
> Cc: Leon Alrae
> Signed-off-by: Peter Cros
ilure.
Signed-off-by: Leon Alrae
---
target-mips/mips-semi.c | 23 +++
1 file changed, 19 insertions(+), 4 deletions(-)
diff --git a/target-mips/mips-semi.c b/target-mips/mips-semi.c
index 1162c76..5050940 100644
--- a/target-mips/mips-semi.c
+++ b/target-mips/mips-semi.c
@@ -
Make use of CMPOP in floating-point compare instructions.
Signed-off-by: Leon Alrae
---
target-mips/translate.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/target-mips/translate.c b/target-mips/translate.c
index 7302857..4a1ffdb 100644
--- a/target-mips/translate.c
+++ b/target-mips
Fix Debug Mode flag clearing, and when DERET is placed between LL and SC
do not make SC fail.
Signed-off-by: Leon Alrae
---
target-mips/op_helper.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/target-mips/op_helper.c b/target-mips/op_helper.c
index 2a9ddff..d461ad8
On 14/07/2015 16:45, Aurelien Jarno wrote:
> By the way, is this debug code really useful? I think by looking at the
> TCG code (-d in_asm,op), it's easy to determine if an instruction is
> correctly disassembled or not.
>
For me this debug code doesn't seem to be useful at all and it only clutte
gen_buffer ()
(gdb) x/i 0x559f6f37
=> 0x559f6f37 : mov
%gs:0x0(%rbp),%ebp
(gdb) info registers rbp
rbp0x76fff040 0x76fff040
The program runs fine in singlestep mode, or with disabled TCG
optimizations. Also, I'm not able to reproduce it in
case GUEST_BASE == 0 or
> a segment register is in use), or by doing an explicit zero-extension.
> The zero-extension can be done in place as we know the registers holds
> a 32-bit value.
>
> Reported-by: Leon Alrae
> Cc: Leon Alrae
> Cc: Paolo Bonzini
> Cc: Richard Hen
On 30/06/2015 14:18, Leon Alrae wrote:
> On 29/06/2015 11:20, Andrew Bennett wrote:
>> From: Andrew Bennett
>>
>> For the MIPS N64 ABI when QEMU reads the break/trap instruction so that
>> it can inspect the break/trap code it reads 8 rather than 4 bytes
>> wh
gned address at the
> beginning of the LWL/LWR/LDL/LDR instructions to possibly trigger a page
> fault and fill the QEMU TLB.
>
> Cc: Leon Alrae
> Reported-by: Hervé Poussineau
> Tested-by: Hervé Poussineau
> Signed-off-by: Aurelien Jarno
> ---
> target-mips/translate
or MIPS MT
target-mips: fix page fault address for LWL/LWR/LDL/LDR
Leon Alrae (3):
target-mips: correct DERET instruction
target-mips: fix logically dead code reported by Coverity
target-mips: fix resource leak reported by Coverity
Yongbok Kim (3):
target-mips: fi
From: Yongbok Kim
In the Release 6 of the MIPS Architecture, LL, SC, LLD, SCD, PREF
and CACHE instructions have 9 bits offsets.
Signed-off-by: Yongbok Kim
Reviewed-by: Aurelien Jarno
Reviewed-by: Leon Alrae
Signed-off-by: Leon Alrae
---
disas/mips.c | 12 ++--
1 file changed, 6
Fix Debug Mode flag clearing, and when DERET is placed between LL and SC
do not make SC fail.
Signed-off-by: Leon Alrae
Reviewed-by: Aurelien Jarno
---
target-mips/op_helper.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/target-mips/op_helper.c b/target-mips
Jarno
Reviewed-by: Leon Alrae
Signed-off-by: Leon Alrae
---
target-mips/mips-defs.h | 2 +-
target-mips/translate_init.c | 18 +-
2 files changed, 10 insertions(+), 10 deletions(-)
diff --git a/target-mips/mips-defs.h b/target-mips/mips-defs.h
index 20aa87c..53b185e 100644
Make use of CMPOP in floating-point compare instructions.
Signed-off-by: Leon Alrae
Reviewed-by: Aurelien Jarno
---
target-mips/translate.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/target-mips/translate.c b/target-mips/translate.c
index 7302857..4a1ffdb 100644
--- a/target-mips
to fail because it does not understand the code number.
The fix forces QEMU to always read 4 bytes of instruction data rather
than deciding how much to read based on the ABI.
Signed-off-by: Andrew Bennett
Reviewed-by: Leon Alrae
Signed-off-by: Leon Alrae
---
linux-user/main.c | 4 ++--
1 file
ilure.
Signed-off-by: Leon Alrae
Reviewed-by: Aurelien Jarno
---
target-mips/mips-semi.c | 23 +++
1 file changed, 19 insertions(+), 4 deletions(-)
diff --git a/target-mips/mips-semi.c b/target-mips/mips-semi.c
index 1162c76..5050940 100644
--- a/target-mips/mips-semi.c
From: Aurelien Jarno
When syncing the task ASID with EntryHi, correctly or the value instead
of assigning it.
Reported-by: "Dr. David Alan Gilbert"
Signed-off-by: Aurelien Jarno
Cc: Leon Alrae
Reviewed-by: Leon Alrae
Signed-off-by: Leon Alrae
---
target-mips/op_helper.c | 2
From: Yongbok Kim
MSACSR.Cause bits are needed to be cleared before a vector floating-point
instructions.
FEXDO.df, FEXUPL.df and FEXUPR.df were missed out.
Signed-off-by: Yongbok Kim
Reviewed-by: Aurelien Jarno
Reviewed-by: Leon Alrae
Signed-off-by: Leon Alrae
---
target-mips/msa_helper.c
/LDR instructions to possibly trigger a page
fault and fill the QEMU TLB.
Cc: Leon Alrae
Reported-by: Hervé Poussineau
Tested-by: Hervé Poussineau
Signed-off-by: Aurelien Jarno
Signed-off-by: Leon Alrae
---
target-mips/translate.c | 12
1 file changed, 12 insertions(+)
diff
Reported-by: Peter Maydell
Signed-off-by: Leon Alrae
---
target-mips/machine.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/target-mips/machine.c b/target-mips/machine.c
index 8fa755c..b15c43a 100644
--- a/target-mips/machine.c
+++ b/target-mips/machine.c
@@ -153,6
On 22/07/2015 13:08, Peter Maydell wrote:
> On 11 March 2015 at 16:15, Leon Alrae wrote:
>> Create VMStateDescription for MIPS CPU. The new structure contains exactly
>> the
>> same fields as before, therefore leaving existing version_id.
>>
>> Signed-off-b
601 - 700 of 988 matches
Mail list logo
