On 14/07/2015 16:45, Aurelien Jarno wrote: > When a LWL, LWR, LDL or LDR instruction triggers a page fault, QEMU > currently reports the aligned address in CP0 BadVAddr, while the Windows > NT kernel expects the unaligned address. > > This patch adds a byte access with the unaligned address at the > beginning of the LWL/LWR/LDL/LDR instructions to possibly trigger a page > fault and fill the QEMU TLB. > > Cc: Leon Alrae <leon.al...@imgtec.com> > Reported-by: Hervé Poussineau <hpous...@reactos.org> > Tested-by: Hervé Poussineau <hpous...@reactos.org> > Signed-off-by: Aurelien Jarno <aurel...@aurel32.net> > --- > target-mips/translate.c | 12 ++++++++++++ > 1 file changed, 12 insertions(+)
Thanks, applied to mips-next. Leon
