On 20/05/2015 09:30, Liviu Ionescu wrote:
>
>> On 20 May 2015, at 11:11, Leon Alrae wrote:
>>
>> like "If both are specified, -kernel/-append are ignored (-kernel is
>> used to load an image, but the path won't be passed to semihosting)"
> ...
&g
On 20/05/2015 09:54, Peter Maydell wrote:
> Well, with these patches alone we end up with a documented but broken
> option. For reasons of consistency (again) I don't want the new
> option in the tree without it being supported by ARM, even if the
> MIPS code that uses it goes in.
Fair enough. I’l
On 20/05/2015 12:12, Liviu Ionescu wrote:
> yes, that's correct, my comment was related to the above quotes from your
> message, in the first part you mention "the path won't be passed to
> semihosting", which is not consistent with the actual behaviour, since the
> entire kernel path is passed
On 20/05/2015 09:54, Peter Maydell wrote:
> On 20 May 2015 at 09:11, Leon Alrae wrote:
>> Agreed. We could initialize semihosting.argv[0] with -kernel and argv[1]
>> with -append string if in semihosting mode and no semihosting args have
>> been specified. I'll update
On 21/05/2015 15:01, Peter Maydell wrote:
> Well, it will presumably mean that on a MIPS semihosting case
> if the user tries -append "some command line" it won't do what
> they expect...
Yes, but I think the user should use semihosting-config arg, which is
more natural in semihosting context, rat
kernels may use all
> available memory without the user having to manually specifying its size
> & location.
>
> Signed-off-by: Paul Burton
> Cc: Aurelien Jarno
> Cc: Leon Alrae
> ---
Reviewed-by: Leon Alrae
do (i.e. argv[1] contains the whole
-append), but is more intuitive from UHI user's point of view and Linux
kernel just does not care as it concatenates argv[1..n] into single cmdline
string anyway.
Signed-off-by: Leon Alrae
---
include/exec/semihost.h | 18 ++
qemu-opt
renaming is not required (these
modifications are relatively simple anyway).
Leon Alrae (2):
semihosting: create SemihostingConfig structure and semihost.h
semihosting: add --semihosting-config arg sub-argument
gdbstub.c | 8 ++--
include/exec/gdbstub.h| 6 ---
include/
stuff from target specific semihosting
code.
Signed-off-by: Leon Alrae
Reviewed-by: Peter Maydell
---
gdbstub.c | 8
include/exec/gdbstub.h| 6 --
include/exec/semihost.h | 44
include/sysemu/sysemu.h | 1
which
probably is fine. However, IIUC these two instructions LWPC and LDPC are
from mips16 ASE, so probably you want to skip them as well? (note that
for R6 we’ve got R6_OPC_LWPC and R6_OPC_LDPC and they are naturally
aligned).
Apart from that,
Reviewed-by: Leon Alrae
BTW these OPC_LWPC a
On 27/05/2015 14:29, Yongbok Kim wrote:
> MIPS SIMD Architecture vector loads and stores require misalignment support.
> MSA Memory access should work as an atomic operation. Therefore, it has to
> check validity of all addresses for a vector store access if it is spanning
> into two pages.
>
> Se
On 27/05/2015 14:29, Yongbok Kim wrote:
> MIPS SIMD Architecture vector loads and stores require misalignment support.
> MSA Memory access should work as an atomic operation. Therefore, it has to
> check validity of all addresses for a vector store access if it is spanning
> into two pages.
>
> Se
On 27/02/2015 19:05, Paolo Bonzini wrote:
> Reported by Leon Alrae on the mailing list, and by
> Andreas Gustafsson as Launchpad bug 1426472.
>
> Paolo Bonzini (2):
> cpus: fix deadlock and segfault in qemu_mutex_lock_iothread
> cpus: be more paranoid in avoiding deadlocks
Hi Matthew,
On 01/03/2015 22:17, Matthew Fortune wrote:
> Hi Leon,
>
> Many thanks for implementing this interface in QEMU. I haven't reviewed
> in great detail as I am not familiar enough with QEMU internals to do
> so. Overall it seems to match the UHI spec. The one potential issue is
> transla
they are cleared. Therefore there is no need for saving
them in vmstate.
Signed-off-by: Leon Alrae
Reviewed-by: Richard Henderson
---
target-mips/cpu.h| 17 +
target-mips/machine.c| 34 ++
target-mips/msa_helper.c | 12
lags (2015-03-11
14:13:57 +)
MIPS patches 2015-03-11
Changes:
* use VMStateDescription for MIPS CPU
----
Leon Alrae (2):
target-mips: replace cpu_save/cpu
Create VMStateDescription for MIPS CPU. The new structure contains exactly the
same fields as before, therefore leaving existing version_id.
Signed-off-by: Leon Alrae
---
target-mips/cpu-qom.h | 4 +
target-mips/cpu.c | 1 +
target-mips/cpu.h | 2 -
target-mips/machine.c | 567
m.c can now be dropped.
>
> Signed-off-by: James Hogan
> Cc: Paolo Bonzini
> Cc: Leon Alrae
> Cc: Aurelien Jarno
> ---
> target-mips/kvm.c | 11 ---
> 1 file changed, 11 deletions(-)
Reviewed-by: Leon Alrae
> Signed-off-by: James Hogan
> Cc: Paolo Bonzini
> Cc: Leon Alrae
> Cc: Aurelien Jarno
> ---
> target-mips/kvm.c | 2 --
> 1 file changed, 2 deletions(-)
Reviewed-by: Leon Alrae
onzini
> Cc: Leon Alrae
> Cc: Aurelien Jarno
> ---
> target-mips/kvm.c | 11 +++
> 1 file changed, 11 insertions(+)
Reviewed-by: Leon Alrae
y a guest so QEMU needs to know about them so as not
> to clobber them on migration/savevm.
>
> Signed-off-by: James Hogan
> Cc: Paolo Bonzini
> Cc: Leon Alrae
> Cc: Aurelien Jarno
> ---
> target-mips/kvm.c | 108
> +
PC needs to be saved if an exception can be generated by an helper.
This fixes a problem related to resuming the execution at unexpected address
after an exception (caused by MSA load/store instruction) has been serviced.
Signed-off-by: Leon Alrae
---
target-mips/translate.c | 2 ++
1 file
CP0.BadVAddr is supposed to capture the most recent virtual address that caused
the exception. Currently this does not work correctly for unaligned instruction
fetch as translation is not stopped and CP0.BadVAddr is updated with subsequent
addresses.
Signed-off-by: Leon Alrae
---
v2
exception.
Config5.UFE: Allows user to write/read Config5.FRE using CTC1/CFC1 instructions.
Enable the feature in MIPS64R6-generic CPU.
Signed-off-by: Leon Alrae
---
target-mips/cpu.h| 13 +-
target-mips/op_helper.c | 34 +
target-mips/translate.c | 307
Hi James,
On 17/03/2015 10:55, James Hogan wrote:
> Hi Leon,
>
> On 17/03/15 09:56, Leon Alrae wrote:
>> This relatively small architectural feature adds the following:
>>
>> FIR.FREP: Read-only. If FREP=1, then Config5.FRE and Config5.UFE are
>> available.
&g
patchset does not include MIPS64 Privileged Resource
Architecture modifications. All those changes will follow the current patchset
soon.
Leon Alrae (17):
target-mips: introduce MIPS64R6 ISA and a new generic CPU
target-mips: signal RI Exception on instructions removed in R6
target-mips: add
Define ISA_MIPS64R6 and add MIPS64R6-generic core supporting new ISA.
Additionally define ISA_MIPS64R3 and ISA_MIPS64R5 to fill the gap.
Signed-off-by: Leon Alrae
---
target-mips/mips-defs.h | 28 +++-
target-mips/translate_init.c | 29
Signed-off-by: Leon Alrae
---
disas/mips.c|8
target-mips/translate.c | 16
2 files changed, 24 insertions(+), 0 deletions(-)
diff --git a/disas/mips.c b/disas/mips.c
index 2106b57..b950e53 100644
--- a/disas/mips.c
+++ b/disas/mips.c
@@ -521,6 +521,8
From: Yongbok Kim
Signed-off-by: Yongbok Kim
Signed-off-by: Leon Alrae
---
disas/mips.c| 44 ++
target-mips/helper.h| 27 ++
target-mips/op_helper.c | 113 ++
target-mips/translate.c | 206
The encoding of LL and SC instruction has changed in MIPS32 Release 6.
Signed-off-by: Leon Alrae
---
disas/mips.c|9 -
target-mips/translate.c | 29 +++--
2 files changed, 35 insertions(+), 3 deletions(-)
diff --git a/disas/mips.c b/disas
After selecting CPU in QEMU the base ISA will not change. Therefore
introducing *_arch function pointers that are set in cpu_state_reset to
point at the appropriate SPECIAL and SPECIAL3 decoding functions, and avoid
unnecessary 'if' statements.
Signed-off-by: Leon Alrae
---
t
functions will contain instructions which were removed in R6.
Signed-off-by: Leon Alrae
---
target-mips/translate.c | 227 +--
1 files changed, 159 insertions(+), 68 deletions(-)
diff --git a/target-mips/translate.c b/target-mips/translate.c
ind
Move DSP and Loongson instruction to *_legacy functions as they have been
removed in R6.
Signed-off-by: Leon Alrae
---
target-mips/translate.c | 195 ---
1 files changed, 98 insertions(+), 97 deletions(-)
diff --git a/target-mips/translate.c b
In R6 the special behaviour for data references is also specified for Kernel
and Supervisor mode. Therefore MIPS_HFLAG_UX is replaced by generic MIPS_HFLAG_X
indicating whether 64-bit mode is enabled in current operating mode.
Signed-off-by: Leon Alrae
---
target-mips/cpu.h | 14
Signed-off-by: Leon Alrae
---
disas/mips.c| 41 +-
target-mips/translate.c | 194 ---
2 files changed, 222 insertions(+), 13 deletions(-)
diff --git a/disas/mips.c b/disas/mips.c
index bee39d8..6def662 100644
--- a/disas/mips.c
From: Yongbok Kim
Signed-off-by: Yongbok Kim
Signed-off-by: Leon Alrae
---
disas/mips.c|4 ++
target-mips/helper.h|2 +
target-mips/op_helper.c | 16 +++
target-mips/translate.c | 103 +-
4 files changed, 113
loads / stores
- traps
- legacy accumulator instructions
- COP1X
- MIPS-3D
Signed-off-by: Leon Alrae
---
target-mips/translate.c | 64 +--
1 files changed, 56 insertions(+), 8 deletions(-)
diff --git a/target-mips/translate.c b/target-mips/translate.c
Also consider OPC_SPIM instruction as deleted in R6 because it is overlaping
with MIPS32R6 SDBBP.
Signed-off-by: Leon Alrae
---
disas/mips.c|5 ++
target-mips/translate.c | 120 ---
2 files changed, 66 insertions(+), 59 deletions
JR has been removed in R6 and now this instruction will cause Reserved
Instruction Exception. Therefore use JALR with rd=0 which is equivalent to JR.
Signed-off-by: Leon Alrae
---
hw/mips/mips_malta.c | 10 +-
1 files changed, 5 insertions(+), 5 deletions(-)
diff --git a/hw/mips
.
Signed-off-by: Leon Alrae
---
disas/mips.c| 22 +++
target-mips/helper.h| 21 +++
target-mips/op_helper.c | 108 +++
target-mips/translate.c | 449 ++-
4 files changed, 552 insertions(+), 48 deletions(-)
diff --git a/disas
Status.FR bit must be ignored on write and read as 1 when an implementation of
Release 6 of the Architecture in which a 64-bit floating point unit is
implemented.
Signed-off-by: Leon Alrae
---
target-mips/translate.c |7 +++
1 files changed, 7 insertions(+), 0 deletions(-)
diff --git a
returns y if |y| > |x|,
otherwise maxnum(x,y)
Signed-off-by: Leon Alrae
---
fpu/softfloat.c | 37 ++---
include/fpu/softfloat.h |4
2 files changed, 34 insertions(+), 7 deletions(-)
diff --git a/fpu/softfloat.c b/fpu/softf
From: Yongbok Kim
Introduce MIPS32R6 Compact Branch instructions which do not have delay slot -
they have forbidden slot instead. However, current implementation does not
support forbidden slot yet.
Signed-off-by: Yongbok Kim
Signed-off-by: Leon Alrae
---
disas/mips.c| 67
From: Yongbok Kim
Signed-off-by: Yongbok Kim
Signed-off-by: Leon Alrae
---
disas/mips.c|2 ++
target-mips/translate.c | 18 --
2 files changed, 18 insertions(+), 2 deletions(-)
diff --git a/disas/mips.c b/disas/mips.c
index 5eac8cc..3852ec4 100644
--- a
The encoding of PREF, CACHE, LLD and SCD instruction changed in MIPS32R6.
Additionally, the hint codes in PREF instruction greater than or
equal to 24 generate Reserved Instruction Exception.
Signed-off-by: Leon Alrae
---
disas/mips.c|4
target-mips/translate.c | 29
Use "R6_" prefix in front of all new Multiply / Divide instructions for
easier differentiation between R6 and preR6.
Signed-off-by: Leon Alrae
---
disas/mips.c| 16 ++
target-mips/translate.c | 351 ---
2 files changed, 346
On 30/05/14 23:41, Aurelien Jarno wrote:
>> In R6 the special behaviour for data references is also specified for Kernel
>> and Supervisor mode. Therefore MIPS_HFLAG_UX is replaced by generic
>> MIPS_HFLAG_X
>> indicating whether 64-bit mode is enabled in current operating mode.
>
> I haven't fou
On 30/05/14 17:43, Aurelien Jarno wrote:
>> +/* A generic CPU providing MIPS64 Release 6 features.
>> + FIXME: Eventually this should be replaced by a real CPU model. */
>> +.name = "MIPS64R6-generic",
>> +.CP0_PRid = 0x0001,
>> +.CP0_Config0 = MIPS_CO
On 02/06/14 20:16, Aurelien Jarno wrote:
>> -case OPC_DADDI:
>> +case OPC_DADDI: /* OPC_BNVC, OPC_BNEZALC, OPC_BNEC */
>> +if (ctx->insn_flags & ISA_MIPS32R6) {
>> +/* OPC_BNVC, OPC_BNEZALC, OPC_BNEC */
>> +gen_compute_compact_branch(ctx, op, rs, rt, imm << 2
},
> +{"jr.hb", "s", 0x0408, 0xfc1f, UBD|RD_s, 0,
> I32R6 }, /* jalr.hb */
jr.hb match should be 0x0409, otherwise:
Reviewed-by: Leon Alrae
Hi Serge,
On 06/07/15 07:14, Serge Vakulenko wrote:
> Needed for pic32mx (M4K) and pic32mz (microAptivUP) simulation.
>
> Signed-off-by: Serge Vakulenko
> ---
> target-mips/translate_init.c | 46
>
> 1 file changed, 46 insertions(+)
This patch look
On 02/10/15 16:34, Yongbok Kim wrote:
> Correct updating XContext.Region field on mmu exceptions.
> If Config3.CTXTC = 0 then the R filed of XContext has to be updated
s/filed/field
> with the value of bits 63..62 of the virtual address upon a TLB
> exception.
>
> Signed-off-by: Yongbok Kim
> -
On 02/10/15 17:50, Yongbok Kim wrote:
> Add enum for BREAK32
>
> Signed-off-by: Yongbok Kim
> ---
> target-mips/translate.c |3 ++-
> 1 files changed, 2 insertions(+), 1 deletions(-)
Reviewed-by: Leon Alrae
On 05/10/15 10:33, Yongbok Kim wrote:
> @@ -18958,6 +18964,10 @@ static void decode_opc(CPUMIPSState *env,
> DisasContext *ctx)
> check_insn_opc_removed(ctx, ISA_MIPS32R6);
> gen_trap(ctx, op1, rs, -1, imm);
> break;
> +case OPC_SIGRIE:
> +
On 07/10/15 10:46, Richard Henderson wrote:
> Leon, do you want to take this as a mips maintainer, or shall I as tcg
> maintainer?
I thought this would go via Aurelien's mips tcg-backend queue. But if
Aurelien is busy, could you take them? (at the moment I don't have
anything handy to test the mip
On 27/10/15 17:12, Yongbok Kim wrote:
> +static uint64_t gic_read(void *opaque, hwaddr addr, unsigned size)
> +{
> +MIPSGICState *gic = (MIPSGICState *) opaque;
> +uint32_t vp_index = gic_get_current_vp(gic);
> +uint64_t ret = 0;
> +int i, base, irq_src;
> +uint32_t other_index;
On 29/10/15 17:17, Yongbok Kim wrote:
> Correct updating XContext.Region field on mmu exceptions.
> If Config3.CTXTC = 0 then the R field of XContext has to be updated
> with the value of bits 63..62 of the virtual address upon a TLB
> exception.
> Also fixed the below line which overs 80 character
n (1):
hw/mips_malta: Fix KVM PC initialisation
Leon Alrae (3):
target-mips: move the test for enabled interrupts to a separate function
target-mips: implement the CPU wake-up on non-enabled interrupts in R6
target-mips: update writing to CP0.Status.KX/SX/UX in MIPS Release R6
Signed-off-by: Leon Alrae
---
target-mips/cpu.c| 4 +++-
target-mips/cpu.h| 29 +++--
target-mips/helper.c | 3 ++-
3 files changed, 20 insertions(+), 16 deletions(-)
diff --git a/target-mips/cpu.c b/target-mips/cpu.c
index 37880d2..bbfee45 100644
--- a/target
Kim
Reviewed-by: James Hogan
Reviewed-by: Leon Alrae
Signed-off-by: Leon Alrae
---
target-mips/helper.c | 7 ---
1 file changed, 4 insertions(+), 3 deletions(-)
diff --git a/target-mips/helper.c b/target-mips/helper.c
index 2d86323..b3fe816 100644
--- a/target-mips/helper.c
+++ b/target
In Release 6, the behaviour of WAIT has been modified to make it a
requirement that a processor that has disabled operation as a result of
executing a WAIT will resume operation on arrival of an interrupt even if
interrupts are not enabled.
Signed-off-by: Leon Alrae
---
target-mips/cpu.c | 7
From: Yongbok Kim
Add Performance Counter (4) and XNP (5) register numbers to RDHWR.
Add check_hwrena() to simplify access control checkings.
Add RDHWR support to microMIPS R6.
Signed-off-by: Yongbok Kim
Reviewed-by: Leon Alrae
Signed-off-by: Leon Alrae
---
target-mips/cpu.h | 1
for KVM to use
ram_low_size. Fix that now.
Fixes: 71c199c81d29 ("mips_malta: provide ememsize env variable to kernels")
Signed-off-by: James Hogan
Cc: Paul Burton
Cc: Leon Alrae
Cc: Aurelien Jarno
Reviewed-by: Aurelien Jarno
Reviewed-by: Leon Alrae
Signed-off-by: Leon Alrae
---
From: Yongbok Kim
Set Config5.XNP for R6 cores to indicate the extended LL/SC family
of instructions NOT present.
Signed-off-by: Yongbok Kim
Reviewed-by: Leon Alrae
Signed-off-by: Leon Alrae
---
target-mips/translate_init.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff
Implement the relationship between CP0.Status.KX, SX and UX. It should not
be possible to set UX bit if SX is 0, the same applies for setting SX if
KX is 0.
Signed-off-by: Leon Alrae
---
target-mips/cpu.h | 7 ++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/target-mips
From: Yongbok Kim
Add SIGRIE (Signal Reserved Instruction Exception) for both MIPS and
microMIPS.
The instruction allows to use the 16-bit code field for software use.
This instruction is introduced by and required as of Release 6.
Signed-off-by: Yongbok Kim
Reviewed-by: Leon Alrae
Signed-off
From: Yongbok Kim
Add enum for BREAK32
Signed-off-by: Yongbok Kim
Reviewed-by: Leon Alrae
Reviewed-by: Aurelien Jarno
Signed-off-by: Leon Alrae
---
target-mips/translate.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/target-mips/translate.c b/target-mips
On 18/01/16 17:35, Peter Maydell wrote:
> Clean up includes so that osdep.h is included first and headers
> which it implies are not included manually.
>
> This commit was created with scripts/clean-includes.
>
> Signed-off-by: Peter Maydell
> ---
> disas/mips.c | 1 +
> hw/mips/add
Hi,
Here's my target-mips queue, few fixes and includes clean-up.
Thanks,
Leon
Cc: Peter Maydell
Cc: Aurelien Jarno
The following changes since commit 047e363b05679724d6b784c6ec6310697fe48ba0:
Merge remote-tracking branch 'remotes/pmaydell/tags/pull-softfloat-20160122'
into staging (2016-
From: Dongxue Zhang
CP0IntCtl_IPPC1, the last letter should be 'i', not 'one'.
Signed-off-by: Dongxue Zhang
Reviewed-by: Leon Alrae
Signed-off-by: Leon Alrae
---
target-mips/cpu.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target-mips/cpu.h b/tar
From: Aurelien Jarno
cvt.s.d and cvt.d.s are FP operations and thus need to convert input
sNaN into corresponding qNaN. Explicitely use the floatXX_maybe_silence_nan
functions for that as the floatXX_to_floatXX functions do not do that.
Cc: Leon Alrae
Signed-off-by: Aurelien Jarno
Reviewed-by
GPR[rs]) >> (8*(4-bp))
tmp = tmp_rt_hi || tmp_rt_lo
GPR[rd] = sign_extend.32(tmp)
Signed-off-by: Miodrag Dinic
Reviewed-by: Aurelien Jarno
Reviewed-by: Leon Alrae
Signed-off-by: Leon Alrae
---
target-mips/translate.c | 11 ++-
1 file changed, 10 insertions(+)
From: Peter Maydell
Clean up includes so that osdep.h is included first and headers
which it implies are not included manually.
This commit was created with scripts/clean-includes.
Signed-off-by: Peter Maydell
Reviewed-by: Leon Alrae
Signed-off-by: Leon Alrae
---
disas/mips.c
Hi James,
On 18/12/15 10:46, James Hogan wrote:
> @@ -611,17 +664,51 @@ static int kvm_mips_get_fpu_registers(CPUState *cs)
> restore_flush_mode(env);
> }
>
> -/* Floating point registers */
> -for (i = 0; i < 32; ++i) {
> -if (env->CP0_Status &
On 25/01/16 17:40, Peter Maydell wrote:
> The r4k_tlb_t structure uses the uint_fast*_t types. Most of these
> uses are in bitfields and are thus pointless, because the bitfield
> itself specifies the width of the type; just use 'unsigned int'
> instead. (On glibc uint_fast16_t is defined as either
On 02/02/16 12:39, James Hogan wrote:
> I can use restore_msa_fp_status(env); here, and actually the FP one
> above (in previous patch) can change to restore_fp_status(env); too,
> since it does the same thing.
This sounds good.
> I've rebased and resolved the uint64 thing too, would you like a r
/EVP instructions.
Signed-off-by: Yongbok Kim
Signed-off-by: Leon Alrae
---
This is an updated version of the patch originally sent by Yongbok some
time ago.
v2:
* rebased
* fix typo: GlobalNumer -> GlobalNumber
* fix minor style issues
* update the patch description
---
disas/mip
Add ITU block to Malta board and make it available to multithreading
processors.
Signed-off-by: Leon Alrae
---
hw/mips/mips_malta.c | 53
1 file changed, 53 insertions(+)
diff --git a/hw/mips/mips_malta.c b/hw/mips/mips_malta.c
index c5da83f
Bypass View does not cause issuing thread to block and does not affect
any of the cells state bit.
Read from a FIFO cell returns the value of the oldest entry.
Store to a FIFO cell changes the value of the newest entry.
Signed-off-by: Leon Alrae
---
hw/misc/mips_itu.c | 27
Signed-off-by: Leon Alrae
---
target-mips/translate.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/target-mips/translate.c b/target-mips/translate.c
index c6e2951..3fb3744 100644
--- a/target-mips/translate.c
+++ b/target-mips/translate.c
@@ -17179,6 +17179,7 @@ static void
tions) not implemented.
Store Conditional support for E/F Try View (i.e. indicate failure if FIFO
is full) not implemented.
Signed-off-by: Leon Alrae
---
hw/misc/mips_itu.c | 113 +
1 file changed, 113 insertions(+)
diff --git a/hw/misc/mips_itu.c
/writes directly.
* storage_io: memory-mapped ITC Storage whose address space is
configurable (i.e. enabled/remapped/resized) by writing to
ITCAddressMap{0,1} registers.
Signed-off-by: Leon Alrae
---
default-configs/mips-softmmu.mak | 1 +
default-configs/mips64-softmmu.mak | 1
atch 9: make changes in the CPU to access ITC Tags
Feedback is welcome!
Thanks,
Leon
Leon Alrae (9):
hw/mips: implement ITC Configuration Tags
hw/mips: add ITC Storage Cells
hw/mips: implement ITC Storage - Control View
hw/mips: implement ITC Storage - Empty/Full Sync and Try Views
hw
the CACHE
instruction as NOP. But since CACHE can operate on ITC Tags new
MIPS_HFLAG_ITC_CACHE hflag is introduced to generate the helper only when
CACHE is in the ITC Access mode.
Signed-off-by: Leon Alrae
---
target-mips/cpu.h | 7 +-
target-mips/helper.h| 3 +++
target-mips
and P/V Synchronized Views) each cell contains a bitmap
to track which threads are currently blocked.
Signed-off-by: Leon Alrae
---
hw/misc/mips_itu.c | 17 +
include/hw/misc/mips_itu.h | 25 +
2 files changed, 42 insertions(+)
diff --git a/hw/misc
is 0. P/V Try View does not block the thread, it returns 0 in this case.
Cell's Empty and Full bits are not modified.
Trap bit (i.e. Gating Storage exceptions) not implemented.
Signed-off-by: Leon Alrae
---
hw/misc/mips_itu.c | 68 ++
1
Control view is used to access the ITC Storage Cell Tags. It never causes
the issuing thread to block.
Guest can empty the FIFO cell by setting Empty bit to 1.
Signed-off-by: Leon Alrae
---
hw/misc/mips_itu.c | 104 +
1 file changed, 104
On 03/02/16 17:16, James Hogan wrote:
> Here's a v5 refresh of my FPU/MSA patchset for v2.6. Thanks to all who
> have taken the time to review it so far.
>
> This patchset primarily adds support for FPU and MIPS SIMD Architecture
> (MSA) in MIPS KVM guests to QEMU. It depends on Linux v4.1, specif
interrupt() to clear the MIPS_HFLAG_WRAP
> flag when necessary, according to compute_hflags().
>
> Fixes: 01f728857941 ("target-mips: Status.UX/SX/KX enable 32-bit...")
> Signed-off-by: James Hogan
> Cc: Leon Alrae
> Cc: Aurelien Jarno
> ---
> Note, compute_hflag
d exception loop. The same applies to errors and debug
> exceptions.
>
> Fix by updating mips_cpu_do_interrupt() to clear the MIPS_HFLAG_WRAP
> flag when necessary, according to compute_hflags().
>
> Fixes: 01f728857941 ("target-mips: Status.UX/SX/KX enable 32-bit...")
>
because we forget to flush QEMU TLB.
This patch fixes it.
Signed-off-by: Leon Alrae
---
target-mips/cpu.h | 18 +-
target-mips/op_helper.c | 13 -
2 files changed, 17 insertions(+), 14 deletions(-)
diff --git a/target-mips/cpu.h b/target-mips/cpu.h
index
_do_interrupt() to clear the MIPS_HFLAG_WRAP
flag when necessary, according to compute_hflags().
Fixes: 01f728857941 ("target-mips: Status.UX/SX/KX enable 32-bit...")
Signed-off-by: James Hogan
Cc: Leon Alrae
Cc: Aurelien Jarno
Reviewed-by: Leon Alrae
Signed-off-by: Leon
1:03 +)
MIPS patches 2015-11-24
Changes:
* bugfixes for accessing 64-bit addresses
James Hogan (1):
target-mips: Fix exceptions while UX=0
Leon Alrae (1):
target-mips:
because we forget to flush QEMU TLB.
This patch fixes it.
Signed-off-by: Leon Alrae
---
target-mips/cpu.h | 18 +-
target-mips/op_helper.c | 13 -
2 files changed, 17 insertions(+), 14 deletions(-)
diff --git a/target-mips/cpu.h b/target-mips/cpu.h
index
On 25/11/15 12:57, Dongxue Zhang wrote:
> CP0IntCtl_IPPC1, the last letter should be 'i', not 'one'.
>
> Signed-off-by: Dongxue Zhang
> ---
> target-mips/cpu.h | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/target-mips/cpu.h b/target-mips/cpu.h
> index 89c01f7..17817c3
Hi,
I just noticed significant performance hit with this change. Booting
small system (I tried on system mips only) was usually taking around 20
seconds, now reaches 3 minutes with this change.
Leon
On 09/02/16 12:13, Paolo Bonzini wrote:
> From: Stefan Hajnoczi
>
> Although accesses to ram_li
-
> 1 file changed, 36 insertions(+), 19 deletions(-)
It fixes the performance problem I was seeing:
Tested-by: Leon Alrae
Thanks,
Leon
Hi Miodrag,
Thanks for the fix; I've applied it to the target-mips queue (in future
please send patches inline).
Thanks,
Leon
On 04/01/16 15:52, Miodrag Dinic wrote:
> Hello Aurelien,
>
> thanks for your comments and review.
> Version 2 of the patch is in the attachment.
>
> Diff between versi
clude/hw/i386/pc.h | 2 +-
> migration/ram.c| 2 +-
> target-alpha/fpu_helper.c | 2 +-
> target-mips/kvm.c | 4 +-
> target-mips/msa_helper.c | 36
> target-s390x/kvm.c | 2 +-
> tests/vhost-user-test.c| 2 +-
> 20 files changed, 187 insertions(+), 197 deletions(-)
>
Looks good to me; for MIPS part in patch 1 and 3:
Acked-by: Leon Alrae
Thanks,
Leon
On 12/01/16 14:31, James Hogan wrote:
> Paolo/Leon: This also affects kvm_mips_get_one_ureg64() in patch 5 of my
> MIPS KVM FPU patchset (mips/kvm: Support signed 64-bit KVM registers).
> Are you okay to fix up the conflict when you apply?
I'll fix it while applying to my queue.
Regards,
Leon
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