[Qemu-devel] [PATCH 8/9] target-mips: check CP0 enabled for CACHE instruction also in R6

[Leon Alrae]

Signed-off-by: Leon Alrae <leon.al...@imgtec.com>
---
 target-mips/translate.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/target-mips/translate.c b/target-mips/translate.c
index c6e2951..3fb3744 100644
--- a/target-mips/translate.c
+++ b/target-mips/translate.c
@@ -17179,6 +17179,7 @@ static void decode_opc_special3_r6(CPUMIPSState *env, 
DisasContext *ctx)
         /* Treat as NOP. */
         break;
     case R6_OPC_CACHE:
+        check_cp0_enabled(ctx);
         /* Treat as NOP. */
         break;
     case R6_OPC_SC:
-- 
2.1.0