On 12/11/2014 18:46, Maciej W. Rozycki wrote:
> On Wed, 12 Nov 2014, Andreas Färber wrote:
>
>> Please consistently use "target-mips: " when that's what you're
>> touching. (For hw/mips/ it's less consistent what to use.)
>
> Sure. What about MIPS changes that span files contained within
> tar
On 12/11/2014 21:07, Paolo Bonzini wrote:
>
>
> On 08/10/2014 12:55, Leon Alrae wrote:
>> case OPC_LUI:
>> -tcg_gen_movi_tl(cpu_gpr[rt], imm << 16);
>> -MIPS_DEBUG("lui %s, " TARGET_FMT_lx, regnames[rt], uimm);
>> +
target_ulong);
> }
> if (env->CP0_Config1 & (1 << CP0C1_FP)
> -&& n >= 38 && n < 73) {
> +&& n >= 38 && n < 72) {
> if (n < 70) {
> if (env->CP0_Status & (1 << CP0St_FR)) {
> env->active_fpu.fpr[n - 38].d = tmp;
>
Reviewed-by: Leon Alrae
nore writes. */
> break;
> }
> return sizeof(target_ulong);
>
Reviewed-by: Leon Alrae
lt; CP0C3_VInt),
> .CP0_LLAddr_rw_bitmask = 0,
> .CP0_LLAddr_shift = 4,
> .SYNCI_Step = 32,
>
Reviewed-by: Leon Alrae
branch. */
> #if defined(TARGET_MIPS)
> if ((env->hflags & MIPS_HFLAG_BMASK) != 0 && n > 1) {
> -env->active_tc.PC -= 4;
> +env->active_tc.PC -= (env->hflags & MIPS_HFLAG_B16 ? 2 : 4);
> cpu->icount_decr.u16.low++;
> env->hflags &= ~MIPS_HFLAG_BMASK;
> }
>
Reviewed-by: Leon Alrae
2(mask, CP0St_KSU, 2) == 0x3;
> +
> +if (has_supervisor && extract32(arg1, CP0St_KSU, 2) == 0x3) {
> mask &= ~(3 << CP0St_KSU);
> }
> -mask &= ~(0x0018 & arg1);
> +mask &= ~(((1 << CP0St_SR) | (1 << CP0St_NMI)) & arg1);
> }
>
> val = arg1 & mask;
>
Thanks for fixing and cleaning this up.
Reviewed-by: Leon Alrae
Hi Maciej,
On 10/11/2014 13:46, Maciej W. Rozycki wrote:
> qemu-mips-status.diff
> Index: qemu-git-trunk/target-mips/cpu.h
> ===
> --- qemu-git-trunk.orig/target-mips/cpu.h 2014-11-09 23:44:32.0
> +
> +++ qemu-git-tru
S
> int rd = uMIPS_RD5(ctx->opcode);
> int rs = uMIPS_RS5(ctx->opcode);
>
> -gen_arith_imm(ctx, OPC_ADDIU, rd, rs, 0);
> +gen_arith(ctx, OPC_ADDU, rd, rs, 0);
> }
> break;
> case ANDI16:
Reviewed-by: Leon Alrae
All the patches up to this one have been applied to mips-next branch
(available at git://github.com/lalrae/qemu.git), thanks. I'll go through
the remaining soon.
Regards,
Leon
On 18/11/2014 03:20, Maciej W. Rozycki wrote:
> @@ -19276,6 +19276,10 @@ void mips_cpu_dump_state(CPUState *cs, F
> env->CP0_Status, env->CP0_Cause, env->CP0_EPC);
> cpu_fprintf(f, "Config0 0x%08x Config1 0x%08x LLAddr 0x"
> TARGET_FMT_lx "\n",
> env->CP0
al microMIPS processor that includes an FPU; if so, then it would
> be good to add it to the list our supported configurations).
FYI, there are real CPUs which support microMIPS and include FPU, for
example microAptivUC.
> qemu-mips-config3-isaonexc.diff
Reviewed-by: Leon Alrae
e
statement "if" block. This also applies in other places in this patch.
Otherwise,
Reviewed-by: Leon Alrae
; } while (0)
> @@ -10967,9 +10974,11 @@ static void gen_mips16_restore (DisasCon
> }
> #undef DECR_AND_LOAD
>
> -tcg_gen_addi_tl(cpu_gpr[29], cpu_gpr[29], framesize);
> +tcg_gen_movi_tl(t2, framesize);
> +gen_op_addr_add(ctx, cpu_gpr[29], cpu_gpr[29], t2);
> tcg_temp_free(t0);
> tcg_temp_free(t1);
> +tcg_temp_free(t2);
> }
>
> static void gen_addiupc (DisasContext *ctx, int rx, int imm,
>
Otherwise,
Reviewed-by: Leon Alrae
On 12/11/2014 18:58, Maciej W. Rozycki wrote:
> On Wed, 12 Nov 2014, Peter Maydell wrote:
>
>>> @@ -208,12 +206,12 @@ int cpu_load(QEMUFile *f, void *opaque,
>>> MIPSCPU *cpu = mips_env_get_cpu(env);
>>> int i;
>>>
>>> -if (version_id < 3) {
>>> +if (version_id != CPU_SAVE_VERSIO
> env->active_fpu.fcr31 = tmp & 0xFF83;
> @@ -107,6 +100,12 @@ int mips_cpu_gdb_write_register(CPUState
> case 71:
> /* FIR is read-only. Ignore writes. */
> break;
> +default:
> +if (env->CP0_Status & (1 << CP0St_FR))
> +env->active_fpu.fpr[n - 38].d = tmp;
> +else
> +env->active_fpu.fpr[n - 38].w[FP_ENDIAN_IDX] = tmp;
Braces are missing here.
> +break;
> }
> return sizeof(target_ulong);
> }
>
Otherwise,
Reviewed-by: Leon Alrae
amp; (0xff << CP0VPECo_TargTC);
> +uint32_t mask = env->CP0_Status_rw_bitmask & ~0xf118;
> CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
>
> -other->CP0_Status = arg1 & ~0xf118;
> +other->CP0_Status = (other->CP0_Status & ~mask) | (arg1 & mask);
> sync_c0_status(env, other, other_tc);
> }
>
>
Reviewed-by: Leon Alrae
00
> @@ -3929,7 +3929,7 @@ int main(int argc, char **argv, char **e
> #endif
> #elif defined(TARGET_MIPS)
> #if defined(TARGET_ABI_MIPSN32) || defined(TARGET_ABI_MIPSN64)
> - cpu_model = "20Kc";
> +cpu_model = "5KEf";
> #else
> cpu_model = "24Kf";
> #endif
>
Reviewed-by: Leon Alrae
gdbstub.c
> Index: qemu-git-trunk/target-mips/op_helper.c
> Index: qemu-git-trunk/target-mips/translate.c
Reviewed-by: Leon Alrae
evel code generated should be the same if
> not better. The local pointer will help with a follow-up change that
> would otherwise make line wrapping unbearable.
>
> Please apply,
>
> Maciej
>
> qemu-mips-msa-helper-status.diff
> Index: qemu-git-trunk/target-mips/msa_helper.c
Reviewed-by: Leon Alrae
ctx.ulri = (env->CP0_Config3 >> CP0C3_ULRI) & 1;
> restore_cpu_state(env, &ctx);
> #ifdef CONFIG_USER_ONLY
> ctx.mem_idx = MIPS_HFLAG_UM;
>
Reviewed-by: Leon Alrae
Hi Maciej,
On 11/12/14 16:18, Maciej W. Rozycki wrote:
> Hi,
>
> The current trunk QEMU fails to run in the system emulation mode for
> the MIPS/Malta (mips64-softmmu) target. It fails right away:
>
> $ qemu-system -M malta -m 256 -k /dev/null -kernel vmlinux-3.2.0-4-4kc-malta
> -nographic -
Signed-off-by: Leon Alrae
---
disas/mips.c | 7 ---
1 file changed, 7 deletions(-)
diff --git a/disas/mips.c b/disas/mips.c
index 2614c52..b94d5d9 100644
--- a/disas/mips.c
+++ b/disas/mips.c
@@ -3801,13 +3801,6 @@ static const char * const mips_hwr_names_mips3264r2[32] =
"$24&qu
ing: unused variable 'mips16_to_32_reg_map'
[-Wunused-const-variable]
target-mips/helper.c:393:27: warning: unused variable 'excp_names'
[-Wunused-const-variable]
Patch #3 in the series additionally removes block of code guarded by #if 0 that
has never been used since it was i
Signed-off-by: Leon Alrae
---
target-mips/translate.c | 4 +---
1 file changed, 1 insertion(+), 3 deletions(-)
diff --git a/target-mips/translate.c b/target-mips/translate.c
index f65ed84..1205909 100644
--- a/target-mips/translate.c
+++ b/target-mips/translate.c
@@ -1882,10 +1882,8 @@ static
The array was "used" in a block of code which has never been enabled. Therefore
removing the array as well as 700 lines of never used code.
Signed-off-by: Leon Alrae
---
disas/mips.c | 721 ---
1 file changed, 721 deletions(-)
Signed-off-by: Leon Alrae
---
target-mips/helper.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target-mips/helper.c b/target-mips/helper.c
index c4b3658..7d26705 100644
--- a/target-mips/helper.c
+++ b/target-mips/helper.c
@@ -388,7 +388,6 @@ hwaddr
On 05/12/2014 18:55, Maciej W. Rozycki wrote:
> On Thu, 4 Dec 2014, Leon Alrae wrote:
>
>>> Index: qemu-git-trunk/target-mips/translate.c
>>> ===
>>> --- qemu-git-trunk.orig/target-mips/tran
On 12/12/2014 12:25, Peter Maydell wrote:
> On 12 December 2014 at 09:30, Leon Alrae wrote:
>> The array was "used" in a block of code which has never been enabled.
>> Therefore
>> removing the array as well as 700 lines of never used code.
>
> That's q
On 12/12/2014 14:51, Peter Maydell wrote:
> On 12 December 2014 at 14:28, Leon Alrae wrote:
>> On 12/12/2014 12:25, Peter Maydell wrote:
>>> On 12 December 2014 at 09:30, Leon Alrae wrote:
>>>> The array was "used" in a block of code which has never bee
This array is used by print_mips16_insn_arg() which is guarded by #if 0.
Therefore doing the same with the array as it generates clang warnings.
Signed-off-by: Leon Alrae
---
disas/mips.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/disas/mips.c b/disas/mips.c
index
On 12/12/2014 15:53, Peter Maydell wrote:
> On 12 December 2014 at 15:52, Leon Alrae wrote:
>> On 12/12/2014 14:51, Peter Maydell wrote:
>>> Failing that, the best source for a mips16 disassembler is
>>> going to be "fix the bugs in the currently disabled code we
Hi Daniel,
On 15/12/2014 14:03, Daniel Sanders wrote:
> Hi,
>
>
>
> FWIW, the R6000 was a MIPS-II processor but I understand there was never
> a proper manual for it. http://www.linux-mips.org/wiki/R6000 has a small
> amount of information but not enough to accurately fill in qemu's structure.
5:20 +)
MIPS patches 2014-12-16
Changes:
* number of bug fixes and minor improvements mainly in microMIPS, mips16
and gdbstub
* make 5KEf default CPU in 64-bit linux-user
* cleanups
----
Leon Alrae (4):
t
From: "Maciej W. Rozycki"
Signed-off-by: Maciej W. Rozycki
Signed-off-by: Leon Alrae
---
target-mips/translate.c | 13 -
1 file changed, 8 insertions(+), 5 deletions(-)
diff --git a/target-mips/translate.c b/target-mips/translate.c
index 643214a..a5a5ca4 100644
--- a/t
From: "Maciej W. Rozycki"
CP1.FIR is read-only in hardware so gdbstub must respect it. We already
respect it for CTC1 instructions, so do it here too.
Signed-off-by: Maciej W. Rozycki
Reviewed-by: Leon Alrae
Signed-off-by: Leon Alrae
---
target-mips/gdbstub.c | 2 +-
1 file
From: "Maciej W. Rozycki"
Move the call to `update_fcr31' in `helper_float_cvtw_s' after the
exception flag check, for consistency with the remaining helpers that do
it last too.
Signed-off-by: Maciej W. Rozycki
Signed-off-by: Leon Alrae
---
target-mips/op_helper.c | 2 +
ozycki
Reviewed-by: Leon Alrae
Signed-off-by: Leon Alrae
---
target-mips/gdbstub.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target-mips/gdbstub.c b/target-mips/gdbstub.c
index f65fec2..7e3a604 100644
--- a/target-mips/gdbstub.c
+++ b/target-mips/gdbstu
rts of the microarchitecture, in particular the
pipeline, stayed unchanged. Or to put it another way, the difference
between a 5K and a 5KE CPU corresponds to one between a 4K and a 4KE
CPU, except for the 64-bit rather than 32-bit ISA.
Signed-off-by: Maciej W. Rozycki
Signed-off-by: Leon Alrae
---
t
From: "Maciej W. Rozycki"
Remove the `FLOAT_OP' macro, unused since commit
b6d96beda3a6cbf20a2d04a609eff78adebd8859 [Use temporary registers for
the MIPS FPU emulation.].
Signed-off-by: Maciej W. Rozycki
Signed-off-by: Leon Alrae
---
target-mips/op_helper.c | 2 --
1
From: "Maciej W. Rozycki"
Include CP0.Config2 through CP0.Config5 registers in the register dump
produced with the `info registers' monitor command. Align vertically
with the registers already output.
Signed-off-by: Maciej W. Rozycki
Signed-off-by: Leon Alrae
---
target-mips/
From: "Maciej W. Rozycki"
Rewrite the FPU register access parts of `mips_cpu_gdb_read_register'
and `mips_cpu_gdb_write_register' for consistency between each other.
Signed-off-by: Maciej W. Rozycki
Reviewed-by: Leon Alrae
Signed-off-by: Leon Alrae
---
target
Signed-off-by: Nathan Froyd
Signed-off-by: Maciej W. Rozycki
Reviewed-by: Leon Alrae
Signed-off-by: Leon Alrae
---
target-mips/translate.c | 3 ++-
translate-all.c | 2 +-
2 files changed, 3 insertions(+), 2 deletions(-)
diff --git a/target-mips/translate.c b/target-mips/translate.
reexisting order, and later
on even more operations sprinkled across the file. Revert the mess by
moving FMA operations to a new ternary class inserted after the binary
class and move the misplaced unary and binary operations to where they
belong.
Signed-off-by: Maciej W. Rozycki
Signed-off-by:
Status
Register Field Descriptions", pp. 210-211.
Signed-off-by: Maciej W. Rozycki
Reviewed-by: Leon Alrae
Signed-off-by: Leon Alrae
---
target-mips/op_helper.c | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/target-mips/op_helper.c b/target-mips/op_helper.c
index d25424
From: "Maciej W. Rozycki"
Set DisasContext's ulri member to 0 or 1 as with other bool members.
Signed-off-by: Maciej W. Rozycki
Reviewed-by: Leon Alrae
Signed-off-by: Leon Alrae
---
target-mips/translate.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --gi
registers, ignoring any read-only locations, and do not synchronise
the environment to evaluate side effects. We also write these registers
in the user emulation mode even though a real kernel presents them as
read only.
Signed-off-by: Maciej W. Rozycki
Signed-off-by: Leon Alrae
---
target-mips/cpu.h
er 64-bit values.
This also serves as an optimization as one op is produced in generated
code rather than two (again, unless `rs' is 0, where it doesn't change
anything).
Signed-off-by: Maciej W. Rozycki
Reviewed-by: Leon Alrae
Signed-off-by: Leon Alrae
---
target-mips/translate.c |
sing only.
Signed-off-by: Maciej W. Rozycki
Reviewed-by: Leon Alrae
Signed-off-by: Leon Alrae
---
target-mips/helper.h| 1 +
target-mips/op_helper.c | 8
target-mips/translate.c | 8 ++--
3 files changed, 15 insertions(+), 2 deletions(-)
diff --git a/target-mips/helper.h b/t
Signed-off-by: Leon Alrae
Reviewed-by: Peter Maydell
---
target-mips/helper.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target-mips/helper.c b/target-mips/helper.c
index c4b3658..7d26705 100644
--- a/target-mips/helper.c
+++ b/target-mips/helper.c
@@ -388,7 +388,6
Reviewed-by: Leon Alrae
Signed-off-by: Leon Alrae
---
target-mips/cpu.h | 7 ++--
target-mips/helper.c| 15 +--
target-mips/translate.c | 107
3 files changed, 114 insertions(+), 15 deletions(-)
diff --git a/target-mips/cpu.h b/t
From: "Maciej W. Rozycki"
Make CP0.Status writes made with the MTTC0 instruction respect this
register's mask just like all the other places. Also preserve the
current values of masked out bits.
Signed-off-by: Maciej W. Rozycki
Reviewed-by: Leon Alrae
Signed-off-by: Leon Alr
From: "Maciej W. Rozycki"
Replace the 20Kc original MIPS64 ISA processor used for 64-bit user
emulation with the 5KEf processor that implements the MIPS64r2 ISA,
complementing the choice of the 24Kf processor for 32-bit emulation.
Signed-off-by: Maciej W. Rozycki
Reviewed-by:
redundant RESTORE_ROUNDING_MODE
macro.
Signed-off-by: Thomas Schwinge
Signed-off-by: Maciej W. Rozycki
Reviewed-by: Leon Alrae
Signed-off-by: Leon Alrae
---
target-mips/cpu.h | 12
target-mips/gdbstub.c | 8 +++-
target-mips/op_helper.c | 12
target-mips/transl
d-by: Leon Alrae
Signed-off-by: Leon Alrae
---
target-mips/cpu.h | 8 +---
target-mips/translate.c | 19 ++-
2 files changed, 19 insertions(+), 8 deletions(-)
diff --git a/target-mips/cpu.h b/target-mips/cpu.h
index e59cb4c..f8cf143 100644
--- a/target-mips/cpu.h
+++ b/t
Signed-off-by: Leon Alrae
Reviewed-by: Peter Maydell
---
target-mips/translate.c | 4 +---
1 file changed, 1 insertion(+), 3 deletions(-)
diff --git a/target-mips/translate.c b/target-mips/translate.c
index f65ed84..1205909 100644
--- a/target-mips/translate.c
+++ b/target-mips/translate.c
From: "Maciej W. Rozycki"
Reduce line wrapping throughout MSA helper macros by using a local float
status pointer rather than referring to the float status through the
environment each time. No functional change.
Signed-off-by: Maciej W. Rozycki
Reviewed-by: Leon Alrae
Signed-of
This array is used by print_mips16_insn_arg() which is guarded by #if 0.
Therefore doing the same with the array as it generates clang warnings.
Signed-off-by: Leon Alrae
---
disas/mips.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/disas/mips.c b/disas/mips.c
index
Signed-off-by: Leon Alrae
Reviewed-by: Peter Maydell
---
disas/mips.c | 7 ---
1 file changed, 7 deletions(-)
diff --git a/disas/mips.c b/disas/mips.c
index 2614c52..b94d5d9 100644
--- a/disas/mips.c
+++ b/disas/mips.c
@@ -3801,13 +3801,6 @@ static const char * const
From: "Maciej W. Rozycki"
Signed-off-by: Maciej W. Rozycki
Signed-off-by: Leon Alrae
---
target-mips/translate.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target-mips/translate.c b/target-mips/translate.c
index f0b8e6f..643214a 100644
--- a/target-mips/t
From: "Maciej W. Rozycki"
Make the data type used for the CP0.Config4 and CP0.Config5 registers
and their mask signed, for consistency with the remaining 32-bit CP0
registers, like CP0.Config0, etc.
Signed-off-by: Maciej W. Rozycki
Reviewed-by: Leon Alrae
Signed-off-by:
From: "Maciej W. Rozycki"
Signed-off-by: Maciej W. Rozycki
Signed-off-by: Leon Alrae
---
target-mips/translate_init.c | 40 +---
1 file changed, 21 insertions(+), 19 deletions(-)
diff --git a/target-mips/translate_init.c b/target-mips/transl
us and CP0.Cause registers, so these features are not marked,
making our support diverge from real hardware.
Signed-off-by: Sandra Loosemore
Signed-off-by: Maciej W. Rozycki
Reviewed-by: Leon Alrae
Signed-off-by: Leon Alrae
---
target-mips/translate_i
From: "Maciej W. Rozycki"
Enable vectored interrupt support for the 74Kf CPU, reflecting hardware.
Signed-off-by: Maciej W. Rozycki
Reviewed-by: Leon Alrae
Signed-off-by: Leon Alrae
---
target-mips/translate_init.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --gi
On 15/12/2014 18:07, Maciej W. Rozycki wrote:
> Great! I have now posted all the changes I had outstanding, there will
> be no more.
Thanks for the patches, they are very valuable - especially
IEEE 754-2008, it's a significant improvement for MIPS! I'll take a
closer look at the remaining ones,
On 02/04/2015 17:47, Liviu Ionescu wrote:
>
>> On 02 Apr 2015, at 17:27, Matthew Fortune wrote:
>>
>> Liviu Ionescu writes:
>>> for completeness:
>>>
>>> ilg-mbp:gnuarmeclipse-qemu.git ilg$ "/Applications/GNU ARM
>>> Eclipse/QEMU/2.2.91-20150402-dev/bin/qemu-system-gnuarmeclipse" -
>>> verbo
On 15/04/2015 10:09, Liviu Ionescu wrote:
> Peter/Leon,
>
> I'm planning for my future releases, and, to avoid incompatible versions, I
> would like to help with the semihosting configuration issue, to speed up
> things. is there any chance to close this issue in the near future?
I'm hoping so
On 15/04/2015 13:06, Liviu Ionescu wrote:
>
>> On 15 Apr 2015, at 14:53, Leon Alrae wrote:
>>
>> On 15/04/2015 10:09, Liviu Ionescu wrote:
>>> Peter/Leon,
>>>
>>> I'm planning for my future releases, and, to avoid incompatible ver
On 15/04/2015 17:08, Liviu Ionescu wrote:
>
>> On 15 Apr 2015, at 15:49, Leon Alrae wrote:
>>
>> ... If there aren't any objections for the proposed solution, then let's
>> just cook up the patch.
>
> the changes related to moving --semihosti
On 15/04/2015 10:35, James Hogan wrote:
> On 13/04/15 12:29, vt wrote:
>> Hi, guys
>>
>> I saw the architecture code about mips in the qemu and kvm modules, so it is
>> no doubt that mips cpu can be supported.
>> But I wonder if anyone have used qemu/kvm virtualization with China loongson
>> pr
On 16/04/2015 13:02, Paolo Bonzini wrote:
>
>
> On 16/04/2015 13:07, Leon Alrae wrote:
>> Since I also haven't had a chance to test Loongson emulation, I thought
>> I'd give it a try (TCG only, Loongson-2E cpu and fulong2e machine).
>>
>> Good news
On 16/04/15 16:17, Paolo Bonzini wrote:
>
>
> On 16/04/2015 17:05, Leon Alrae wrote:
>> On 16/04/2015 13:02, Paolo Bonzini wrote:
>>>
>>>
>>> On 16/04/2015 13:07, Leon Alrae wrote:
>>>> Since I also haven't had a chance to test Loo
patches 2015-04-17
Changes:
* fix broken fulong2e
Leon Alrae (1):
mips: fix broken fulong2e machine
hw/pci-host/bonito.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
After commit 5312bd8 the bonito_readl() and bonito_writel() have been
accessing incorrect addresses. Consequently QEMU is crashing when trying
to boot Linux kernel on fulong2e machine.
Cc: qemu-sta...@nongnu.org
Signed-off-by: Paolo Bonzini
Signed-off-by: Leon Alrae
---
hw/pci-host/bonito.c
On 17/04/2015 11:42, Peter Maydell wrote:
> On 17 April 2015 at 10:46, Leon Alrae wrote:
>> After commit 5312bd8 the bonito_readl() and bonito_writel() have been
>> accessing incorrect addresses. Consequently QEMU is crashing when trying
>> to boot Linux kernel on fulong2e ma
On 17/04/2015 11:58, Peter Maydell wrote:
> On 17 April 2015 at 11:49, Leon Alrae wrote:
>> On 17/04/2015 11:42, Peter Maydell wrote:
>>> On 17 April 2015 at 10:46, Leon Alrae wrote:
>>>> After commit 5312bd8 the bonito_readl() and bonito_writel() have been
>
Hi,
The machine was broken for a long time (since v1.1), it would be great
to have it working again in v2.3.
v2: modified "From:" to indicate the actual author of the change
Thanks,
Leon
Cc: Peter Maydell
The following changes since commit b8df9208f357d2b36e1b19634aea973618dc7ba8:
Update v
From: Paolo Bonzini
After commit 5312bd8 the bonito_readl() and bonito_writel() have been
accessing incorrect addresses. Consequently QEMU is crashing when trying
to boot Linux kernel on fulong2e machine.
Cc: qemu-sta...@nongnu.org
Signed-off-by: Paolo Bonzini
Signed-off-by: Leon Alrae
On 16/04/2015 15:22, Peter Maydell wrote:
> On 15 April 2015 at 10:09, Liviu Ionescu wrote:
>> we currently have two solutions:
>>
>> - multiple: --semihosting-config arg="..."
>> - a single option, placed at the end, and followed by any number
>> of arguments: --semihosting-cmdline $@ \n
>>
>>
MIPS architectural feature allowing emulation of Status.FR=0 on a CPU
with Status.FR hardwired to 1.
v2:
* move functions and drop prototypes (James)
* fix declaration after code (James)
Leon Alrae (2):
target-mips: move group of functions above gen_load_fpr32()
target-mips: add Config5.FRE
Instructions
exception.
Config5.UFE: Allows user to write/read Config5.FRE using CTC1/CFC1
instructions.
Enable the feature in MIPS64R6-generic CPU.
Signed-off-by: Leon Alrae
---
target-mips/cpu.h| 13 +-
target-mips/op_helper.c | 34 +
target-mips
Move the "Tests" group of functions so that gen_load_fpr32() and
gen_store_fpr32() can use generate_exception().
Signed-off-by: Leon Alrae
---
target-mips/translate.c | 118
1 file changed, 58 insertions(+), 60 deletions(-)
diff --gi
Hi Christopher,
On 09/04/2015 18:57, Peter Maydell wrote:
> On 9 April 2015 at 18:23, Christopher Covington
> wrote:
>> On Fri, Mar 27, 2015 at 12:40 PM, Peter Maydell
>> wrote:
>>> You need to have the semihosting_enabled check here rather
>>> than in the do_interrupt code, because otherwise we
On 21/04/2015 19:08, Liviu Ionescu wrote:
>
>> On 21 Apr 2015, at 16:34, Leon Alrae wrote:
>>
>> I'll resend the patch with dropped "RFC" as I would really like to go
>> forward and finally close this issue.
>
> perhaps you should first take a c
On 28/04/2015 10:11, arei.gong...@huawei.com wrote:
> From: Gonglei
>
> Coveristy reports that variable prom_buf/params_buf going
> out of scope leaks the storage it points to.
>
> Cc: Aurelien Jarno
> Cc: Leon Alrae
> Signed-off-by: Gonglei
> ---
> hw/mips/mi
.PageGrain.ELPA = 0) then assuming 32-bit Address Mode.
For MIPS64 default PABITS are 36.
env->PABITS value is constant and indicates maximum PABITS available on
a core, whereas env->PAMask is calculated from env->PABITS and is also
affected by CP0.PageGrain.ELPA.
Signed-off-by: Leon Alrae
--
,
Leon
Leon Alrae (7):
target-mips: extend selected CP0 registers to 64-bits in MIPS32
target-mips: support Page Frame Number Extension field
target-mips: add CP0.PageGrain.ELPA support
target-mips: add MTHC0 and MFHC0 instructions
target-mips: correct MFC0 for CP0.EntryLo in MIPS64
Extend EntryLo0, EntryLo1, LLAddr and TagLo from 32 to 64 bits in MIPS32.
Signed-off-by: Leon Alrae
---
target-mips/cpu.h | 14 +++---
target-mips/machine.c | 20 ++--
target-mips/op_helper.c | 8
target-mips/translate.c | 5 +++--
4 files changed, 24
Since PFNX is now supported the bits 31:30 have to be cleared.
Signed-off-by: Leon Alrae
---
target-mips/translate.c | 12 ++--
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/target-mips/translate.c b/target-mips/translate.c
index f95b655..a41fc98 100644
--- a/target-mips
Enable XPA in MIPS32R5-generic and LPA in MIPS64R6-generic.
Signed-off-by: Leon Alrae
---
target-mips/translate_init.c | 15 +--
1 file changed, 9 insertions(+), 6 deletions(-)
diff --git a/target-mips/translate_init.c b/target-mips/translate_init.c
index af6fb7a..8674118 100644
Update tlb->PFN to contain PFN concatenated with PFNX. PFNX is 0 if large
physical address is not supported.
Signed-off-by: Leon Alrae
---
target-mips/op_helper.c | 32 ++--
1 file changed, 26 insertions(+), 6 deletions(-)
diff --git a/target-mips/op_helper.
and XI, which were shifted to bits
63:62 by MTC0 to EntryLo0 or EntryLo1. Therefore creating separate
functions generating for EntryLo0 and EntryLo1.
Signed-off-by: Leon Alrae
---
disas/mips.c| 2 +
target-mips/cpu.h | 1 +
target-mips/translate.c | 216
Signed-off-by: Leon Alrae
---
target-mips/translate_init.c | 9 -
1 file changed, 9 deletions(-)
diff --git a/target-mips/translate_init.c b/target-mips/translate_init.c
index 8e088c9..af6fb7a 100644
--- a/target-mips/translate_init.c
+++ b/target-mips/translate_init.c
@@ -553,9 +553,6
Hi James,
On 28/04/2015 14:35, James Hogan wrote:
>
>
> On 28/04/15 13:41, Leon Alrae wrote:
>> Update tlb->PFN to contain PFN concatenated with PFNX. PFNX is 0 if large
>> physical address is not supported.
>>
>> Signed-off-by: Leon Alrae
>
Hi James,
On 28/04/2015 16:08, James Hogan wrote:
>> diff --git a/target-mips/mips-defs.h b/target-mips/mips-defs.h
>> index 1784227..20aa87c 100644
>> --- a/target-mips/mips-defs.h
>> +++ b/target-mips/mips-defs.h
>> @@ -10,11 +10,11 @@
>>
>> #if defined(TARGET_MIPS64)
>> #define TARGET_LONG_
On 28/04/2015 16:52, James Hogan wrote:
>> diff --git a/disas/mips.c b/disas/mips.c
>> index 1afe0c5..c236495 100644
>> --- a/disas/mips.c
>> +++ b/disas/mips.c
>> @@ -2238,6 +2238,8 @@ const struct mips_opcode mips_builtin_opcodes[] =
>> {"ceil.l.s", "D,S", 0x460a, 0x003f, WR_D|RD_S|FP_S|
Hi Hervé,
On 25/03/2015 14:13, Leon Alrae wrote:
> On 05/03/2015 22:13, Hervé Poussineau wrote:
>> Hi,
>>
>> This patchset improves dp8393x network card emulation to current QEMU
>> standards,
>> mostly decouples it from MIPS rc4030 chipset emulatio
> I think I wasn't expecting that because 32-bit kernels can run on MIPS64
> hardware using the same mfc0/mfhc0 instructions, so having a single
> internal representation in QEMU seemed simpler & less fragile, since the
> same source code needs to support both MIPS32 and MIPS64 anyway.
In my opini
On 14/05/2015 20:12, Richard Henderson wrote:
> /* We know both pages are present and writable. */
> if (eaddr == baddr + 15) {
> /* Consecutive pages in RAM. */
> memcpy(baddr, register, 16);
> } else {
> /* Someone's doing an MSA store to device memory. */
> for (
On 15/05/2015 14:43, Richard Henderson wrote:
> On 05/15/2015 05:09 AM, Leon Alrae wrote:
>> On 14/05/2015 20:12, Richard Henderson wrote:
>>> /* We know both pages are present and writable. */
>>> if (eaddr == baddr + 15) {
>>> /* Consecutive page
On 18/05/2015 17:18, Peter Maydell wrote:
> On 8 May 2015 at 12:41, Leon Alrae wrote:
>> Add new "arg" sub-argument to the --semihosting-config allowing to pass
>> multiple input argument separately. It is required for example by UHI
>> semihosting to construct arg
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