Create VMStateDescription for MIPS CPU. The new structure contains exactly the
same fields as before, therefore leaving existing version_id.
Signed-off-by: Leon Alrae
---
target-mips/cpu-qom.h | 4 +
target-mips/cpu.c | 1 +
target-mips/cpu.h | 2 -
target-mips/machine.c | 567
s are welcome.
Thanks,
Leon
v2:
* use cc->vmsd rather than dc->vmsd (Andreas Faerber)
* avoid saving TCG-related state (Richard Henderson)
Leon Alrae (2):
target-mips: replace cpu_save/cpu_load with VMStateDescription
target-mips: add missing MSACSR and restore fp_status and hflags
targ
Hi Michael,
On 24/02/2015 21:47, Michael Roth wrote:
> Hi everyone,
>
> The following new patches are queued for QEMU stable v2.2.1:
>
> https://github.com/mdroth/qemu/commits/stable-2.2-staging
>
> The release is planned for 2015-03-10:
>
> http://wiki.qemu.org/Planning/2.2
>
> Please re
On 26/02/2015 11:35, Paolo Bonzini wrote:
>
>
> On 25/02/2015 18:16, Leon Alrae wrote:
>> Hi,
>>
>> On 16/02/2015 18:17, Paolo Bonzini wrote:
>>> This needs to go away sooner or later, but one complication is the
>>> complex VFIO data structures that
ogram name. However, if
no arguments are passed then argument count will be 0.
Also tweak Malta's pseudo-bootloader. On CPU reset the $4 register is set to -1
when semihosting is enabled in order to indicate that the UHI operations should
be used to obtain input arguments.
Signed-off-by: Leon
;MIPS Toolchain, MD01069 UHI Reference Manual", Version: 1.0.14
The manual is available here:
http://prplfoundation.org/wiki/MIPS_documentation
Regards,
Leon
Leon Alrae (2):
target-mips: add Unified Hosting Interface (UHI) support
target-mips: add "-semihosting-arg" optio
s
and will unwind and forward UHI SYSCALL exceptions to the exception
vector that was installed prior to running the application.
Signed-off-by: Matthew Fortune
Signed-off-by: Leon Alrae
---
hw/mips/mips_malta.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/mips/mips_ma
From: "Maciej W. Rozycki"
Correct addresses passed around in semihosting to use a data type suitable
for both 32-bit and 64-bit targets.
Signed-off-by: Maciej W. Rozycki
Signed-off-by: Leon Alrae
---
Maciej,
I kept the same fix locally. I'm replacing it in this patchset with y
Add UHI semihosting support for MIPS. QEMU run with "-semihosting" option will
alter the behaviour of SDBBP 1 instruction -- UHI operation will be called
instead of generating a debug exception.
This commit implements all UHI operations apart from Argc, Argnlen and Argn.
Signed-of
The test is supposed to terminate TB if the end of the page is reached.
However, with current implementation it may never succeed for microMIPS or
mips16.
Reported-by: Richard Henderson
Signed-off-by: Leon Alrae
---
target-mips/translate.c | 5 -
1 file changed, 4 insertions(+), 1 deletion
Signed-off-by: Leon Alrae
---
target-mips/op_helper.c | 10 +++---
1 file changed, 7 insertions(+), 3 deletions(-)
diff --git a/target-mips/op_helper.c b/target-mips/op_helper.c
index ea7d95f..73a8e45 100644
--- a/target-mips/op_helper.c
+++ b/target-mips/op_helper.c
@@ -304,16 +304,20
BadVAddr is supposed to capture the most recent address that caused
the exception. Currently this is not happening as translation is not stopped
and BadVAddr is updated with subsequent addresses.
Signed-off-by: Leon Alrae
---
target-mips/translate.c | 1 +
1 file changed, 1 insertion(+)
diff
Signed-off-by: Leon Alrae
---
target-mips/translate.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/target-mips/translate.c b/target-mips/translate.c
index 635192c..77d89be 100644
--- a/target-mips/translate.c
+++ b/target-mips/translate.c
@@ -4947,7 +4947,7 @@ static
Using rs = -1 in gen_logic_imm() for microMIPS LUI instruction is dangerous
and may bite us when implementing microMIPS R6 because in R6 AUI and LUI
are distinguished by rs value. Therefore use 0 for safety.
Reported-by: Paolo Bonzini
Signed-off-by: Leon Alrae
---
target-mips/translate.c | 2
Recently added CP0.BadInstr and CP0.BadInstrP registers ended up in cpu_load()
under different offset than in cpu_save(). These and all registers between were
incorrectly restored.
Signed-off-by: Leon Alrae
---
target-mips/machine.c | 6 --
1 file changed, 4 insertions(+), 2 deletions
On 28/01/2015 00:14, Maciej W. Rozycki wrote:
> On Mon, 26 Jan 2015, Leon Alrae wrote:
>
>> The test is supposed to terminate TB if the end of the page is reached.
>> However, with current implementation it may never succeed for microMIPS or
>> mips16.
>>
>
Convert MIPS CPU to use VMState. The saved fields are the same as before, with
one exception -- for FPU actually MSA vector registers are saved. This is
because FP registers are mapped on the MSA vector registers.
Signed-off-by: Leon Alrae
---
Hi,
This is a first cut of MIPS CPU state described
u/softfloat-specialize.h
Reviewed-by: Leon Alrae
On 28/01/2015 23:11, Maciej W. Rozycki wrote:
>> @@ -4947,7 +4947,7 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int
>> reg, int sel)
>> #if defined(TARGET_MIPS64)
>> if (ctx->rxi) {
>> TCGv tmp = tcg_temp_new();
>> -tcg_gen_andi_tl(tmp, arg,
>
> [1] "IEEE Standard for Floating-Point Arithmetic", IEEE Computer
> Society, IEEE Std 754-2008, 29 August 2008, pp. 21-22
>
> [2] same, p. 37
>
> [3] same, p. 30
>
> Signed-off-by: Maciej W. Rozycki
> ---
> This is in particular how MIPS hardware operates, other processors
> supposedly do the same if they claim compliance to IEEE 754.
>
> Please apply.
>
> qemu-softfloat-convert-snan.diff
> Index: qemu-git-trunk/fpu/softfloat.c
Reviewed-by: Leon Alrae
ge we clear MIPS_HFLAG_BMASK in execution-time hflags if
instruction in delay or forbidden slot wants to terminate tb for some reason
(i.e. ctx->bstate != BS_NONE).
Also, die early and loudly if "unknown branch" is encountered as this should
never happen.
Signed-off-by: Leon Alrae
---
targ
On 12/12/2014 19:34, Maciej W. Rozycki wrote:
> Mechanically replace `*_default_nan' variables with inline functions and
> convert references accordingly. Use `__inline__' rather than `inline'
> so that the latter does not cause the definitions to become static as a
> result of macro expansion,
ure.
Reported-by: Daniel Sanders
Signed-off-by: Leon Alrae
Tested-by: Daniel Sanders
---
linux-user/syscall_defs.h | 86 +++
1 file changed, 19 insertions(+), 67 deletions(-)
diff --git a/linux-user/syscall_defs.h b/linux-user/syscall_defs.h
i
On 01/02/2015 08:12, Hervé Poussineau wrote:
> Hi,
>
> This patchset removes the isa_mem_base variable in VGA display devices.
> This variable is a global variable telling at which address is the
> ISA memory base address in the system memory address space.
>
> Once removed, we're paving the way
On 11/12/2014 00:21, Maciej W. Rozycki wrote:
> Rework the MIPS ABIs and CPU emulations available according to the
> following target list:
>
> - mips|mipsel -- 32-bit CPUs only, system and user emulation mode,
>o32 user ABI,
>
> - mips64|mips64el -- 32-bit and 6
On 09/12/2014 01:56, Maciej W. Rozycki wrote:
> +if (info->elf_flags & EF_MIPS_NAN2008)
> +env->active_fpu.fcr31 |=
> +(1 << FCR31_NAN2008) & env->active_fpu.fcr31_rw_bitmask;
> +else
> +env->active_fpu.fcr31 &=
> +~((1 << FCR3
On 09/02/2015 20:55, Maciej W. Rozycki wrote:
>>> +uint32_t helper_float_chs_s(CPUMIPSState *env, uint32_t fst0)
>>> +{
>>> +uint32_t fst1;
>>> +
>>> +fst1 = float32_sub(0, fst0, &env->active_fpu.fp_status);
>>> +update_fcr31(env, GETPC());
>>> +return fst1;
>>> +}
>>
>> I think the
On 10/02/2015 14:30, Maciej W. Rozycki wrote:
> On Tue, 10 Feb 2015, Leon Alrae wrote:
>
>>> These cases could be addressed by either replacing subtraction from 0.0
>>> with multiplication by -1.0, or by tweaking the rounding mode as needed
>>> temporarily.
PC needs to be saved if an exception can be generated by an helper.
This fixes a problem related to resuming the execution at unexpected address
after an exception (caused by MSA load/store instruction) has been serviced.
Signed-off-by: Leon Alrae
---
target-mips/translate.c | 2 ++
1 file
CP0.BadVAddr is supposed to capture the most recent virtual address that caused
the exception. Currently this does not work correctly for unaligned instruction
fetch as translation is not stopped and CP0.BadVAddr is updated with subsequent
addresses.
Signed-off-by: Leon Alrae
---
target-mips
ge we clear MIPS_HFLAG_BMASK in execution-time hflags if
instruction in delay or forbidden slot wants to terminate tb for some reason
(i.e. ctx->bstate != BS_NONE).
Also, die early and loudly if "unknown branch" is encountered as this should
never happen.
Signed-off-by: Leon Alrae
---
targ
8:15 +)
MIPS patches 2015-03-18
Changes:
* bug fixes
----
Leon Alrae (3):
target-mips: fix CP0.BadVAddr by stopping translation on Address Error
target-mips: fix hflags m
Currently qemu-system-mips aborts if it fails to find efi-pcnet.rom file which
does not make sense. NIC on Malta board should not require x86 firmware.
Reported-by: Maciej W. Rozycki
Suggested-by: Gerd Hoffmann
Signed-off-by: Leon Alrae
---
Hi,
This fixes a problem reported some time ago
New threads always point at the same env which is incorrect and usually leads
to a crash.
Signed-off-by: Leon Alrae
---
Hi,
This patch fixes the bug introduced in:
commit 2994fd96d986578a342f2342501b4ad30f6d0a85
Author: Eduardo Habkost
cpu: Make cpu_init() return QOM CPUState object
mips_r4k.c | 3 +--
>> 5 files changed, 8 insertions(+), 13 deletions(-)
>
> Reviewed-by: Andreas Färber
>
> Leon and Paolo, I assume one of you will be handling this?
>
Acked-by: Leon Alrae
Paolo, is this going via your memory API pullreq?
Regards,
Leon
On 05/03/2015 22:13, Hervé Poussineau wrote:
> Hi,
>
> This patchset improves dp8393x network card emulation to current QEMU
> standards,
> mostly decouples it from MIPS rc4030 chipset emulation, and add PROM and
> load/save
> functionalities.
> Only required cleanup has been done on the rc4030
Hi Duarte,
On 25/03/2015 14:20, Duarte Silva wrote:
> On Wednesday 25 March 2015 13:13:14 James Hogan wrote:
>> Hi Duarte,
>>
>> On 22/03/15 11:13, Duarte Silva wrote:
>>> Hi guys,
>>>
>>> I have been struggling to get some binaries compiled for NetLogic XLP
>>> processor to run under QEMU. I have
On 25/03/2015 14:44, Leon Alrae wrote:
> Hi Duarte,
>
> On 25/03/2015 14:20, Duarte Silva wrote:
>> On Wednesday 25 March 2015 13:13:14 James Hogan wrote:
>>> Hi Duarte,
>>>
>>> On 22/03/15 11:13, Duarte Silva wrote:
>>>> Hi guys,
>>>
On 25/03/2015 15:38, Duarte Silva wrote:
> On Wednesday 25 March 2015 14:54:41 Leon Alrae wrote:
>> On 25/03/2015 14:44, Leon Alrae wrote:
>>> Hi Duarte,
>>>
>>> On 25/03/2015 14:20, Duarte Silva wrote:
>>>> On Wednesday 25 March 2015 13:13:14 James
Hi Duarte,
On 25/03/2015 23:54, Duarte Silva wrote:
> On Wednesday 25 March 2015 17:33:59 Leon Alrae wrote:
>> On 25/03/2015 15:38, Duarte Silva wrote:
>>> On Wednesday 25 March 2015 14:54:41 Leon Alrae wrote:
>>>> On 25/03/2015 14:44, Leon Alrae wrote:
>>>
Hi,
On 27/03/2015 17:05, Peter Maydell wrote:
> On 27 March 2015 at 16:57, Liviu Ionescu wrote:
>>
>>> On 27 Mar 2015, at 18:22, Christopher Covington
>>> wrote:
>>>
>>>
>>> Hi,
>>>
>>> Here are a few patches preparing for and adding AArch64 Angel
>>> semihosting support.
>>
>> please note that
On 27/03/2015 17:33, Liviu Ionescu wrote:
>
>> On 27 Mar 2015, at 19:15, Leon Alrae wrote:
>>
>> ... introducing separate "-semihosting-arg" option to pass input arguments
>
> if we'll ever go for this solution, I would call it "-semihosting-
Signed-off-by: Leon Alrae
---
Hi,
Continuing the discussion related to extending QEMU's command line with new
argument allowing to pass semi-hosting input arguments to the guest program:
https://lists.gnu.org/archive/html/qemu-devel/2015-03/msg05960.html
This simple patch adds &quo
On 01/04/2015 16:21, Liviu Ionescu wrote:
>
>> On 01 Apr 2015, at 16:18, Leon Alrae wrote:
>>
>> ... This simple patch adds "arg" sub-argument which in my opinion is flexible
>> enough to satisfy semi-hosting interfaces which allocate buffers at runtime
>
On 02/04/2015 09:29, Liviu Ionescu wrote:
>
>> On 02 Apr 2015, at 10:56, Leon Alrae wrote:
>>
>> ... The UHI semihosting supports Argn syscall which returns single argument,
>> and Argn is called multiple times to build argv (each argument can
>> contain white
On 02/04/2015 10:14, Leon Alrae wrote:
> On 02/04/2015 09:29, Liviu Ionescu wrote:
>>
>>> On 02 Apr 2015, at 10:56, Leon Alrae wrote:
>>>
>>> ... The UHI semihosting supports Argn syscall which returns single argument,
>>> and Argn is called mu
)
MIPS patches 2014-11-03
Changes:
* second part (privileged) of MIPS64R6 support
* MIPS SIMD Architecture support
Leon Alrae (15):
target-mips: add KScratch registers
softmmu: provide softmmu access type
In Revision 3 of the architecture, the RI and XI bits were added to the TLB
to enable more secure access of memory pages. These bits (along with the Dirty
bit) allow the implementation of read-only, write-only, no-execute access
policies for mapped pages.
Signed-off-by: Leon Alrae
Reviewed-by
Signed-off-by: Leon Alrae
Reviewed-by: Yongbok Kim
---
target-mips/helper.c | 21 ++---
1 file changed, 10 insertions(+), 11 deletions(-)
diff --git a/target-mips/helper.c b/target-mips/helper.c
index fe16820..1c9e69d 100644
--- a/target-mips/helper.c
+++ b/target-mips/helper.c
CP0_KScratch1-6 registers.
For Release 6, all KScratch registers are required.
Signed-off-by: Leon Alrae
Reviewed-by: Yongbok Kim
---
target-mips/cpu.h | 3 +++
target-mips/translate.c | 44
2 files changed, 47 insertions(+)
diff --git a/target
New MIPS features depend on the access type and enum is more convenient than
using the numbers directly.
Signed-off-by: Leon Alrae
Reviewed-by: Thomas Huth
---
include/exec/cpu-common.h | 6 ++
softmmu_template.h| 26 --
2 files changed, 22 insertions
Signed-off-by: Leon Alrae
Reviewed-by: Yongbok Kim
---
target-mips/cpu.h | 2 +-
target-mips/machine.c | 26 +-
2 files changed, 26 insertions(+), 2 deletions(-)
diff --git a/target-mips/cpu.h b/target-mips/cpu.h
index 4687f4f..c66a725 100644
--- a/target-mips
Signed-off-by: Leon Alrae
Reviewed-by: Yongbok Kim
---
target-mips/cpu.h | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/target-mips/cpu.h b/target-mips/cpu.h
index 6367d8c..3b975eb 100644
--- a/target-mips/cpu.h
+++ b/target-mips/cpu.h
@@ -790,7 +790,8 @@ static inline
when the virtual address of a memory load
reference matches a TLB entry whose RI bit is set. This exception type can
only occur if the RI bit is implemented within the TLB and is enabled, this is
denoted by the PageGrain RIE bit.
Signed-off-by: Leon Alrae
Reviewed-by: Yongbok Kim
---
target-mips
mtc0 and dmtc0 helpers.
Signed-off-by: Leon Alrae
Reviewed-by: Yongbok Kim
---
target-mips/cpu.h| 4
target-mips/helper.h | 5 +
target-mips/op_helper.c | 25 ++---
target-mips/translate.c | 26 --
target-mips
add missing Config4 and Config5 cases for dm{f,t}c0.
Signed-off-by: Leon Alrae
Reviewed-by: Yongbok Kim
---
target-mips/cpu.h | 11 +--
target-mips/translate.c | 24 +++-
2 files changed, 32 insertions(+), 3 deletions(-)
diff --git a/target-mips/cpu.h b/target
From: Yongbok Kim
add MSA exceptions
Reviewed-by: James Hogan
Signed-off-by: Yongbok Kim
Signed-off-by: Leon Alrae
---
target-mips/helper.c | 10 ++
1 file changed, 10 insertions(+)
diff --git a/target-mips/helper.c b/target-mips/helper.c
index c92b25c..3a93c20 100644
--- a/target
From: Yongbok Kim
add MSA I8 format instructions
Reviewed-by: James Hogan
Signed-off-by: Yongbok Kim
Signed-off-by: Leon Alrae
---
target-mips/helper.h | 10 ++
target-mips/msa_helper.c | 66 ++
target-mips/translate.c | 82
is in a branch delay slot.
Using error_code to indicate whether AdEL or TLBL was triggered during
instruction fetch, in this case BadInstr is not updated as valid instruction
word is not available.
Signed-off-by: Leon Alrae
Reviewed-by: Yongbok Kim
---
target-mips/cpu.h | 6
target
it
tries to limit the input value but the limit is higher than the actual
number of tlb entries.
Signed-off-by: Leon Alrae
Reviewed-by: Yongbok Kim
---
target-mips/op_helper.c | 70 +
1 file changed, 53 insertions(+), 17 deletions(-)
diff --git a
From: Yongbok Kim
add msa_helper.c
Reviewed-by: James Hogan
Reviewed-by: Leon Alrae
Signed-off-by: Yongbok Kim
Signed-off-by: Leon Alrae
---
target-mips/Makefile.objs | 2 +-
target-mips/msa_helper.c | 49 +++
2 files changed, 50 insertions
From: Yongbok Kim
add MSA I5 format instructions
Signed-off-by: Yongbok Kim
Reviewed-by: Leon Alrae
Signed-off-by: Leon Alrae
---
target-mips/helper.h | 13 +
target-mips/msa_helper.c | 142 +++
target-mips/translate.c | 77
invalid on TLB entry write by having
EntryHi.EHINV set to 1.
Signed-off-by: Leon Alrae
Reviewed-by: Yongbok Kim
---
disas/mips.c | 2 ++
target-mips/cpu.h| 7 +
target-mips/helper.c | 2 +-
target-mips/helper.h | 2 ++
target-mips/op_helper.c
Signed-off-by: Leon Alrae
Reviewed-by: Yongbok Kim
---
target-mips/translate_init.c | 11 +--
1 file changed, 9 insertions(+), 2 deletions(-)
diff --git a/target-mips/translate_init.c b/target-mips/translate_init.c
index bcfc46a..0b70d05 100644
--- a/target-mips/translate_init.c
+++ b
From: Yongbok Kim
add MSA branch instructions
Reviewed-by: James Hogan
Signed-off-by: Yongbok Kim
Signed-off-by: Leon Alrae
---
target-mips/translate.c | 334 +++-
1 file changed, 220 insertions(+), 114 deletions(-)
diff --git a/target-mips
, ERET,
DERET, WAIT and PAUSE will generate RI exception if executed in forbidden or
delay slot.
Signed-off-by: Leon Alrae
Reviewed-by: Yongbok Kim
---
target-mips/cpu.h | 3 +-
target-mips/translate.c | 109
2 files changed, 76 insertions
From: Yongbok Kim
add MSA ELM format instructions
Signed-off-by: Yongbok Kim
Signed-off-by: Leon Alrae
---
target-mips/helper.h | 10 +++
target-mips/msa_helper.c | 162 +++
target-mips/translate.c | 118 ++
3
HW does.
Additionally, remove CP0 Random register as it became reserved in Release 6.
Signed-off-by: Leon Alrae
Reviewed-by: Yongbok Kim
---
target-mips/translate.c | 538 +++-
1 file changed, 260 insertions(+), 278 deletions(-)
diff --git a/target
From: Yongbok Kim
add defines and data structure for MIPS SIMD Architecture
Reviewed-by: James Hogan
Signed-off-by: Yongbok Kim
Signed-off-by: Leon Alrae
---
target-mips/cpu.h | 52 +++--
target-mips/mips-defs.h | 1 +
target-mips
From: Yongbok Kim
add MSA MI10 format instructions
update LSA and DLSA for MSA
add 16, 64 bit load and store
Signed-off-by: Yongbok Kim
Signed-off-by: Leon Alrae
---
target-mips/helper.h| 3 ++
target-mips/op_helper.c | 84 ++---
target-mips
From: Yongbok Kim
add MSA opcode enum
Reviewed-by: James Hogan
Reviewed-by: Leon Alrae
Signed-off-by: Yongbok Kim
Signed-off-by: Leon Alrae
---
target-mips/translate.c | 245
1 file changed, 245 insertions(+)
diff --git a/target-mips
From: Yongbok Kim
Remove the duplicated ieee_rm in gdbstub.c.
Make the other ieee_rm and ieee_ex_to_mips available to other files.
Reviewed-by: James Hogan
Reviewed-by: Leon Alrae
Signed-off-by: Yongbok Kim
Signed-off-by: Leon Alrae
---
target-mips/cpu.h | 4
target-mips
From: Yongbok Kim
add MSA 3RF format instructions
Signed-off-by: Yongbok Kim
Signed-off-by: Leon Alrae
---
target-mips/helper.h | 42 ++
target-mips/msa_helper.c | 1494 ++
target-mips/translate.c | 163 +
3 files changed, 1699
From: Yongbok Kim
stop translation as ctc1 instruction can change hflags
Reviewed-by: James Hogan
Signed-off-by: Yongbok Kim
Signed-off-by: Leon Alrae
---
target-mips/translate.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/target-mips/translate.c b/target-mips/translate.c
From: Yongbok Kim
add MSA BIT format instructions
Reviewed-by: Leon Alrae
Signed-off-by: Yongbok Kim
Signed-off-by: Leon Alrae
---
target-mips/helper.h | 13
target-mips/msa_helper.c | 196 +++
target-mips/translate.c | 88
From: Yongbok Kim
add MSA VEC/2R format instructions
Signed-off-by: Yongbok Kim
Signed-off-by: Leon Alrae
---
target-mips/helper.h | 12
target-mips/msa_helper.c | 140 +++
target-mips/translate.c | 113
From: Yongbok Kim
add msa_reset() and global msa register (d type only)
Reviewed-by: James Hogan
Signed-off-by: Yongbok Kim
Signed-off-by: Leon Alrae
---
target-mips/translate.c | 56
target-mips/translate_init.c | 34
From: Yongbok Kim
add MSA 3R format instructions
Signed-off-by: Yongbok Kim
Signed-off-by: Leon Alrae
---
target-mips/helper.h | 64 +
target-mips/msa_helper.c | 657 +++
target-mips/translate.c | 242 +
3 files changed
From: Yongbok Kim
add MSA 2RF format instructions
Signed-off-by: Yongbok Kim
Signed-off-by: Leon Alrae
---
target-mips/helper.h | 17 ++
target-mips/msa_helper.c | 530 +++
target-mips/translate.c | 74 +++
3 files changed, 621
From: Yongbok Kim
add MSA support to mips32r5-generic core definition
Signed-off-by: Yongbok Kim
Reviewed-by: Leon Alrae
Signed-off-by: Leon Alrae
---
target-mips/translate_init.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/target-mips/translate_init.c b/target
From: Yongbok Kim
disassemble MIPS SIMD Architecture instructions
Signed-off-by: Yongbok Kim
Signed-off-by: Leon Alrae
---
disas/mips.c | 716 ++-
1 file changed, 714 insertions(+), 2 deletions(-)
diff --git a/disas/mips.c b/disas
4-03-01
> 02:45:51.0 +
> +++ qemu-git-trunk/default-configs/mipsel-softmmu.mak 2014-10-28
> 23:02:26.677701438 +
> @@ -32,6 +32,5 @@ CONFIG_G364FB=y
> CONFIG_I8259=y
> CONFIG_JAZZ_LED=y
> CONFIG_MC146818RTC=y
> -CONFIG_VT82C686=y
> CONFIG_ISA_TESTDEV=y
> CONFIG_EMPTY_SLOT=y
>
Reviewed-by: Leon Alrae
itmask;
> #define CP0C4_M31
> -uint32_t CP0_Config5;
> -uint32_t CP0_Config5_rw_bitmask;
> +int32_t CP0_Config5;
> +int32_t CP0_Config5_rw_bitmask;
> #define CP0C5_M 31
> #define CP0C5_K 30
> #define CP0C5_CV 29
>
Reviewed-by: Leon Alrae
MMU_TYPE_R4000,
> +},
> + {
> /* A generic CPU providing MIPS32 Release 5 features.
> FIXME: Eventually this should be replaced by a real CPU model. */
> .name = "mips32r5-generic",
>
The actual microMIPS CPU definition is indeed a worthwile addition -
thanks. It was on my TODO list to upstream such a CPU but I haven't got
round to it.
Reviewed-by: Leon Alrae
Regards,
Leon
al cleanup won't happen before 2.2 release due to incoming
hard-freeze, this patch looks good to me.
> +check_cp1_enabled(ctx);
> +gen_compute_branch1(ctx, mips32_op,
> +(ctx->opcode >> 18) & 0x7, imm << 1);
> +} else {
> +generate_exception_err(ctx, EXCP_CpU, 1);
> +}
> break;
> case BPOSGE64:
> case BPOSGE32:
>
Reviewed-by: Leon Alrae
Regards,
Leon
; .CP0_Config2 = MIPS_CONFIG2,
> -.CP0_Config3 = MIPS_CONFIG3 | (1 << CP0C3_LPA),
> +.CP0_Config3 = MIPS_CONFIG3 | (1U << CP0C3_M) | (1 << CP0C3_DSP2P) |
> + (1 << CP0C3_DSPP) | (1 << CP0C3_LPA),
> .CP0_LLAddr_rw_bitmask = 0,
> .CP0_LLAddr_shift = 0,
> .SYNCI_Step = 32,
>
Reviewed-by: Leon Alrae
New R6 COP1 conditional branches currently don't have delay slot. Fixing this
by setting MIPS_HFLAG_BDS32 flag which is required for branches having 4-byte
delay slot.
Signed-off-by: Leon Alrae
---
target-mips/translate.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/target
ranslate.c 2014-11-02
> 18:51:10.838947420 +
> +++ qemu-git-trunk/target-mips/translate.c2014-11-02 18:51:14.838939198
> +
> @@ -17522,7 +17522,7 @@ gen_intermediate_code_internal(MIPSCPU *
> gen_io_end();
> }
> if (cs->singlestep_enabled &
On 05/11/2014 20:16, Maciej W. Rozycki wrote:
> Now as to CP0.Status.CU1, while fixing the 5Kc and 5KEc processors is an
> obvious change, I think the removal of the extra check may not be such.
> The thing is in the original architecture -- and it still stands for CP2
> -- these bits used to
On 05/11/2014 15:26, Leon Alrae wrote:
> On 04/11/2014 15:41, Maciej W. Rozycki wrote:
>> Set the CP0.Config3.DSP2P bit for the 74kf processor and both that bit
>> and the CP0.Config3.DSP bit for the artificial mips32r5-generic and
>> mips64dspr2 processors. They have the
On 07/11/2014 12:33, Maciej W. Rozycki wrote:
> On Fri, 7 Nov 2014, Leon Alrae wrote:
>
>> When I've been applying this patch to my mips-next candidate branch for
>> 2.2 I realized that you haven't rebased it onto the recent version where
>> MSA has been adde
-07
Changes:
* bug fixes
Leon Alrae (1):
target-mips: fix for missing delay slot in BC1EQZ and BC1NEZ
Maciej W. Rozycki (5):
mips: Remove CONFIG_VT82C686 from non-Fulong configs
mips: Respect CP0.Status.CU1 for
From: Yongbok Kim
Avoid to allocate different TCG registers for the FPU registers
that are mapped on the MSA vectore registers.
Signed-off-by: Yongbok Kim
Reviewed-by: Richard Henderson
Signed-off-by: Leon Alrae
---
target-mips/translate.c | 8 +++-
1 file changed, 3 insertions(+), 5
mmand line
argument.
The problem may have been easily missed because we have no hard-float
microMIPS CPU configuration present; in fact we have no microMIPS CPU
configuration of any kind present.
Signed-off-by: Maciej W. Rozycki
Reviewed-by: Leon Alrae
Signed-off-by: Leon Alrae
---
ta
ge is only available on Fulong platforms (CONFIG_FULONG)
that are exclusively little-endian, 64-bit MIPS. Previously vt82c686.o
was pulled explicitly with obj-$(CONFIG_FULONG).
Signed-off-by: Maciej W. Rozycki
Reviewed-by: Leon Alrae
Signed-off-by: Leon Alrae
---
default-configs/mips-softmmu
o have both CP0.Config3.DSP and
CP0.Config3.DSP2P set or software won't detect its presence.
Signed-off-by: Maciej W. Rozycki
Reviewed-by: Leon Alrae
[leon.al...@imgtec.com: remove DSP flags from mips32r5-generic]
Signed-off-by: Leon Alrae
---
target-mips/translate_init.c | 8 +--
New R6 COP1 conditional branches currently don't have delay slot. Fixing this
by setting MIPS_HFLAG_BDS32 flag which is required for branches having 4-byte
delay slot.
Signed-off-by: Leon Alrae
Reviewed-by: Yongbok Kim
---
target-mips/translate.c | 1 +
1 file changed, 1 insertion(+)
;: mtc0t1,c0_config
(gdb)
-- oops!
Signed-off-by: Maciej W. Rozycki
Reviewed-by: Leon Alrae
Signed-off-by: Leon Alrae
---
target-mips/translate.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target-mips/translate.c b/target-mips/translate.c
index 194d4fb..0bea3c4
From: "Maciej W. Rozycki"
Define macros for CP0.Config3 and CP0.Config4 bits. These used to be
exhaustive as at MIPS32r3, but more bits may have been added since.
Signed-off-by: Maciej W. Rozycki
Signed-off-by: Leon Alrae
---
target-mips/cpu.h | 13 +
1 file c
On 07/11/14 17:36, Maciej W. Rozycki wrote:
> On Fri, 7 Nov 2014, Leon Alrae wrote:
>
>>> I have been working with the current trunk, the change applies
>>> correctly there AFAICT.
>>
>> 55a2201 commit added (1 << CP0C3_MSAP) to CP0_Config3 for
>&g
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