tdout-path.
Given that this step was added to ARM virt ~ 3 months after 3.15 was
released, could we simply replace it (patch below)?
Failing that, could we set both for now?
/
Leif
>From 25a51745c6243ff279684a3990c8c6aad25ed7b5 Mon Sep 17 00:00:00 2001
From: Leif Lindholm
Date: Wed, 19 Nov
Sorry for being late to the party, missed this set when it went out.
On Thu, Oct 30, 2014 at 05:52:44PM +, Peter Maydell wrote:
> On 30 October 2014 17:43, Alexander Spyridakis
> wrote:
> > Currently, the virt machine model generates Device Tree information
> > dynamically based on the exist
On Mon, Mar 09, 2015 at 09:28:05PM +0900, Peter Maydell wrote:
> On 9 March 2015 at 21:12, Leif Lindholm wrote:
> > Sorry for being late to the party, missed this set when it went out.
>
> You seem to be replying to an email thread which is now many
> months old and at a part o
The _ADR entry in SPCR is optional and redundant. The same information
is already provided in _CRS (which is mandatory).
Signed-off-by: Leif Lindholm
---
So, this _ADR entry is only consumed by a set of not-widely-circulated
patches for the Linux kernel. And while the ARM Server Base Boot
On Thu, Aug 06, 2015 at 02:28:03PM +0200, Andrew Jones wrote:
> On Thu, Aug 06, 2015 at 12:24:27PM +0100, Leif Lindholm wrote:
> > The _ADR entry in SPCR is optional and redundant. The same information
> > is already provided in _CRS (which is mandatory).
> >
> > S
Hi Wei,
So, I can verify that this works all the way into Linux userland
dmidecode on arm64.
One question:
This set still leaves the -smbios set of options x86 only.
Would
--- a/qemu-options.hx
+++ b/qemu-options.hx
@@ -1412,7 +1412,7 @@ DEF("smbios", HAS_ARG, QEMU_OPTION_smbios,
"-smbios
On Tue, Sep 15, 2015 at 09:20:40AM +0800, Shannon Zhao wrote:
>
>
> On 2015/9/15 0:35, Andrew Jones wrote:
> > On Sun, Sep 13, 2015 at 04:06:33PM +0100, Leif Lindholm wrote:
> >> Add a DBG2 table, describing the pl011 UART.
> >>
> >> Signed-off-by: Leif
Add a DBG2 table, describing the pl011 UART.
Signed-off-by: Leif Lindholm
---
hw/arm/virt-acpi-build.c | 88 +++-
1 file changed, 87 insertions(+), 1 deletion(-)
diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c
index 9088248..763d531
:
- Static structure replaced with separate Header/Device structs.
- Missing cpu_to_le*() transforms added in table construction.
- Added missing setting of address_size_offset.
- Commit message modified to mention SPCR spec version bump.
Leif Lindholm (2):
ACPI: Add definitions for the DBG2 table
The DBG2 table can be considered a "companion" to SPCR - it points out
debug consoles available in the system.
Also update SPCR comments to reflect DBG2 is now described in this file,
and update the supported SPCR specification revision (no functional
change).
Signed-off-by: Lei
Add a DBG2 table, describing the pl011 UART.
Signed-off-by: Leif Lindholm
---
hw/arm/virt-acpi-build.c | 37 -
1 file changed, 36 insertions(+), 1 deletion(-)
diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c
index 9088248..6d53dbe 100644
The Debug Port Table 2 (DBG2) is mandated by the ARM Server Base Boot
Requirements specification. Add the DBG2 table definitions, and set up
an entry in the ARM virt machine for the pl011 UART.
Leif Lindholm (2):
ACPI: Add definitions for the DBG2 table
hw/arm/virt-acpi-build: Add DBG2 table
The DBG2 table can be considered a "companion" to SPCR - it points out
debug consoles available in the system.
Signed-off-by: Leif Lindholm
---
include/hw/acpi/acpi-defs.h | 37 +++--
1 file changed, 35 insertions(+), 2 deletions(-)
diff --git a/inclu
On Tue, Sep 08, 2015 at 11:18:27AM +0800, Shannon Zhao wrote:
> On 2015/9/7 22:23, Leif Lindholm wrote:
> > The Debug Port Table 2 (DBG2) is mandated by the ARM Server Base Boot
> > Requirements specification. Add the DBG2 table definitions, and set up
> > an entry in the ARM
On Tue, Sep 08, 2015 at 11:27:08AM +0800, Shannon Zhao wrote:
>
>
> On 2015/9/7 22:23, Leif Lindholm wrote:
> > The DBG2 table can be considered a "companion" to SPCR - it points out
> > debug consoles available in the system.
> >
> > Signed-off-by:
Add a DBG2 table, describing the pl011 UART.
Signed-off-by: Leif Lindholm
---
hw/arm/virt-acpi-build.c | 60 +++-
1 file changed, 59 insertions(+), 1 deletion(-)
diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c
index 9088248..0ea7023
x27;m just slightly too
unfamiliar with both ACPI in general and the QEMU aml_* functions to
quite wrap my head around how to do this dynamically.
Leif Lindholm (2):
ACPI: Add definitions for the DBG2 table
hw/arm/virt-acpi-build: Add DBG2 table
hw/arm/virt-acpi-build
The DBG2 table can be considered a "companion" to SPCR - it points out
debug consoles available in the system.
Also update SPCR comments to reflect DBG2 is now described in this file,
and update the supported SPCR specification revision (no functional
change).
Signed-off-by: Lei
On Wed, Aug 19, 2015 at 04:49:15PM -0400, Gabriel L. Somlo wrote:
> Hi Ard,
>
> On Wed, Aug 19, 2015 at 11:42:02AM +0200, Ard Biesheuvel wrote:
> > (missed some cc's)
> >
> > On 19 August 2015 at 11:38, Ard Biesheuvel
> > wrote:
> > > From: "Gabriel L. Somlo"
> > >> Several different architect
On Thu, Aug 20, 2015 at 01:24:39AM +0100, Peter Maydell wrote:
> On 6 August 2015 at 14:25, Andrew Jones wrote:
> > On Thu, Aug 06, 2015 at 01:55:14PM +0100, Leif Lindholm wrote:
> >> On Thu, Aug 06, 2015 at 02:28:03PM +0200, Andrew Jones wrote:
> >> > In the least
On Thu, Aug 20, 2015 at 07:09:57PM +0800, Shannon Zhao wrote:
> >>>Could somebody who understands ACPI and the ramifications
> >>>here let me know if I should apply this patch, please?
> >>>(since we're now post-2.4)
> >>
> >>I presume my opinion is clear, but I'm cc:ing some of the Linaro ACPI
> >
On Tue, Aug 25, 2015 at 04:17:42PM +0100, Peter Maydell wrote:
> On 13 August 2015 at 18:09, Wei Huang wrote:
> > This patch adds support for SMBIOS 3.0 entry point. When caller invokes
> > smbios_set_defaults(), it can specify entry point as 2.1 or 3.0. Then
> > smbios_get_tables() will return th
uthor: Wei Huang
> Date: Tue Aug 25 16:34:47 2015 -0400
>
> smbios: add smbios 3.0 support
>
> This patch adds support for SMBIOS 3.0 entry point. When caller invokes
> smbios_set_defaults(), it can specify entry point as 2.1 or 3.0. Then
> smbios_get_t
for that aspect:
Reviewed-by: Leif Lindholm
/
Leif
hw/ide/ahci-allwinner.c| 3 +--
hw/ide/ahci.c | 1 +
9 files changed, 43 insertions(+), 34 deletions(-)
create mode 100644 include/hw/ide/ahci-sysbus.h
diff --git a/include/hw/arm/allwinner-a10.h b/include/hw/ar
d provides only data we use in firmware.
>
> Added NUMA information to list of things reported by DeviceTree.
>
> Signed-off-by: Marcin Juszkiewicz
Reviewed-by: Leif Lindholm
Thanks!
/
Leif
> ---
> docs/system/arm/sbsa.rst | 35 ++-
>
> To unify tests for AArch64/virt and AArch64/sbsa-ref we boot
> the same Alpine Linux image on both.
>
> Signed-off-by: Marcin Juszkiewicz
> Signed-off-by: Philippe Mathieu-Daudé
> Message-Id: <20230323082813.971535-1-marcin.juszkiew...@linaro.org>
Thanks for this.
traditional nitpick and ask this to be added above
sysemu/numa.h in order to maintain alphabetical ordering within the
sysemu block?
With that:
Reviewed-by: Leif Lindholm
> #include "exec/hwaddr.h"
> #include "kvm_arm.h"
> #include "hw/arm/boot.h"
> --
> 2.38.1
>
On Thu, Nov 11, 2021 at 16:55:09 +, Peter Maydell wrote:
> On Tue, 9 Nov 2021 at 22:52, Leif Lindholm wrote:
> >
> > On Tue, Nov 09, 2021 at 21:21:46 +, Peter Maydell wrote:
> > > The other thing we should nail down is how the user is going to
> > > sel
mc->minimum_page_bits = 12;
Seems reasonable; Leif, any objection?
None.
Longer-term, I still want to move to "max" as the default, but that is
likely to require some invasive changes to TF-A, and this is already a
huge improvement. So:
Reviewed-by: Leif Lindholm
Thanks!
/
Leif
On 2023-05-15 11:15, Peter Maydell wrote:
On Mon, 15 May 2023 at 11:04, Marcin Juszkiewicz
wrote:
Let add GIC information into DeviceTree as part of SBSA-REF versioning.
Trusted Firmware will read it and provide to next firmware level.
Bumps platform version to 0.1 one so we can check is nod
On 2023-05-05 13:09, Marcin Juszkiewicz wrote:
Bochs card is normal PCI Express card so it fits better in system with
PCI Express bus. VGA is simple legacy PCI card.
Signed-off-by: Marcin Juszkiewicz
Reviewed-by: Leif Lindholm
---
hw/arm/sbsa-ref.c | 2 +-
1 file changed, 1 insertion
Reviewed-by: Leif Lindholm
---
hw/arm/sbsa-ref.c | 19 ++-
1 file changed, 18 insertions(+), 1 deletion(-)
diff --git a/hw/arm/sbsa-ref.c b/hw/arm/sbsa-ref.c
index 792371fdce..9204e8605f 100644
--- a/hw/arm/sbsa-ref.c
+++ b/hw/arm/sbsa-ref.c
@@ -29,6 +29,7 @@
#include "
On Tue, Nov 09, 2021 at 13:43:50 +, Peter Maydell wrote:
> On Fri, 15 Oct 2021 at 13:23, Leif Lindholm wrote:
> > (Apologies for delay. Alex also tells me you are currently away, but
> > there is no strong urgency here.)
>
> (Thanks for the ping via Alex -- I missed
On Tue, Nov 09, 2021 at 21:21:46 +, Peter Maydell wrote:
> > Hmm, right. So you're thinking containing the versioning fully in the
> > interfaces presented by the model:
> > - Is the version node present?
> > - If so, is it greater than X?
> > - If so, is it great enough to support the SC
On Wed, Apr 27, 2022 at 7:13 PM Leif Lindholm
wrote:
>
> NUVIA was acquired by Qualcomm in March 2021, but kept functioning on
> separate infrastructure for a transitional period. We've now switched
> over to contributing as Qualcomm Innocation Center (quicinc), so update
>
NUVIA was acquired by Qualcomm in March 2021, but kept functioning on
separate infrastructure for a transitional period. We've now switched
over to contributing as Qualcomm Innocation Center (quicinc), so update
my email address to reflect this.
Signed-off-by: Leif Lindholm
Cc: Leif Lindhol
incremented.
These properties are both introduced with the value 0.
(Hence, a machine where the DT is lacking these nodes is equivalent
to version 0.0.)
Signed-off-by: Leif Lindholm
Cc: Peter Maydell
Cc: Radoslaw Biernacki
Cc: Cédric Le Goater
---
hw/arm/sbsa-ref.c | 3 +++
1 file changed, 3
Hi Cedric,
On Thu, Apr 28, 2022 at 10:55:54 +0200, Cédric Le Goater wrote:
> > The sbsa-ref machine is continuously evolving. Some of the changes we
> > want to make in the near future, to align with real components (e.g.
> > the GIC-700), will break compatibility for existing firmware.
> >
> > I
On Thu, Apr 28, 2022 at 13:46:36 +0100, Peter Maydell wrote:
> On Wed, 27 Apr 2022 at 19:13, Leif Lindholm wrote:
> >
> > NUVIA was acquired by Qualcomm in March 2021, but kept functioning on
> > separate infrastructure for a transitional period. We've now switched
&
On Fri, Apr 29, 2022 at 09:17:09 +0200, Cédric Le Goater wrote:
> > Signed-off-by: Leif Lindholm
> > Cc: Peter Maydell
> > Cc: Radoslaw Biernacki
> > Cc: Cédric Le Goater
> > ---
> > hw/arm/sbsa-ref.c | 3 +++
> > 1 file changed, 3 insertions(+)
&g
NUVIA was acquired by Qualcomm in March 2021, but kept functioning on
separate infrastructure for a transitional period. We've now switched
over to contributing as Qualcomm Innocation Center (quicinc), so update
my email address to reflect this.
Signed-off-by: Leif Lindholm
Cc: Leif Lindhol
revision ID register found on a physical platform.
These properties are both introduced with the value 0.
(Hence, a machine where the DT is lacking these nodes is equivalent
to version 0.0.)
Signed-off-by: Leif Lindholm
Cc: Peter Maydell
Cc: Radoslaw Biernacki
Cc: Cédric Le Goater
Hi everyone,
As some of you might have noticed, my email setup broke a little over
a month ago. At the time I was on leave, so did not notice for a
while. And upon my return, it turned out it had broken in New and
Exciting ways - so it took some time to restore.
This has now been achieved, and I
From: Leif Lindholm
We have mainly (well, as will become clear, in fact "exclusively") been using
sbsa-ref with the "max" CPU. But sbsa-ref was created with a default CPU of
Cortex-A57, which we have not updated along the way.
However, the "max" cpu has seen a bug
From: Leif Lindholm
Due to a change in upstream TF-A, boot fails (in edk2) on all cpus that
don't implement FEAT_DIT. The only currently emulated cpu that "supports"
this feature is "max". So switch to using that cpu by default for
sbsa-ref.
However, it is worth
for "max" as default to have stable set of features enabled
by default. It is still supported and can be selected with "--cpu"
argument.
I still want to move to max at some point :)
But this is a good improvement for now.
Reviewed-by: Leif Lindholm
Signed-off-by: Marcin J
chain (gcc 12.2.0).
Missing signoff?
Apart from that:
Reviewed-by: Leif Lindholm
---
tests/avocado/machine_aarch64_sbsaref.py | 20 ++--
1 file changed, 10 insertions(+), 10 deletions(-)
diff --git a/tests/avocado/machine_aarch64_sbsaref.py
b/tests/avocado/machine_aarch64_sbsare
On 2024-05-31 10:37, Marcin Juszkiewicz wrote:
Updated firmware for QEMU CI is already in merge queue so we can move
platform to be future proof.
All supported cpus work fine with 1GHz timer frequency when firmware is
fresh enough.
Signed-off-by: Marcin Juszkiewicz
Reviewed-by: Leif
: Marcin Juszkiewicz
Reviewed-by: Leif Lindholm
Thanks!
---
docs/system/arm/sbsa.rst | 4
hw/arm/sbsa-ref.c| 11 ++-
2 files changed, 14 insertions(+), 1 deletion(-)
diff --git a/docs/system/arm/sbsa.rst b/docs/system/arm/sbsa.rst
index 2bf22a1d0b..2bf3fc8d59 100644
Hi Peter,
(Apologies for delay. Alex also tells me you are currently away, but
there is no strong urgency here.)
On Thu, Sep 23, 2021 at 17:00:35 +0100, Peter Maydell wrote:
> > If we assume that we don't want to further complicate this set by
> > adding the additional logic *now*, I see three op
ponent does not
necessarily want/need the same maintainers as the sbsa-ref platform.
I'm still happy to maintain it, and it may make sense to keep it under
this header for now.
(In which case
Reviewed-by: Leif Lindholm
)
Regards,
Leif
> F: docs/system/arm/sbsa.rst
> F: tests/avocado/machine_aarch64_sbsaref.py
>
> --
> 2.41.0
>
ovement to me.
Not even compilation tested, just the least confusing way of asking
whether the change could be accepted at all.
Leif Lindholm (3):
include/hw/arm: move BSA definitions to bsa.h
{include/}hw/arm: refactor BSA/virt PPI logic
hw/arm/sbsa-ref: use bsa.h for PPI definitions
h
Use the private peripheral interrupt definitions from bsa.h instead of
defining them locally. Refactor to use PPI() to convert from INTID macro
where necessary.
Signed-off-by: Leif Lindholm
---
hw/arm/sbsa-ref.c | 24 +++-
1 file changed, 11 insertions(+), 13 deletions
virt.h defines a number of IRQs that are ultimately described by Arm's
Base System Architecture specification. Move these to a dedicated header
so that they can be reused by other platforms that do the same.
Include that header from virt.h to minimise churn.
Signed-off-by: Leif Lin
used.
Signed-off-by: Leif Lindholm
---
hw/arm/virt-acpi-build.c | 4 ++--
hw/arm/virt.c| 9 +
include/hw/arm/bsa.h | 14 +++---
3 files changed, 14 insertions(+), 13 deletions(-)
diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c
index 6b674231c2..963c5
On 2023-09-14 14:15, Marcin Juszkiewicz wrote:
W dniu 14.09.2023 o 14:01, Leif Lindholm pisze:
While reviewing Marcin's patch this morning, cross referencing different
specifications and looking at various places around the source code in
order to convinced myself he really hadn
virt.h defines a number of IRQs that are ultimately described by Arm's
Base System Architecture specification. Move these to a dedicated header
so that they can be reused by other platforms that do the same.
Include that header from virt.h to minimise churn.
Signed-off-by: Leif Lin
used.
Signed-off-by: Leif Lindholm
---
hw/arm/virt-acpi-build.c | 4 ++--
hw/arm/virt.c| 9 +
include/hw/arm/virt.h| 14 +++---
3 files changed, 14 insertions(+), 13 deletions(-)
diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c
index 6b674231c2..963c5
On Fri, Sep 15, 2023 at 13:35:19 +0200, Marcin Juszkiewicz wrote:
> Update prebuilt firmware images to have TF-A with Neoverse V1 support enabled.
> This allowed us to enable test for this cpu in sbsa-ref machine.
>
> Signed-off-by: Marcin Juszkiewicz
Acked-by: Leif Lindholm
&g
Use the private peripheral interrupt definitions from bsa.h instead of
defining them locally. Refactor to use PPI() to convert from INTID macro
where necessary.
Signed-off-by: Leif Lindholm
---
hw/arm/sbsa-ref.c | 23 +++
1 file changed, 11 insertions(+), 12 deletions
same header instead of defining its own values
locally.
Changes since RFC:
- Compilation tested
- Reordered patches 1-2 as suggested by Philippe.
Leif Lindholm (3):
{include/}hw/arm: refactor virt PPI logic
include/hw/arm: move BSA definitions to bsa.h
hw/arm/sbsa-ref: use bsa.h for PPI defini
Use the private peripheral interrupt definitions from bsa.h instead of
defining them locally. Refactor to use the INTIDs defined there instead
of the PPI# used previously.
Signed-off-by: Leif Lindholm
---
hw/arm/sbsa-ref.c | 20 +---
1 file changed, 9 insertions(+), 11 deletions
ation instead of doing the
translation, as suggested by Peter.
- Added explicit comment that listed IDs are INTIDs.
Changes since RFC:
- Compilation tested
- Reordered patches 1-2 as suggested by Philippe.
Leif Lindholm (3):
{include/}hw/arm: refactor virt PPI logic
include/hw/arm: mov
virt.h defines a number of IRQs that are ultimately described by Arm's
Base System Architecture specification. Move these to a dedicated header
so that they can be reused by other platforms that do the same.
Include that header from virt.h to minimise churn.
Signed-off-by: Leif Lin
uired.
Signed-off-by: Leif Lindholm
---
hw/arm/virt-acpi-build.c | 12 ++--
hw/arm/virt.c| 24 ++--
include/hw/arm/virt.h| 14 +++---
3 files changed, 27 insertions(+), 23 deletions(-)
diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-bu
On 2023-09-19 11:12, Peter Maydell wrote:
This patchset is an RFC that wires up the NS EL2 virtual timer IRQ on
the virt board, similarly to what
https://patchew.org/QEMU/20230913140610.214893-1-marcin.juszkiew...@linaro.org/
does for the sbsa-ref board.
Patches 1 and 3 are the usual dance to ke
On 2023-06-27 13:12, Peter Maydell wrote:
On Mon, 26 Jun 2023 at 08:52, Marcin Juszkiewicz
wrote:
Add PCI Express information into DeviceTree as part of SBSA-REF
versioning.
Trusted Firmware will read it and provide to next firmware level.
Signed-off-by: Marcin Juszkiewicz
---
hw/arm/sbsa
On 2023-06-27 14:27, Peter Maydell wrote:
On Tue, 27 Jun 2023 at 13:52, Leif Lindholm wrote:
On 2023-06-27 13:12, Peter Maydell wrote:
On Mon, 26 Jun 2023 at 08:52, Marcin Juszkiewicz
wrote:
Add PCI Express information into DeviceTree as part of SBSA-REF
versioning.
Trusted Firmware will
On 2023-06-27 15:27, Peter Maydell wrote:
Serious question: would it be preferable if we moved to a custom DT node
where we stick everything in as KEY=VALUE pairs to reduce this confusion?
I don't really mind, I just want it to be clear what is going on here
so that when I'm reviewing patches I
Hi Peter,
On 2023-06-19 13:47, Peter Maydell wrote:
On Wed, 7 Jun 2023 at 03:34, Yuquan Wang wrote:
The current sbsa-ref cannot use EHCI controller which is only
able to do 32-bit DMA, since sbsa-ref doesn't have RAM below 4GB.
Hence, this uses system bus XHCI to provide a usb controller with
On 2023-05-31 16:27, Peter Maydell wrote:
On Wed, 31 May 2023 at 15:58, Graeme Gregory wrote:
The current sbsa-ref cannot use EHCI controller which is only
able to do 32-bit DMA, since sbsa-ref doesn't have RAM above 4GB.
Hence, this uses XHCI to provide a usb controller with 64-bit
DMA capabli
+Ard
On Thu, Jun 01, 2023 at 16:01:43 +0100, Peter Maydell wrote:
> > >> Also has EHCI never worked, or has it worked in some modes and so this
> > >> change should be versioned?
> > >
> > > AIUI, EHCI has never worked and can never have worked, because
> > > this board's RAM is all above 4G and t
Hi Yuquan,
On Fri, Jun 02, 2023 at 11:24:11 +0800, Yuquan Wang wrote:
> > > > To skip the migration hazard, my prefernece is we just leave the EHCI
> > > > device in for now, and add a separate XHCI on PCIe. We can drop the
> > > > EHCI device at some point in the future.
> > >
> > > Why PCIe for
On Thu, Sep 07, 2023 at 10:35:51 +1000, Gavin Shan wrote:
> Set mc->valid_cpu_types so that the user specified CPU type can
> be validated in machine_run_board_init(). We needn't to do it
> by ourselves.
>
> Signed-off-by: Gavin Shan
Reviewed-by: Leif Lindholm
> ---
On Sun, Oct 22, 2023 at 16:51:23 +0100, David Woodhouse wrote:
> From: David Woodhouse
>
> Signed-off-by: David Woodhouse
Reviewed-by: Leif Lindholm
> ---
> hw/arm/sbsa-ref.c | 4 +---
> 1 file changed, 1 insertion(+), 3 deletions(-)
>
> diff --git a/hw/arm/sbsa-r
On Wed, Dec 05, 2018 at 05:50:23PM +0800, Hongbo Zhang wrote:
> > > +static
> > > +void sbsa_ref_machine_done(Notifier *notifier, void *data)
> > > +{
> > > +VirtMachineState *vms = container_of(notifier, VirtMachineState,
> > > + machine_done);
> > > +
On Fri, Nov 16, 2018 at 02:04:07PM -0800, Ard Biesheuvel wrote:
> > > > What is this using the exynos4210 USB device for? That
> > > > is definitely not correct for a generic board.
> > > >
> > > Checked the code:
> > > #define TYPE_SYS_BUS_EHCI "sysbus-ehci-usb"
> > > #define TYPE_EXYNOS4210_EHCI
On Mon, Nov 19, 2018 at 07:51:29AM -0800, Ard Biesheuvel wrote:
> > > > I think what we *really* want is sysbus-xhci-generic.
> > > >
> > > > That'll be a bit more work though as xhci core and xhci pci needs to be
> > > > splitted, simliar to how it was done for ehci in commit
> > > > 5010d4dc618b6
On Thu, Aug 30, 2018 at 03:07:29PM +0800, Hongbo Zhang wrote:
> >> Yes, I am working on the v3, with main changes:
> >> - machine name "sbsa-ref" (good name?)
> >> - a separate file sbsa-ref.c
> >> - don't touch the acpi c file, acpi will be supplied by uefi
> >
> > I agree with the above three
On Thu, Aug 30, 2018 at 09:39:33AM +0100, Peter Maydell wrote:
> On 30 August 2018 at 09:31, Leif Lindholm wrote:
> > On Thu, Aug 30, 2018 at 03:07:29PM +0800, Hongbo Zhang wrote:
> >> @Ard, @Leif, is there any possibility to remove all the DT nodes?
> >> On real hardw
On Thu, Aug 30, 2018 at 03:29:02PM +0200, Ard Biesheuvel wrote:
> On 30 August 2018 at 12:02, Leif Lindholm wrote:
> > On Thu, Aug 30, 2018 at 09:39:33AM +0100, Peter Maydell wrote:
> >> On 30 August 2018 at 09:31, Leif Lindholm wrote:
> >> > On Thu, Aug 30, 20
e options from being parsed for any non-x86
targets.
Change this to use a status variable instead of compile-time filtering.
Signed-off-by: Leif Lindholm
---
Verified on ARM mach-virt with UEFI shell "smbiosview" command and QEMU
command line parameter -smbios type=0,version=foobar.
, Leif Lindholm wrote:
> Commit c30e1565 ("smbios: implement smbios support for mach-virt")
> enabled automatic generation of SMBIOS tables for TARGET_ARM, and
> actually provides data for the "virt" machine.
>
> However, do_smbios_option() still had an #ifdef TA
On Wed, Dec 21, 2016 at 11:51:02AM +0100, Igor Mammedov wrote:
> On Fri, 16 Dec 2016 15:23:19 +
> > Verified on ARM mach-virt with UEFI shell "smbiosview" command and QEMU
> > command line parameter -smbios type=0,version=foobar.
> >
> > arch_init.c| 6 +++---
> > include/hw/s
-smbios command line options were accepted but silently ignored on
TARGET_ARM, due to a test for TARGET_I386 in arch_init.c.
Copy the mechanism of hw/pci/pci-stub.c to implement an smbios-stub
instead, enabled for all targets without CONFIG_SMBIOS.
Signed-off-by: Leif Lindholm
---
Not sure if
On Wed, Dec 21, 2016 at 06:58:44PM +0100, Paolo Bonzini wrote:
> On 21/12/2016 14:59, Igor Mammedov wrote:
> >> Apparently a misunderstanding of the underlying command line handling
> >> mechanics.
> >>
> >>> Also this patch would break build for targets that don't link smbios.c
> >>> (i.e. which d
now reset or shut down through software control. Verified from UEFI
Shell with upstream edk2-platforms and upstream + 1 patch
trusted-firmware-a.
So with that fix:
Tested-by: Leif Lindholm
Reviewed-by: Leif Lindholm
Thanks!
/
Leif
> ---
> hw/arm/sbsa-ref.c | 95 +
Update address to reflect new employer.
Signed-off-by: Leif Lindholm
---
MAINTAINERS | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/MAINTAINERS b/MAINTAINERS
index 483edfbc0b..3c8653f26f 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -735,7 +735,7 @@ F: include/hw/ssi
On Thu, Jan 16, 2020 at 17:42:26 +, Leif Lindholm wrote:
> Update address to reflect new employer.
>
> Signed-off-by: Leif Lindholm
Reviewed-by: Leif Lindholm
> ---
> MAINTAINERS | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/MAINTAINE
On Thu, Jan 16, 2020 at 19:25:52 +0100, Philippe Mathieu-Daudé wrote:
> On 1/16/20 6:42 PM, Leif Lindholm wrote:
> > Update address to reflect new employer.
> >
> > Signed-off-by: Leif Lindholm
> > ---
> > MAINTAINERS | 2 +-
> > 1 file changed, 1 in
ble PMU counters.
>
> So let make QEMU provide those 6 PMU counters.
>
> SBSA-ACS says now:
>
> 12 : Check number of PMU counters : Result: PASS
>
> Signed-off-by: Marcin Juszkiewicz
Reviewed-by: Leif Lindholm
It would be good if we could get 6.0 close
On Wed, Mar 03, 2021 at 18:06:46 +, Peter Maydell wrote:
> On Wed, 3 Mar 2021 at 17:48, Leif Lindholm wrote:
> > It would be good if we could get 6.0 closer to SBSA compliance.
>
> How far away are we at the moment ?
>
> > Would it be worth the effort to make this co
On Thu, Mar 04, 2021 at 15:14:36 +, Peter Maydell wrote:
> On Thu, 4 Mar 2021 at 13:53, Leif Lindholm wrote:
> >
> > On Wed, Mar 03, 2021 at 18:06:46 +, Peter Maydell wrote:
> > > On Wed, 3 Mar 2021 at 17:48, Leif Lindholm wrote:
> > > > It would b
As a first step towards GICv4 compatibility, add support for gic revision 4
to GICv3 driver (i.e. don't bail out if revision 4 is encountered).
Signed-off-by: Leif Lindholm
---
hw/intc/arm_gicv3_common.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw
... problematic ... system, which will misbehave if you try
to use the virtual LPIs. But it does help with letting me use QEMU for
modelling a platform containing a GICv4, and share firmware images with
other prototyping platforms.
Leif Lindholm (4):
hw/intc: don't bail out gicv3 model ini
Make gicv3_idreg() able to return either gicv3 or gicv4 data.
Add a parameter to specify gic version.
Signed-off-by: Leif Lindholm
---
hw/intc/arm_gicv3_dist.c | 2 +-
hw/intc/arm_gicv3_redist.c | 2 +-
hw/intc/gicv3_internal.h | 12 ++--
3 files changed, 12 insertions(+), 4
GICv3 sets aside 128K for each redistributor block, whereas GICv4 sets
aside 256K. To enable use of the gicv3 model for gicv4, abstract this
away as the helper function gicv3_redist_size() and replace the current
hardcoded locations with calls to this function.
Signed-off-by: Leif Lindholm
The VLPI frames are what make the redistributor size change, so ensure
we state in GICD_TYPER that we have them.
Signed-off-by: Leif Lindholm
---
hw/intc/arm_gicv3_dist.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/hw/intc/arm_gicv3_dist.c b/hw/intc/arm_gicv3_dist.c
index b65f56f903
On Tue, Feb 02, 2021 at 10:31:16 +, Peter Maydell wrote:
> On Sun, 24 Jan 2021 at 02:53, Leif Lindholm wrote:
> >
> > Make gicv3_idreg() able to return either gicv3 or gicv4 data.
> > Add a parameter to specify gic version.
> >
> > Signed-off-by: Le
On Tue, Feb 02, 2021 at 10:39:22 +, Peter Maydell wrote:
> On Sun, 24 Jan 2021 at 02:53, Leif Lindholm wrote:
> >
> > GICv4 sets aside 256K per redistributor configuration block, whereas GICv3
> > only uses 128K. However, some codebases (like TF-A, EDK2) will happ
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