During transactions, these get added to memory attributes at the same
time other attributes are added.
Similar to the requester ID, these are added on PTWs, GPCs, and
descriptor grabbing as well.
Signed-off-by: Joe Komlodi
---
target/arm/cpu.c | 2 ++
target/arm/cpu.h | 2 ++
target/arm/ptw.c
These are used to represent implementation-specific data.
These are based off of AMBA-AXI user signals, but can be used in any
implementation.
The length of 4-bits is arbitrary.
Signed-off-by: Joe Komlodi
---
include/exec/memattrs.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/include
checkpatch.pl doesn't like these spaces around the colon, so we may as
well fix it up.
No functional change.
Signed-off-by: Joe Komlodi
---
include/exec/memattrs.h | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/include/exec/memattrs.h b/include/exec/memattrs.h
ces that set attributes (using address_space_rw or some
other means), can add them on a per-device basis.
RFC because it's possible we might want this implementated in some other
way, and it touches some pretty frequently used code that I'm somewhat
familiar with, but not 100% fam
MEMTXATTRS_UNSPECIFIED, and we should respect
that instead of injecting user-defined attributes in the function.
Signed-off-by: Joe Komlodi
---
hw/pci/pci.c| 3 +++
include/hw/pci/pci_device.h | 1 +
2 files changed, 4 insertions(+)
diff --git a/hw/pci/pci.c b/hw/pci/pci.c
index 6496d027ca
ating TLBs. Similarly, we add the
requester ID during PTW, while populating the rest of the memory
attributes.
We add the requester ID during GPC and descriptor grabbing as well as
PTWs.
Signed-off-by: Joe Komlodi
---
target/arm/cpu.c | 4
target/arm/cpu.h | 6 ++
target/arm/ptw.
On Wed, Feb 28, 2024 at 6:21 AM Peter Maydell wrote:
>
> On Tue, 27 Feb 2024 at 22:24, Joe Komlodi wrote:
> > This adds requester IDs to ARM CPUs and adds a "user-defined" memory
> > attribute.
> >
> > The requester ID on ARM CPUs is there because I'
On Thu, Feb 29, 2024 at 1:57 AM Peter Maydell wrote:
>
> On Thu, 29 Feb 2024 at 04:52, Joe Komlodi wrote:
> > On Wed, Feb 28, 2024 at 6:21 AM Peter Maydell
> > wrote:
> > > So as far as I can see, this patchset defines a bunch of mechanism,
> > > but no ac
On Thu, Feb 8, 2024 at 8:39 AM Peter Maydell wrote:
>
> On Fri, 2 Feb 2024 at 20:48, Joe Komlodi wrote:
> >
> > It's possible for a reset to come in the middle of a transaction, which
> > causes the bus to be in an old state when a new transaction comes in.
>
On Fri, Feb 16, 2024 at 5:04 PM Corey Minyard wrote:
>
> On Thu, Feb 08, 2024 at 04:39:10PM +, Peter Maydell wrote:
> > On Fri, 2 Feb 2024 at 20:48, Joe Komlodi wrote:
> > >
> > > It's possible for a reset to come in the middle of a transaction, which
&
It's possible for a reset to come in the middle of a transaction, which
causes the bus to be in an old state when a new transaction comes in.
Signed-off-by: Joe Komlodi
---
hw/i2c/core.c | 19 +++
1 file changed, 19 insertions(+)
diff --git a/hw/i2c/core.c b/hw/i2c/core.c
ward.
Basically as long as a reset happens in the middle of a transaction, the
state of the old transaction would still partially be there after the
reset. Once a new transaction comes in, the partial stale state can
cause the new transaction to incorrectly fail.
Thanks,
Joe
Joe Komlodi (3):
hw/
If a reset comes while the SMBus device is not in its idle state, it's
possible for it to get confused on valid transactions post-reset.
Signed-off-by: Joe Komlodi
Reviewed-by: Peter Maydell
---
hw/i2c/smbus_slave.c | 9 +
1 file changed, 9 insertions(+)
diff --git a/h
The current logging doesn't tell us which specific smbus device is an
error state.
Signed-off-by: Joe Komlodi
Reviewed-by: Peter Maydell
---
hw/i2c/smbus_slave.c | 8 ++--
1 file changed, 6 insertions(+), 2 deletions(-)
diff --git a/hw/i2c/smbus_slave.c b/hw/i2c/smbus_slave.c
Hi peter,
On Thu, Feb 1, 2024 at 7:24 AM Peter Maydell wrote:
>
> On Fri, 26 Jan 2024 at 00:56, Joe Komlodi wrote:
> >
> > It's possible for a reset to come in the middle of a transaction, which
> > causes the bus to be in an old state when a new transaction comes i
The current logging doesn't tell us which specific smbus device is an
error state.
Signed-off-by: Joe Komlodi
---
hw/i2c/smbus_slave.c | 8 ++--
1 file changed, 6 insertions(+), 2 deletions(-)
diff --git a/hw/i2c/smbus_slave.c b/hw/i2c/smbus_slave.c
index 1300c9ec72..9f9afc25a4 1
It's possible for a reset to come in the middle of a transaction, which
causes the bus to be in an old state when a new transaction comes in.
Signed-off-by: Joe Komlodi
---
hw/i2c/core.c| 19 +++
include/hw/i2c/i2c.h | 2 +-
2 files changed, 20 insertions(+), 1 del
n would still partially be there after the
reset. Once a new transaction comes in, the partial stale state can
cause the new transaction to incorrectly fail.
Thanks,
Joe
Joe Komlodi (3):
hw/i2c: core: Add reset
hw/i2c/smbus_slave: Add object path on error prints
hw/i2c: smbus_slave: Res
If a reset comes while the SMBus device is not in its idle state, it's
possible for it to get confused on valid transactions post-reset.
Signed-off-by: Joe Komlodi
---
hw/i2c/smbus_slave.c | 9 +
1 file changed, 9 insertions(+)
diff --git a/hw/i2c/smbus_slave.c b/hw/i2c/smbus_sl
The registers are only 32 bits wide, so we should cast the 64-bit value
passed in to only be 32 bits wide.
Signed-off-by: Joe Komlodi
Reviewed-by: Patrick Venture
Reviewed-by: Titus Rwantare
---
hw/i3c/aspeed_i3c.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/hw
RESET_CTRL and INTR_FORCE are write-only.
Signed-off-by: Joe Komlodi
Reviewed-by: Patrick Venture
---
hw/i3c/aspeed_i3c.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/hw/i3c/aspeed_i3c.c b/hw/i3c/aspeed_i3c.c
index 6f514bef5e..79715f462d 100644
--- a/hw/i3c/aspeed_i3c.c
+++ b/hw/i3c
Adds behavior to the device reset register.
Signed-off-by: Joe Komlodi
Reviewed-by: Patrick Venture
Reviewed-by: Stephen Longfield
---
hw/i3c/aspeed_i3c.c | 110 +---
hw/i3c/trace-events | 1 +
2 files changed, 104 insertions(+), 7 deletions(-)
diff
tiated by target)
- 1-byte opcode
- 1-byte IBI address
- 1-byte RnW boolean
- 4-byte length of IBI payload from target as a LE uint32 (can be 0)
- n-byte IBI payload
Signed-off-by: Joe Komlodi
Reviewed-by: Patrick Venture
Reviewed-by: Stephen Longfield
---
hw/i3c/Kconfig | 5
Adds the rest of the fields laid out in the AST26xx datasheet.
Signed-off-by: Joe Komlodi
Reviewed-by: Patrick Venture
---
hw/i3c/aspeed_i3c.c | 260 ++--
1 file changed, 248 insertions(+), 12 deletions(-)
diff --git a/hw/i3c/aspeed_i3c.c b/hw/i3c
This adds a remote I3C qtest using the Aspeed I3C controller and an
AST2600 board.
The qtest uses a basic Aspeed I3C driver to test:
- data transmission from controller to target
- data reception from target to controller
- target sending an IBI (with data bytes) to controller
Signed-off-by: Joe
ve data to/from the controller,
the user reads/writes to a bidirectional TX/RX port.
Signed-off-by: Joe Komlodi
Reviewed-by: Stephen Longfield
Reviewed-by: Patrick Venture
---
hw/i3c/aspeed_i3c.c | 848
hw/i3c/trace-events | 10 +
incl
Signed-off-by: Joe Komlodi
Reviewed-by: Patrick Venture
Reviewed-by: Hao Wu
---
hw/i3c/aspeed_i3c.c | 57 +
1 file changed, 57 insertions(+)
diff --git a/hw/i3c/aspeed_i3c.c b/hw/i3c/aspeed_i3c.c
index 2ed09234ff..b9aa1367d8 100644
--- a/hw/i3c
ng support. The hotplugging doesn't do anything too
complicated, it just adds the device attempting to hotplug to the bus. It is
the device's responsibility to hot-join and go through the DAA process to
participate on the bus.
Thanks!
Joe
Joe Komlodi (16):
hw/misc/aspeed_i3c: Move to i3
Moves the Aspeed I3C model and traces into hw/i3c and create I3C build
files.
Signed-off-by: Joe Komlodi
Reviewed-by: Patrick Venture
Reviewed-by: Titus Rwantare
---
hw/Kconfig| 1 +
hw/arm/Kconfig| 1 +
hw/i3c/Kconfig
Adds functionality to the CTRL register.
Signed-off-by: Joe Komlodi
Reviewed-by: Titus Rwantare
Reviewed-by: Patrick Venture
---
hw/i3c/aspeed_i3c.c | 36
1 file changed, 36 insertions(+)
diff --git a/hw/i3c/aspeed_i3c.c b/hw/i3c/aspeed_i3c.c
index
controller sets an interrupt to notify
software about what happened.
When the IBI is finished being serviced, the controller pushes the
result of the IBI and any data received from the target into the IBI
queue.
Signed-off-by: Joe Komlodi
Reviewed-by: Patrick Venture
Reviewed-by: Stephen Longfield
This adds support for hotplugging in I3C.
Conceptually this can be thought of as an I3C target being physically
socketed onto a board.
It is then the target's responsibility to go through the hot-join and
DAA process so it can participate on the bus.
Signed-off-by: Joe Komlodi
Review
.
Signed-off-by: Joe Komlodi
Reviewed-by: Titus Rwantare
Reviewed-by: Patrick Venture
---
hw/i3c/Kconfig | 10 ++
hw/i3c/meson.build | 1 +
hw/i3c/mock-target.c | 312 +++
hw/i3c/trace-events | 9 +
include/hw/i3c/mock
handle it in some way.
Signed-off-by: Joe Komlodi
Reviewed-by: Patrick Venture
Reviewed-by: Titus Rwantare
---
hw/i3c/core.c| 629 +++
hw/i3c/meson.build | 1 +
hw/i3c/trace-events | 16 ++
include/hw/i3c/i3c.h | 275 +++
4
Adds read-only field masks for the I3C device and controller registers.
Signed-off-by: Joe Komlodi
Reviewed-by: Patrick Venture
---
hw/i3c/aspeed_i3c.c | 56 +
1 file changed, 56 insertions(+)
diff --git a/hw/i3c/aspeed_i3c.c b/hw/i3c/aspeed_i3c.c
Adds reset values for the new registers added.
Signed-off-by: Joe Komlodi
Reviewed-by: Patrick Venture
---
hw/i3c/aspeed_i3c.c | 17 +
1 file changed, 17 insertions(+)
diff --git a/hw/i3c/aspeed_i3c.c b/hw/i3c/aspeed_i3c.c
index ae247e03bb..034a17ff8e 100644
--- a/hw/i3c
Hi all,
On Sun, Apr 2, 2023 at 1:11 AM Jeremy Kerr wrote:
>
> Hi Cédric,
>
> > > Isn't this the designware i3c ip block, and as such could we name
> > > it so?
> >
> > Currently, QEMU only has a model for a dummy Aspeed I3C variant so
> > this is a great addition.
>
> [...]
>
> > According to rec
Hi Jeremy,
On Sun, Apr 2, 2023 at 11:14 PM Jeremy Kerr wrote:
>
> Hi Joe,
>
> > Adds a model to communicate to remote I3C devices over chardev. This
> > allows QEMU to communicate to I3C targets that exist outside of QEMU.
>
> Nice!
>
> I've been wanting something similar for a while, both for i2
;:{
"path":"/machine/soc/gpio[0]",
"property":"gpio-pin-level"
}}
Signed-off-by: Joe Komlodi
---
hw/gpio/npcm7xx_gpio.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/hw/gpio/npcm7xx_gpio.c b/hw/gpio/npcm7xx_gpio.c
index 2a7be60d8d..58db3a8d64
;:"qom-set","arguments": {
"path":"/machine/soc/gpio[0]",
"property":"gpio-pins-in",
"value":1048576
}}
1048576 == 0x10, JSON does not support hex.
Signed-off-by: Joe Komlodi
---
hw/gpio/npcm7xx_gpio.c | 28
QMP, so this adds properties to
allow people to do so.
Since the NPCM7xx is typically used to help manage other SoCs, hopefully
other people will find this useful as well.
Thanks!
Joe
Joe Komlodi (2):
hw/gpio/npcm7xx: Add GPIO DIN object property
hw/gpio/npcm7xx: Support qom-get on GPIO pin
Hi jeremy,
On Tue, Apr 11, 2023 at 2:17 AM Jeremy Kerr wrote:
>
> Hi Joe,
>
> > +static int aspeed_i3c_device_ibi_finish(I3CBus *bus)
> > +{
> > +AspeedI3CDevice *s = ASPEED_I3C_DEVICE(bus->qbus.parent);
> > +bool nack_and_disable_hj = ARRAY_FIELD_EX32(s->regs, DEVICE_CTRL,
> > +
problems.
Thanks!
Joe
Joe Komlodi (2):
hw/i2c: smbus_slave: Reset state on reset
hw/i2c: core: Add reset
hw/i2c/core.c| 25 ++---
hw/i2c/smbus_slave.c | 9 +
2 files changed, 31 insertions(+), 3 deletions(-)
--
2.40.0.rc2.332.ga46443480c-goog
It's possible for a reset to come in the middle of a transaction, which
causes the bus to be in an old state when a new transaction comes in.
Signed-off-by: Joe Komlodi
---
hw/i2c/core.c | 25 ++---
1 file changed, 22 insertions(+), 3 deletions(-)
diff --git a/hw/i2c/c
If a reset comes while the SMBus device is not in its idle state, it's
possible for it to get confused on valid transactions post-reset.
Signed-off-by: Joe Komlodi
---
hw/i2c/smbus_slave.c | 9 +
1 file changed, 9 insertions(+)
diff --git a/hw/i2c/smbus_slave.c b/hw/i2c/smbus_sl
On Thu, Jan 11, 2024 at 6:03 AM Corey Minyard wrote:
>
> On Wed, Jan 10, 2024 at 09:26:37PM +0000, Joe Komlodi wrote:
> > Hi all,
> >
> > This series adds some resets for SMBus and for the I2C core. Along with
> > it, we make SMBus slave error printing a little mor
of the old transaction would still partially be there after the
reset. Once a new transaction comes in, the partial stale state can
cause the new transaction to incorrectly fail.
Thanks,
Joe
Joe Komlodi (3):
hw/i2c: core: Add reset
hw/i2c/smbus_slave: Add object path on error prints
hw/i2c: s
The current logging doesn't tell us which specific smbus device is an
error state.
Signed-off-by: Joe Komlodi
---
hw/i2c/smbus_slave.c | 8 ++--
1 file changed, 6 insertions(+), 2 deletions(-)
diff --git a/hw/i2c/smbus_slave.c b/hw/i2c/smbus_slave.c
index 1300c9ec72..e24a1ef472 1
If a reset comes while the SMBus device is not in its idle state, it's
possible for it to get confused on valid transactions post-reset.
Signed-off-by: Joe Komlodi
---
hw/i2c/smbus_slave.c | 9 +
1 file changed, 9 insertions(+)
diff --git a/hw/i2c/smbus_slave.c b/hw/i2c/smbus_sl
It's possible for a reset to come in the middle of a transaction, which
causes the bus to be in an old state when a new transaction comes in.
Signed-off-by: Joe Komlodi
---
hw/i2c/core.c| 30 +-
include/hw/i2c/i2c.h | 6 +-
2 files changed, 30 inser
new
mode, so we use SHARED_FIELD_XX macros to reuse most of the code between
the different modes.
For packet mode, most of the command behavior is the same compared to
other modes, but there are some minor changes to how interrupts are
handled compared to other modes.
Signed-off-by: Jo
Signed-off-by: Joe Komlodi
Change-Id: I566eb09f4b9016e24570572f367627f6594039f5
---
hw/i2c/aspeed_i2c.c | 3 +++
hw/i2c/trace-events | 2 +-
2 files changed, 4 insertions(+), 1 deletion(-)
diff --git a/hw/i2c/aspeed_i2c.c b/hw/i2c/aspeed_i2c.c
index 948d8dc2bb..f179f78ee9 100644
--- a/hw/i2c
Moves register definitions and short commonly used inlined functiosn to
the header file to help tidy up the implementation file.
Signed-off-by: Joe Komlodi
Change-Id: I34dff7485b6bbe3c9482715ccd94dbd65dc5f324
---
hw/i2c/aspeed_i2c.c | 266 ---
include/hw
This cleans up some of the field accessing, setting, and clearing
bitwise operations, and wraps them in macros instead.
Signed-off-by: Joe Komlodi
Change-Id: I33018d6325fa04376e7c29dc4a49ab389a8e333a
---
hw/i2c/aspeed_i2c.c | 393 ++--
1 file changed, 196
grate over to the register API and then add new mode
support.
Thanks!
Joe
Joe Komlodi (7):
hw/registerfields: Add shared fields macros
aspeed: i2c: Add ctrl_global_rsvd property
aspeed: i2c: Migrate to registerfields API
aspeed: i2c: Use reg array instead of individual vars
aspeed: i2c: Ad
The Aspeed I2C controller is used across other SKUs that have different
reserved bits for the ctrl_global_rsvd register.
Signed-off-by: Joe Komlodi
Change-Id: I606c5933c527274a9d2b0afe559b2e895767636c
---
hw/arm/aspeed_ast2600.c | 2 ++
hw/i2c/aspeed_i2c.c | 4
include/hw/i2c
extract FIELD1 via
SHARED_ARRAY_FIELD_EX32(s->regs, R_REG_MODE1, FIELD1)
or
SHARED_ARRAY_FIELD_EX32(s->regs, R_REG_MODE2, FIELD1)
Signed-off-by: Joe Komlodi
Change-Id: Id3dc53e7d2f8741c95697cbae69a81bb699fa3cb
---
include/hw/registerfields.h | 70 +
1 file c
macros on registers.
Signed-off-by: Joe Komlodi
Change-Id: Ib94996b17c361b8490c042b43c99d8abc69332e3
---
hw/i2c/aspeed_i2c.c | 286 +---
include/hw/i2c/aspeed_i2c.h | 11 +-
2 files changed, 133 insertions(+), 164 deletions(-)
diff --git a/hw/i2c
e the CNTFRQ reset value.
Signed-off-by: Joe Komlodi
---
hw/timer/sse-timer.c | 4 +++-
include/hw/timer/sse-timer.h | 2 ++
2 files changed, 5 insertions(+), 1 deletion(-)
diff --git a/hw/timer/sse-timer.c b/hw/timer/sse-timer.c
index e92e83747d..a727f05bac 100644
--- a/hw/timer/sse-ti
.
Since it's valid for CNTFRQ to have a non-zero reset value, we just
added an object property so people can set it.
Thanks!
Joe
Joe Komlodi (1):
hw/timer/sse-timer: Add CNTFRQ reset property
hw/timer/sse-timer.c | 4 +++-
include/hw/timer/sse-timer.h | 2 ++
2 files changed, 5 inser
The current logging doesn't tell us which specific smbus device is an
error state.
Signed-off-by: Joe Komlodi
---
hw/i2c/smbus_slave.c | 8 ++--
1 file changed, 6 insertions(+), 2 deletions(-)
diff --git a/hw/i2c/smbus_slave.c b/hw/i2c/smbus_slave.c
index 1300c9ec72..e24a1ef472 1
straightforward.
Basically as long as a reset happens in the middle of a transaction, the
state of the old transaction would still partially be there after the
reset. Once a new transaction comes in, the partial stale state can
cause the new transaction to incorrectly fail.
Thanks,
Joe
Joe Komlodi (4
It's possible for a reset to come in the middle of a transaction, which
causes the bus to be in an old state when a new transaction comes in.
Signed-off-by: Joe Komlodi
---
hw/i2c/core.c| 30 +-
include/hw/i2c/i2c.h | 6 +-
2 files changed, 30 inser
If a reset comes while the SMBus device is not in its idle state, it's
possible for it to get confused on valid transactions post-reset.
Signed-off-by: Joe Komlodi
---
hw/i2c/smbus_slave.c | 9 +
1 file changed, 9 insertions(+)
diff --git a/hw/i2c/smbus_slave.c b/hw/i2c/smbus_sl
for the SMBusDevice class, and
have the mux class invoke it when it resets.
Signed-off-by: Joe Komlodi
---
hw/i2c/i2c_mux_pca954x.c | 5 +
hw/i2c/smbus_slave.c | 3 +++
include/hw/i2c/smbus_slave.h | 1 +
3 files changed, 9 insertions(+)
diff --git a/hw/i2c/i2c_mux_pca954x.c b/hw
+cminyard
Accidentally typed Corey's email address wrong in the initial send, oops.
On Wed, Jan 10, 2024 at 1:26 PM Joe Komlodi wrote:
>
> Hi all,
>
> This series adds some resets for SMBus and for the I2C core. Along with
> it, we make SMBus slave error printing a
to a relative pin number on a
controller, assuming each controller has 32-bits of pins.
If no allowlist is specified, we transmit on any pin update.
Signed-off-by: Joe Komlodi
---
hw/gpio/google_gpio_transmitter.c | 122 ++
include/hw/gpio/google_gpio_transmitter.h
This tests each NPCM7xx GPIO controller to make sure that when GPIO state is
updated, the controller sends a request to the GPIO transmitter to transmit the
data via chardev.
Along with that, we verify that the data is formatted correctly.
Signed-off-by: Joe Komlodi
---
tests/qtest
This adds the GPIO transmitter to the NPCM7xx GPIO controller and
transmits packets any time the pin state changes.
Signed-off-by: Joe Komlodi
---
hw/arm/Kconfig | 1 +
hw/arm/npcm7xx.c | 7 +++
hw/gpio/npcm7xx_gpio.c | 14 ++
include/hw
state the x86
machine is in based on the GPIO state of the BMC, and notify the VM
manager of any important changes.
The VM manager can then power up/down and reset the x86 machine as
needed.
Thanks!
Joe
Joe Komlodi (6):
hw/gpio/gpio_transmitter: Add Device
hw/gpio/gpio_transmitter: Add
For transmitting the GPIO state to the outside world, the GPIO transmitter will
need to know which controller's state has been updated.
To do this, we'll just number each controller at initialization.
Signed-off-by: Joe Komlodi
---
hw/arm/npcm7xx.c | 1 +
hw/gpio/npcm
For the GPIO transmitter to properly transmit on pin changes, it must
know the initial state of the GPIO pins on the controller.
Signed-off-by: Joe Komlodi
---
hw/gpio/npcm7xx_gpio.c | 9 +
1 file changed, 9 insertions(+)
diff --git a/hw/gpio/npcm7xx_gpio.c b/hw/gpio/npcm7xx_gpio.c
controller doesn't care about it, and because any
errors would be the fault of the external software receiving the GPIO
transmitter packets.
Signed-off-by: Joe Komlodi
---
hw/gpio/Kconfig | 3 +
hw/gpio/google_gpio_transmitter.c | 127
Hi all,
This series adds memattrs on MicroBlaze transactions.
It does so by adding support for the use-non-secure property on MicroBlaze CPUs.
>From there, we can then determine if the transaction should be secure or not,
and memory attributes can be set accordingly.
Thanks!
Joe
Joe Komlodi
their corresponding values are taken from:
https://www.xilinx.com/support/documentation/sw_manuals/xilinx2020_2/ug984-vivado-microblaze-ref.pdf
page 153.
Signed-off-by: Joe Komlodi
---
target/microblaze/cpu.c | 46 ++
target/microblaze/cpu.h | 11
Using the cfg.use_non_secure bitfield and the MMU access type, we can determine
if the access should be secure or not.
Signed-off-by: Joe Komlodi
---
target/microblaze/cpu.c| 2 +-
target/microblaze/cpu.h| 3 ++-
target/microblaze/helper.c | 26 +++---
3 files
Using MMUAccessType makes it more clear what the variable's use is.
No functional change.
Signed-off-by: Joe Komlodi
---
target/microblaze/mmu.c | 2 +-
target/microblaze/mmu.h | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/target/microblaze/mmu.c b/target/micro
Hi Francisco,
Comments marked with [Joe]
-Original Message-
From: Francisco Iglesias
Sent: Tuesday, October 20, 2020 6:50 AM
To: Joe Komlodi
Cc: qemu-devel@nongnu.org; alist...@alistair23.me; kw...@redhat.com;
mre...@redhat.com; qemu-bl...@nongnu.org
Subject: Re: [PATCH 1/2] hw/block
://www.micron.com/-/media/client/global/documents/products/data-sheet/
nor-flash/serial-nor/mt25q/die-rev-b/mt25q_qlkt_u_02g_cbb_0.pdf
?rev=9b167fbf2b3645efba6385949a72e453
Page 34, page 39 note 5
Signed-off-by: Joe Komlodi
---
hw/block/m25p80.c | 26 +++---
1 file changed, 23
value
(8 or 10) if the register is all 0s or 1s.
If the register value isn't all 0s or 1s, then the flash expects the amount of
cycles sent to be equal to the count in the register.
Thanks!
Joe
Joe Komlodi (1):
hw/block/m25p80: Fix Numonyx fast read dummy cycle count
hw/block/
Hi Peter,
This series has been reviewed, but it looks like it slipped through the cracks.
Is it possible it could be merged through your tree, assuming it looks good?
Thanks!
Joe
-Original Message-
From: Qemu-devel On Behalf
Of Joe Komlodi
Sent: Monday, November 16, 2020 3:11 PM
To
When reporting register to GDB, note that even though 32-bit Microblaze
supports having certain registers wider than 32-bits, we're repoting all of
them as being 32-bits wide right now to maintain compatibility with GDB.
Thanks!
Joe
Joe Komlodi (4):
target/microblaze: gdb: Add dynamic GDB XM
SRegs used to be reported to GDB by iterating over the SRegs array,
however we do not store them in an order that allows them to be
reported to GDB in that way.
To fix this, a simple map is used to map the register GDB wants to its
location in the SRegs array.
Signed-off-by: Joe Komlodi
Increase the number of registers reported to match GDB.
Registers that aren't modeled are reported as 0.
Signed-off-by: Joe Komlodi
---
target/microblaze/translate.c | 16 ++--
1 file changed, 14 insertions(+), 2 deletions(-)
diff --git a/target/microblaze/translate.c b/t
Increase the number of Microblaze registers QEMU will report when
talking to GDB.
Signed-off-by: Joe Komlodi
---
target/microblaze/cpu.c | 2 +-
target/microblaze/gdbstub.c | 52 ++---
2 files changed, 50 insertions(+), 4 deletions(-)
diff --git a
Add dynamic GDB register XML for Microblaze, and modify the config file to
use XML when building for Microblaze.
For the dynamic XML to be read, there still needs to be a core XML file.
Signed-off-by: Joe Komlodi
---
configure | 1 +
target/microblaze/cpu.c | 4
The check to see if we can use FPU2 instructions would return 0 if
cfg.use_fpu == 2, rather than returning the PVR2_USE_FPU2_MASK.
This would cause all FPU2 instructions (fsqrt, flt, fint) to not be used.
Signed-off-by: Joe Komlodi
---
target/microblaze/translate.c | 2 +-
1 file changed, 1
Hi all,
This fixes a backwards if statement that caused Microblaze FPU2 instructions
to not be executed, even if use-fpu=2 in the DTS.
Thanks!
Joe
Joe Komlodi (1):
target/microblaze: Fix FPU2 instruction check
target/microblaze/translate.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion
- 1/4: Added missing core XML file
Joe Komlodi (4):
target/microblaze: gdb: Add dynamic GDB XML register support
target/microblaze: gdb: Extend the number of registers presented to
GDB
target/microblaze: gdb: Fix incorrect SReg reporting
target/microblaze: monitor: Increase the number
Increase the number of Microblaze registers QEMU will report when
talking to GDB.
Signed-off-by: Joe Komlodi
---
target/microblaze/cpu.c | 2 +-
target/microblaze/gdbstub.c | 52 ++---
2 files changed, 50 insertions(+), 4 deletions(-)
diff --git a
SRegs used to be reported to GDB by iterating over the SRegs array,
however we do not store them in an order that allows them to be
reported to GDB in that way.
To fix this, a simple map is used to map the register GDB wants to its
location in the SRegs array.
Signed-off-by: Joe Komlodi
Increase the number of registers reported to match GDB.
Registers that aren't modeled are reported as 0.
Signed-off-by: Joe Komlodi
---
target/microblaze/translate.c | 16 ++--
1 file changed, 14 insertions(+), 2 deletions(-)
diff --git a/target/microblaze/translate.c b/t
Add dynamic GDB register XML for Microblaze, and modify the config file to
use XML when building for Microblaze.
For the dynamic XML to be read, there still needs to be a core XML file.
Signed-off-by: Joe Komlodi
---
configure | 1 +
gdb-xml/microblaze-core.xml | 64
Hi Edgar,
Ah, I did. It was in my directory but didn't get added to git.
It should have been part of the first patch.
I'll add it to the first patch and send up a v2.
Thanks!
Joe
-Original Message-
From: Edgar E. Iglesias
Sent: Wednesday, May 13, 2020 10:29 AM
To: J
Hi Edgar,
Comments marked with [Joe]
-Original Message-
From: Edgar E. Iglesias
Sent: Thursday, May 14, 2020 6:41 AM
To: Joe Komlodi
Cc: qemu-devel@nongnu.org
Subject: Re: [PATCH V2 1/4] target/microblaze: gdb: Add dynamic GDB XML
register support
On Wed, May 13, 2020 at 11:08:45AM
This adds the Microblaze core and stack protect XML files, and also
modifies the configuration to build those files.
Signed-off-by: Joe Komlodi
---
configure| 1 +
gdb-xml/microblaze-core.xml | 62
gdb-xml/microblaze
Hi all,
This adds GDB XML files for Microblaze CPUs.
For Microblaze, it's split up into core and stack protect XML files.
Thanks!
Joe
Joe Komlodi (1):
target/microblaze: Add GDB XML files for Microblaze
configure| 1 +
gdb-xml/microblaze-core.xml
If we have a field that's wider than 32-bits, we need a data type wide enough to
be able to create the bitfield used to deposit the value.
Signed-off-by: Joe Komlodi
---
include/hw/registerfields.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/include/hw/registerfield
We already have some utilities to handle 64-bit wide registers, so this just
adds some more for:
- Initializing 64-bit registers
- Extracting and depositing to an array of 64-bit registers
Signed-off-by: Joe Komlodi
---
hw/core/register.c | 12
include/hw/register.h
Hi all,
This adds more utilities for 64-bit registers.
As part of it, it also fixes FIELD_DP64 to work with bit fields wider than
32-bits.
Thanks!
Joe
Joe Komlodi (2):
hw/core/register: Add more 64-bit utilities
hw/registerfields: Use 64-bit bitfield for FIELD_DP64
hw/core/register.c
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