[PATCH] target/riscv: support cache-related PMU events in virtual mode

let tlb_fill() function also increments PMU counter when it is from two-stage translation, so QEMU could also monitor these PMU events when CPU runs in VS/VU mode (like running guest OS). Signed-off-by: Jim Shu --- target/riscv/cpu_helper.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion

[PATCH] hw/intc: sifive_plic: fix out-of-bound access of source_priority array

If the number of interrupt is not multiple of 32, PLIC will have out-of-bound access to source_priority array. Compute the number of interrupt in the last word to avoid this out-of-bound access of array. Signed-off-by: Jim Shu --- hw/intc/sifive_plic.c | 12 +++- 1 file changed, 11

Re: [PATCH] target/riscv: Support SW update of PTE A/D bits and Ssptwad extension

Hi Alistair, Why do we want to support that? We can do either and we are > implementing the much more usual scheme. I don't see a reason to > bother implementing the other one. Is anyone ever going to use it? > Thanks for your response. I got it. Regards, Jim Shu

Re: [PATCH 2/2] target/riscv: Make the "virt" register writable by GDB

Thanks for reviewing. I'll fix this issue. On Mon, Mar 6, 2023 at 7:26 PM LIU Zhiwei wrote: > > > On 2023/3/5 17:42, Jim Shu wrote: > > This patch also enables debugger to set current privilege mode to > > VU/VS-mode. > > > > Extend previous commit 81d29

Re: [PATCH 2/2] target/riscv: Make the "virt" register writable by GDB

On Mon, Mar 6, 2023 at 7:26 PM LIU Zhiwei wrote: > > > On 2023/3/5 17:42, Jim Shu wrote: > > This patch also enables debugger to set current privilege mode to > > VU/VS-mode. > > > > Extend previous commit 81d2929c41d32af138f3562f5a7b309f6eac7ca7 to > > sup

Re: [PATCH] include/hw/riscv/sifive_e.h: Fix the type of parent_obj of SiFiveEState.

Reviewed-by: Jim Shu On Fri, Aug 19, 2022 at 3:11 PM Tommy Wu wrote: > > Fix the type of parent_obj of SiFiveEState from 'SysBusDevice' > to 'MachineState'. Because the parent of SiFiveEState is 'MachineState'. > > Signed-off-by: Tommy Wu > ---

[PATCH] hw/intc: sifive_plic: fix hard-coded max priority level

Property in maximum priority level. Signed-off-by: Emmanuel Blot Signed-off-by: Jim Shu Reviewed-by: Frank Chang --- hw/intc/sifive_plic.c | 6 -- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/hw/intc/sifive_plic.c b/hw/intc/sifive_plic.c index af4ae3630e..f864efa761 100644

Re: [PATCH 2/4] hw/intc: sifive_plic.c: Fix interrupt priority index.

formula "irq = ((addr - plic->priority_base) >> 2) + 1" will take offset 0x4 as IRQ source 1, which is correct. Your fix will cause the bug in existing machines. Thanks, Jim Shu On Tue, Sep 6, 2022 at 11:21 PM Tyler Ng wrote: > > Here's the patch

Re: [PATCH 2/4] hw/intc: sifive_plic.c: Fix interrupt priority index.

Hi Tyler, Thanks for the explanation. I understand the issue here. I think we should align the priority base in each RISC-V platform to the same value (no matter 0x0 or 0x4) if they use PLIC in the same way. Thanks, Jim Shu On Tue, Sep 27, 2022 at 4:04 AM Tyler Ng wrote: > >

Re: [PATCH] hw/intc: sifive_plic: fix hard-coded max priority level

"num_priorities + 1" should be power-of-2 and SW could discover available bits of interrupt source priority. I'll do this enhancement in the next version patch. [1] https://github.com/riscv/riscv-plic-spec/blob/master/riscv-plic.adoc#interrupt-priorities Thanks, Jim Shu On Mon, S

[PATCH v2 1/2] hw/intc: sifive_plic: fix hard-coded max priority level

Property in maximum priority level. Signed-off-by: Emmanuel Blot Signed-off-by: Jim Shu Reviewed-by: Frank Chang --- hw/intc/sifive_plic.c | 6 -- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/hw/intc/sifive_plic.c b/hw/intc/sifive_plic.c index af4ae3630e..f864efa761 100644

[PATCH v2 0/2] Enhance maximum priority support of PLIC

This patchset fixes hard-coded maximum priority of interrupt priority register and also changes this register to WARL field to align the PLIC spec. Changelog: v2: * change interrupt priority register to WARL field. Jim Shu (2): hw/intc: sifive_plic: fix hard-coded max priority level hw

[PATCH v2 2/2] hw/intc: sifive_plic: change interrupt priority register to WARL field

hange each bit of interrupt priority register to WARL field when the number of supported priority is power-of-2. [1] https://github.com/riscv/riscv-plic-spec/blob/master/riscv-plic.adoc#interrupt-priorities Signed-off-by: Jim Shu --- hw/intc/sifive_plic.c | 21 +++-- 1 file change

Re: [PATCH v2 2/2] hw/intc: sifive_plic: change interrupt priority register to WARL field

hi Clément, Thank you very much. I'll fix it in the next version patch. Thanks, Jim Shu On Fri, Sep 30, 2022 at 8:58 PM Clément Chigot wrote: > > Hi Jim, > > On Fri, Sep 30, 2022 at 2:32 PM Jim Shu wrote: > > > > PLIC spec [1] requires interrupt source priority

Re: [PATCH v2 2/2] hw/intc: sifive_plic: change interrupt priority register to WARL field

Hi Clément, > > > @@ -180,7 +180,15 @@ static void sifive_plic_write(void *opaque, hwaddr > > > addr, uint64_t value, > > > if (addr_between(addr, plic->priority_base, plic->num_sources << 2)) > > > { > > > uint32_t irq = ((addr - plic->priority_base) >> 2) + 1; > > > > > > -

[PATCH v3 1/2] hw/intc: sifive_plic: fix hard-coded max priority level

Property in maximum priority level. Signed-off-by: Emmanuel Blot Signed-off-by: Jim Shu Reviewed-by: Frank Chang --- hw/intc/sifive_plic.c | 6 -- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/hw/intc/sifive_plic.c b/hw/intc/sifive_plic.c index af4ae3630e..f864efa761 100644

[PATCH v3 2/2] hw/intc: sifive_plic: change interrupt priority register to WARL field

hange each bit of interrupt priority register to WARL field when the number of supported priority is power-of-2. [1] https://github.com/riscv/riscv-plic-spec/blob/master/riscv-plic.adoc#interrupt-priorities Signed-off-by: Jim Shu --- hw/intc/sifive_plic.c | 21 +++-- 1 file change

[PATCH v3 0/2] Enhance maximum priority support of PLIC

This patchset fixes hard-coded maximum priority of interrupt priority register and also changes this register to WARL field to align the PLIC spec. Changelog: v3: * fix opposite of power-of-2 max priority checking expression. v2: * change interrupt priority register to WARL field. Jim Shu

Re: [PATCH v2 2/3] hw/dma: xilinx_axidma: Send DMA error IRQ if any memory access is failed

On Thu, Aug 8, 2024 at 9:34 PM Peter Maydell wrote: > > On Thu, 1 Aug 2024 at 15:08, Jim Shu wrote: > > > > The memory transactions from DMA could have bus-error in some cases. If > > it is failed, DMA device should send error IRQs. > > > > Signed-off-by

[PATCH] target/riscv: support atomic instruction fetch (Ziccif)

f-by: Jim Shu Reviewed-by: Frank Chang --- target/riscv/translate.c | 45 ++-- 1 file changed, 34 insertions(+), 11 deletions(-) diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 0569224e53..2be8ef63e6 100644 --- a/target/riscv/transla

[RFC PATCH 00/16] Implements RISC-V WorldGuard extension v0.4

11: Add WG global device and CPU extensions 4. Commit 12 ~ 15: Add WG checker device 5. Commit 16: Add WG support to the virt machine Jim Shu (16): accel/tcg: Store section pointer in CPUTLBEntryFull accel/tcg: memory access from CPU will pass access_type to IOMMU exec: Add RISC-V WorldGu

[RFC PATCH 02/16] accel/tcg: memory access from CPU will pass access_type to IOMMU

tion so that IOMMU could return the correct section of specified access_type. Signed-off-by: Jim Shu --- accel/tcg/cputlb.c | 15 +-- include/exec/exec-all.h | 11 +++ system/physmem.c | 16 +++- target/alpha/help

[RFC PATCH 03/16] exec: Add RISC-V WorldGuard WID to MemTxAttrs

signal. Signed-off-by: Jim Shu --- include/exec/memattrs.h | 5 + 1 file changed, 5 insertions(+) diff --git a/include/exec/memattrs.h b/include/exec/memattrs.h index 14cdd8d582..d00f3c5500 100644 --- a/include/exec/memattrs.h +++ b/include/exec/memattrs.h @@ -52,6 +52,11 @@ typedef struct

[RFC PATCH 01/16] accel/tcg: Store section pointer in CPUTLBEntryFull

OMMU devices don't have this issue since they are only in the path of DMA access. Currently, the bug only occurs when ARM MPC device (hw/misc/tz-mpc.c) returns 'blocked_io_as' to emulate blocked access handling. Upcoming RISC-V wgChecker device is also affected by this bug.

[RFC PATCH 08/16] target/riscv: Allow global WG config to set WG CPU callbacks

Some WG CPU functions depend on global WG config (like num-of-world), so we let the global WG config device to set callbacks of a RISC-V HART. Signed-off-by: Jim Shu --- target/riscv/cpu.h | 4 1 file changed, 4 insertions(+) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index

[RFC PATCH 12/16] hw/misc: riscv_wgchecker: Implement RISC-V WorldGuard Checker

ansactions Signed-off-by: Jim Shu --- hw/misc/meson.build| 2 +- hw/misc/riscv_wgchecker.c | 604 + hw/misc/trace-events | 8 + include/hw/misc/riscv_worldguard.h | 63 +++ 4 files changed, 676 insertions(+), 1 deletion(-) c

[RFC PATCH 15/16] hw/misc: riscv_wgchecker: Check the slot settings in translate

that point. One tricky part here is that the perm of 'blocked_io_as' is the condition of deny access. For example, if wgChecker only permits RO access, the perm of 'downstream_as' will be IOMMU_RO and the perm of 'blocked_io_as' will be IOMMU_WO. Signed

[RFC PATCH 09/16] target/riscv: Implement WorldGuard CSRs

The WG v0.4 specification adds 3 CSRs to configure S/U/HS/VS-mode WIDs of CPUs in the higher privileged modes. The Smwg extension at least requires a RISC-V HART to have M/U-mode, and the Sswg/Smwgd extension at least requires a RISC-V HART to have M/S/U-mode. Signed-off-by: Jim Shu --- target

[RFC PATCH 14/16] hw/misc: riscv_wgchecker: Implement correct block-access behavior

The wgChecker is configurable for whether blocked accesses: * should cause a bus error or just read return zero and write ignore * should generate the interrupt or not Signed-off-by: Jim Shu --- hw/misc/riscv_wgchecker.c | 169 +- 1 file changed, 167

[RFC PATCH 07/16] target/riscv: Add defines for WorldGuard CSRs

Add CSRs for 3 WG extensions: Smwg, Smwgd, and Sswg. Signed-off-by: Jim Shu --- target/riscv/cpu_bits.h | 5 + 1 file changed, 5 insertions(+) diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index 74318a925c..3ea8a8e9a0 100644 --- a/target/riscv/cpu_bits.h +++ b/target/riscv

[RFC PATCH 16/16] hw/riscv: virt: Add WorldGuard support

* Add 'wg=on' option to enable RISC-V WorldGuard * Add wgChecker to protect several resources: DRAM, FLASH, UART. Signed-off-by: Jim Shu --- docs/system/riscv/virt.rst | 10 +++ hw/riscv/Kconfig | 1 + hw/riscv/virt.c

[RFC PATCH 13/16] hw/misc: riscv_wgchecker: Implement wgchecker slot registers

wgChecker slot is similar to PMP region. SW could program each slot to configure the permission of address range. Signed-off-by: Jim Shu --- hw/misc/riscv_wgchecker.c | 330 + hw/misc/riscv_worldguard.c | 3 + include/hw/misc/riscv_worldguard.h

[RFC PATCH 10/16] target/riscv: Add WID to MemTxAttrs of CPU memory transactions

When a RISC-V HART has WG extension, their memory transactions will contain WID. Support MemTxAttrs in RISC-V target and add WID inside if a HART has WG extension. Signed-off-by: Jim Shu --- target/riscv/cpu.c| 2 +- target/riscv/cpu.h| 1 + target/riscv/cpu_helper.c | 51

[RFC PATCH 11/16] hw/misc: riscv_worldguard: Add API to enable WG extension of CPU

riscv_worldguard_apply_cpu() could enable WG CPU extension and set WG callback to CPUs. It is used by machine code after realizing global WG device. Signed-off-by: Jim Shu --- hw/misc/riscv_worldguard.c | 87 ++ include/hw/misc/riscv_worldguard.h | 1 + 2

[RFC PATCH 05/16] target/riscv: Add CPU options of WorldGuard CPU extension

We define CPU options for WG CSR support in RISC-V CPUs which can be set by machine/device emulation. The RISC-V CSR emulation will also check this feature for emulating WG CSRs. Signed-off-by: Jim Shu --- target/riscv/cpu.c | 8 target/riscv/cpu_cfg.h | 3 +++ target

[RFC PATCH 04/16] hw/misc: riscv_worldguard: Add RISC-V WorldGuard global config

Add a device for RISCV WG global config, which contains the number of worlds, reset value, and trusted WID ... etc. This global config is used by both CPU WG extension and wgChecker devices. Signed-off-by: Jim Shu --- hw/misc/Kconfig| 3 + hw/misc/meson.build

[RFC PATCH 06/16] target/riscv: Add hard-coded CPU state of WG extension

s, we should set it by machine code. Signed-off-by: Jim Shu --- target/riscv/cpu.c| 2 ++ target/riscv/cpu.h| 2 ++ target/riscv/cpu_cfg.h| 2 ++ target/riscv/cpu_helper.c | 18 ++ 4 files changed, 24 insertions(+) diff --git a/target/riscv/cpu.c b/targe

Re: [RFC PATCH 02/16] accel/tcg: memory access from CPU will pass access_type to IOMMU

permission. At least this mechanism has the correct behavior. Thanks, Jim On Thu, Jun 13, 2024 at 1:34 PM Ethan Chen wrote: > > On Wed, Jun 12, 2024 at 04:14:02PM +0800, Jim Shu wrote: > > [EXTERNAL MAIL] > > > > It is the preparation patch for upcoming RISC-V wgChecker de

Re: [RFC PATCH 01/16] accel/tcg: Store section pointer in CPUTLBEntryFull

t supported in QEMU, which is similar to MPC or wgChecker device.) Thanks, Jim Shu On Thu, Jun 13, 2024 at 2:23 PM LIU Zhiwei wrote: > > On 2024/6/12 16:14, Jim Shu wrote: > > 'CPUTLBEntryFull.xlat_section' stores section_index in last 12 bits to > >

[PATCH] vfio/pci: Fix null pointer deference from error API

pci_dev_realize() use the local error variable, which requires `error_setg()` API to allocate the error object at first. Signed-off-by: Jim Shu --- hw/vfio/pci.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/vfio/pci.c b/hw/vfio/pci.c index 0a99e55247..d994ad8bb9 100644

Re: [PATCH] vfio/pci: Fix null pointer deference from error API

On Thu, Sep 12, 2024 at 2:18 PM Cédric Le Goater wrote: > > Hello Jim, > > On 9/12/24 07:17, Jim Shu wrote: > > pci_dev_realize() use the local error variable, which requires > > `error_setg()` API to allocate the error object at first. > > > > Signed-off-by:

Re: [PATCH] vfio/pci: Fix null pointer deference from error API

On Thu, Sep 12, 2024 at 5:56 PM Cédric Le Goater wrote: > > Hello Jim, > > On 9/12/24 08:36, Jim Shu wrote: > > Hi Cédric, > > > > Thank you very much for the quick response! > > > > I have checked the error API again. It seems to be my porting issue o

[PATCH] target/riscv: Support SW update of PTE A/D bits and Ssptwad extension

ion is based on priv spec v1.12: "When a virtual page is accessed and the A bit is clear, or is written and the D bit is clear, a page-fault exception (corresponding to the original access type) is raised." Signed-off-by: Jim Shu Reviewed-by: Frank Chang --- target/riscv/cpu.c

Re: [PATCH] target/riscv: Support SW update of PTE A/D bits and Ssptwad extension

in RISC-V priv spec, so I think it's reasonable to implement them in QEMU. The only issue here is to choose a proper CPU option name to turn on/off HW update of A/D bits. Regards, Jim Shu On Mon, Jul 18, 2022 at 12:02 PM Anup Patel wrote: > +Atish > > On Mon, Jul 18, 2022 at 9

Re: [PATCH v4 00/14] Initial support for machine creation via QMP

Hi all, Thanks for the work! I'm from SiFive and we are very interested in this feature. QMP/QAPI configurable QEMU machine is a useful feature in our use case. With this feature, we can both model our versatile FPGA-based platforms more easily and model a new platform without modification of sou

Re: [PATCH v5 1/6] machine: add phase_get() and document phase_check()/advance()

Tested-by: Jim Shu On Thu, May 19, 2022 at 11:41 PM Damien Hedde wrote: > phase_get() returns the current phase, we'll use it in next > commit. > > Signed-off-by: Damien Hedde > Reviewed-by: Philippe Mathieu-Daudé > --- > include/hw/qdev-core.h | 19 +++

Re: [PATCH v5 6/6] qapi/device_add: Allow execution in machine initialized phase

Tested-by: Jim Shu On Thu, May 19, 2022 at 11:37 PM Damien Hedde wrote: > From: Mirela Grujic > > This commit allows to use the QMP command to add a cold-plugged > device like we can do with the CLI option -device. > > Note: for device_add command in qdev.json adding th

Re: [PATCH v5 4/6] qapi/device_add: compute is_hotplug flag

Tested-by: Jim Shu On Thu, May 19, 2022 at 11:37 PM Damien Hedde wrote: > Instead of checking the phase everytime, just store the result > in a flag. We will use more of it in the following commit. > > Signed-off-by: Damien Hedde > Reviewed-by: Philippe Mathieu-Daudé > -

Re: [PATCH v5 2/6] machine&vl: introduce phase_until() to handle phase transitions

Tested-by: Jim Shu On Thu, May 19, 2022 at 11:41 PM Damien Hedde wrote: > phase_until() is implemented in vl.c and is meant to be used > to make startup progress up to a specified phase being reached(). > At this point, no behavior change is introduced: phase_until() > only suppo

Re: [PATCH v5 3/6] vl: support machine-initialized target in phase_until()

Tested-by: Jim Shu On Thu, May 19, 2022 at 11:36 PM Damien Hedde wrote: > phase_until() now supports the following transitions: > + accel-created -> machine-initialized > + machine-initialized -> machine-ready > > As a consequence we can now support the use of qmp_ex

Re: [PATCH v4 05/14] qapi/device_add: handle the rom_order_override when cold-plugging

Tested-by: Jim Shu On Wed, Feb 23, 2022 at 5:18 PM Damien Hedde wrote: > rom_set_order_override() and rom_reset_order_override() were called > in qemu_create_cli_devices() to set the rom_order_override value > once and for all when creating the devices added on CLI. > > Unf

Re: [PATCH v4 07/14] none-machine: add the NoneMachineState structure

Tested-by: Jim Shu On Wed, Feb 23, 2022 at 5:59 PM Damien Hedde wrote: > The none machine was using the parent state structure. > We'll need a custom state to add a field in the following commit. > > Signed-off-by: Damien Hedde > --- > hw/c

Re: [PATCH v4 12/14] add sysbus-mmio-map qapi command

Tested-by: Jim Shu On Wed, Feb 23, 2022 at 5:37 PM Damien Hedde wrote: > This command allows to map an mmio region of sysbus device onto > the system memory. Its behavior mimics the sysbus_mmio_map() > function apart from the automatic unmap (the C function unmaps > the region if i

Re: [PATCH v4 08/14] none-machine: add 'ram-addr' property

Tested-by: Jim Shu On Fri, Mar 4, 2022 at 12:36 AM Damien Hedde wrote: > > > On 3/3/22 15:41, Philippe Mathieu-Daudé wrote: > > On 23/2/22 10:07, Damien Hedde wrote: > >> Add the property to configure a the base address of the ram. > >> The default value remai

Re: [PATCH v4 14/14] hw: set user_creatable on opentitan/sifive_e devices

Tested-by: Jim Shu On Fri, Mar 4, 2022 at 11:23 PM Philippe Mathieu-Daudé < philippe.mathieu.da...@gmail.com> wrote: > On 23/2/22 10:07, Damien Hedde wrote: > > The devices are: > > + ibex-timer > > + ibex-uart > > + riscv.aclint.swi > > + ris

Re: [PATCH v4 13/14] hw/mem/system-memory: add a memory sysbus device

Tested-by: Jim Shu On Wed, Feb 23, 2022 at 5:14 PM Damien Hedde wrote: > This device can be used to create a memory wrapped into a > sysbus device. > This device has one property 'readonly' which allows > to choose between a ram or a rom. > > The purpose for this de

Re: [PATCH v4 09/14] none-machine: allow cold plugging sysbus devices

Tested-by: Jim Shu On Thu, Mar 3, 2022 at 10:46 PM Philippe Mathieu-Daudé < philippe.mathieu.da...@gmail.com> wrote: > On 23/2/22 10:07, Damien Hedde wrote: > > Allow plugging any sysbus device on this machine (the sysbus > > devices still need to be 'user-creatable

Re: [PATCH v4 11/14] softmmu/memory: add memory_region_try_add_subregion function

Tested-by: Jim Shu On Fri, Mar 4, 2022 at 7:00 PM Damien Hedde wrote: > > > > On 3/3/22 14:32, Philippe Mathieu-Daudé wrote: > > On 23/2/22 10:12, Damien Hedde wrote: > >> Hi Philippe, > >> > >> I suppose it is ok if I change your mail in the rev

Re: [PATCH v3 0/2] Enhance maximum priority support of PLIC

Gentle ping. It's a patch for fix and spec alignment of PLIC. On Mon, Oct 3, 2022 at 12:14 PM Jim Shu wrote: > > This patchset fixes hard-coded maximum priority of interrupt priority > register and also changes this register to WARL field to align the PLIC > spec. >

[PATCH 2/2] target/riscv: Make the "virt" register writable by GDB

This patch also enables debugger to set current privilege mode to VU/VS-mode. Extend previous commit 81d2929c41d32af138f3562f5a7b309f6eac7ca7 to support H-extension. Signed-off-by: Jim Shu Reviewed-by: Frank Chang --- target/riscv/gdbstub.c | 18 -- 1 file changed, 16

[PATCH 1/2] target/riscv: Expose "virt" register for GDB for reads

This patch enables a debugger to read current virtualization mode via virtual "virt" register. After it, we could get full current privilege mode via both "priv" and "virt" register. Extend previous commit ab9056ff9bdb3f95db6e7a666d10522d289f14ec to support H-exte

[PATCH 0/2] Align SiFive PDMA behavior to real hardware

HiFive Unmatched PDMA supports high/low 32-bit access of 64-bit register, but QEMU emulation support low part access now. Enhance QEMU emulation to support high 32-bit access. Also, permit 4/8-byte valid access in PDMA as we have verified 32/64-bit accesses of PDMA registers are supported. Jim

[PATCH 2/2] hw/dma: sifive_pdma: permit 4/8-byte access size of PDMA registers

It's obvious that PDMA support 64-bit access of 64-bit registers, and in previous commit, we confirm that PDMA support 32-bit access of both 32/64-bit registers. Thus, we configure 32/64-bit memory access of PDMA registers as valid in general. Signed-off-by: Jim Shu Reviewed-by: Frank

[PATCH 1/2] hw/dma: sifive_pdma: support high 32-bit access of 64-bit register

2 80001000 0002 => md.l 0x28000 1; md.l 0x280001000 1 <= Dump src/dst memory contents 280000000: 12345678 xV4. 280001000: 12345678 xV4. Signed-off-by: Jim Shu Reviewed-by: Frank Chang --- hw/dma/sifiv

Re: [PATCH 1/2] hw/dma: sifive_pdma: support high 32-bit access of 64-bit register

Hi Bin, Thanks for the review. I will fix the commit log and the behavior of writing high 32-bit of RO registers in v2 patch. Thanks, Jim Shu On Tue, Jan 4, 2022 at 10:55 AM Bin Meng wrote: > Hi Jim, > > On Tue, Dec 28, 2021 at 8:53 AM Jim Shu wrote: > > > > Real PDM

[PATCH v2 2/2] hw/dma: sifive_pdma: permit 4/8-byte access size of PDMA registers

It's obvious that PDMA supports 64-bit access of 64-bit registers, and in previous commit, we confirm that PDMA supports 32-bit access of both 32/64-bit registers. Thus, we configure 32/64-bit memory access of PDMA registers as valid in general. Signed-off-by: Jim Shu Reviewed-by: Frank

[PATCH v2 1/2] hw/dma: sifive_pdma: support high 32-bit access of 64-bit register

2 80001000 0002 => md.l 0x28000 1; md.l 0x280001000 1 <= Dump src/dst memory contents 280000000: 12345678 xV4. 280001000: 12345678 xV4. Signed-off-by: Jim Shu Reviewed

[PATCH v2 0/2] Align SiFive PDMA behavior to real hardware

. Changelog: v2: * Fix high 32-bit write access of 64-bit RO registers * Fix commit log Jim Shu (2): hw/dma: sifive_pdma: support high 32-bit access of 64-bit register hw/dma: sifive_pdma: permit 4/8-byte access size of PDMA registers hw/dma/sifive_pdma.c | 181

Re: [PATCH v4 01/11] target/riscv: Add zimop extension

Reviewed-by: Jim Shu On Tue, Jul 9, 2024 at 7:39 PM LIU Zhiwei wrote: > Zimop extension defines an encoding space for 40 MOPs.The Zimop > extension defines 32 MOP instructions named MOP.R.n, where n is > an integer between 0 and 31, inclusive. The Zimop extension > additionally d

Re: [PATCH v4 02/11] disas/riscv: Support zimop disassemble

On Tue, Jul 9, 2024 at 7:41 PM LIU Zhiwei wrote: > Signed-off-by: LIU Zhiwei > Acked-by: Alistair Francis > Reviewed-by: Deepak Gupta > Reviewed-by: Jim Shu

Re: [PATCH v4 03/11] target/riscv: Add zcmop extension

cpu.c | 5 > target/riscv/translate.c| 1 + > 6 files changed, 39 insertions(+) > create mode 100644 target/riscv/insn_trans/trans_rvzcmop.c.inc > Reviewed-by: Jim Shu

Re: [PATCH v4 04/11] disas/riscv: Support zcmop disassemble

an be redefined by later extension. > > Signed-off-by: LIU Zhiwei > Acked-by: Alistair Francis > Reviewed-by: Deepak Gupta > --- > disas/riscv.c | 23 +++ > 1 file changed, 23 insertions(+) Reviewed-by: Jim Shu

[PATCH 1/2] include/elf.h: align ELF macro name with glibc

Rename DT_BINDNOW to DT_BIND_NOW to align with glibc header: "elf/elf.h" Signed-off-by: Jim Shu --- include/elf.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/elf.h b/include/elf.h index e7259ec366..ef47b5e2ad 100644 --- a/include/elf.h +++ b/inc

[PATCH 0/2] Let gen-vdso tool to use internal ELF header

Let gen-vdso tool to use QEMU's internal ELF header. It could avoid compatibility issue of glibc version in the environment. QEMU RISC-V zicfiss/lp extension patchset will add "EM_RISCV" symbol to it. This symbol is not supported in the legacy glibc. Jim Shu (2): include/elf.h:

[PATCH 2/2] linux-user: Add QEMU include path to vdso

Add include path to 'gen-vdso.c' to get ELF header in QEMU source. Signed-off-by: Jim Shu --- linux-user/meson.build | 5 - 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/linux-user/meson.build b/linux-user/meson.build index bc41e8c3bc..ccce4f7e70 100644 --- a/

[PATCH 1/4] hw/dma: xilinx_axidma: Correct the txlen value in the descriptor

Currently, txlen is always decremented to 0 before filling to the descriptor. Keep the origin txlen value to have the correct value of descriptor status field. It will fix the 'tx_bytes' statistic value in linux axi-ethernet driver. Signed-off-by: Jim Shu --- hw/dma/xilinx_ax

[PATCH 4/4] hw/net: xilinx_axienet: Fix DMA RX IRQ if ethernet disable RX

ckets when enabling it. Signed-off-by: Jim Shu --- hw/net/xilinx_axienet.c | 71 - 1 file changed, 42 insertions(+), 29 deletions(-) diff --git a/hw/net/xilinx_axienet.c b/hw/net/xilinx_axienet.c index 05d41bd548..8428f10946 100644 --- a/hw/net/xilinx_axie

[PATCH 3/4] hw/dma: xilinx_axidma: Reset qemu_irq when DMA/Stream is reset

Current DMA/Stream reset will clear interrupt pending bit of DMA device. The qemu_irq of device should be updated at the same time. Signed-off-by: Jim Shu --- hw/dma/xilinx_axidma.c | 25 + 1 file changed, 13 insertions(+), 12 deletions(-) diff --git a/hw/dma

[PATCH 2/4] hw/dma: xilinx_axidma: Send DMA error IRQ if any memory access is failed

The memory transactions from DMA could have bus-error in some cases. If it is failed, DMA device should send error IRQs. Signed-off-by: Jim Shu --- hw/dma/trace-events| 1 + hw/dma/xilinx_axidma.c | 69 ++ 2 files changed, 50 insertions(+), 20

[PATCH 0/4] Several fixes of AXI-ethernet/DMA

Fix txlen value in the descriptor status field, DMA error handling, and ethernet/DMA reset flow. *** BLURB HERE *** Jim Shu (4): hw/dma: xilinx_axidma: Correct the txlen value in the descriptor hw/dma: xilinx_axidma: Send DMA error IRQ if any memory access is failed hw/dma

Re: [PATCH 0/2] Let gen-vdso tool to use internal ELF header

Hi Richard, Thanks for your feedback. I think it is reasonable. I will drop this patchset. Regards, Jim Shu On Fri, Jul 26, 2024 at 1:28 PM Richard Henderson wrote: > > On 7/26/24 14:32, Jim Shu wrote: > > Let gen-vdso tool to use QEMU's internal ELF header. It could avoid

Re: [PATCH 4/4] hw/net: xilinx_axienet: Fix DMA RX IRQ if ethernet disable RX

Shu. On Mon, Jul 29, 2024 at 11:31 PM Peter Maydell wrote: > > On Fri, 26 Jul 2024 at 06:59, Jim Shu wrote: > > > > When AXI ethernet RX is disabled, it shouldn't send packets to AXI DMA, > > which may let AXI DMA to send RX full IRQs. It is aligned with real AXI &g

Re: [PATCH 3/4] hw/dma: xilinx_axidma: Reset qemu_irq when DMA/Stream is reset

Hi Peter, Except DeviceState::reset(), stream_reset() is only used in axidma_write() and axidma_write() has qemu_set_irq() at the end of function. I think this commit could be dropped. I will remove it in the v2 patchset. Thanks, Jim Shu On Mon, Jul 29, 2024 at 11:23 PM Peter Maydell wrote

[PATCH v2 2/3] hw/dma: xilinx_axidma: Send DMA error IRQ if any memory access is failed

The memory transactions from DMA could have bus-error in some cases. If it is failed, DMA device should send error IRQs. Signed-off-by: Jim Shu --- hw/dma/trace-events| 1 + hw/dma/xilinx_axidma.c | 69 ++ 2 files changed, 50 insertions(+), 20

[PATCH v2 1/3] hw/dma: xilinx_axidma: Correct the txlen value in the descriptor

Currently, txlen is always decremented to 0 before filling to the descriptor. Keep the origin txlen value to have the correct value of descriptor status field. It will fix the 'tx_bytes' statistic value in linux axi-ethernet driver. Signed-off-by: Jim Shu --- hw/dma/xilinx_ax

[PATCH v2 0/3] Several fixes of AXI-ethernet/DMA

v2: - Remove redundant RCW1_RX checking in enet_write() - Remove qemu_set_irq() in DeviceState::reset() Fix txlen value in the descriptor status field, DMA error handling, and ethernet/DMA reset flow. Jim Shu (3): hw/dma: xilinx_axidma: Correct the txlen value in the descriptor hw/dma

[PATCH v2 3/3] hw/net: xilinx_axienet: Fix DMA RX IRQ if ethernet disable RX

ckets when enabling it. Signed-off-by: Jim Shu --- hw/net/xilinx_axienet.c | 71 - 1 file changed, 42 insertions(+), 29 deletions(-) diff --git a/hw/net/xilinx_axienet.c b/hw/net/xilinx_axienet.c index 05d41bd548..0ecdc30be6 100644 --- a/hw/net/xilinx_axie

[PATCH 2/3] target/riscv: add log of PMP permission checking

Like MMU translation, add qemu log of PMP permission checking for debugging. Signed-off-by: Jim Shu --- target/riscv/cpu_helper.c | 12 1 file changed, 12 insertions(+) diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index f6ac63bf0e..c1ecb8a710 100644 --- a

[PATCH 3/3] target/riscv: flush TLB pages if PMP permission has been changed

If PMP permission of any address has been changed by updating PMP entry, flush all TLB pages to prevent from getting old permission. Signed-off-by: Jim Shu --- target/riscv/pmp.c | 4 1 file changed, 4 insertions(+) diff --git a/target/riscv/pmp.c b/target/riscv/pmp.c index ebd874cde3

[PATCH 3/3] target/riscv: flush TLB pages if PMP permission has been changed

If PMP permission of any address has been changed by updating PMP entry, flush all TLB pages to prevent from getting old permission. Signed-off-by: Jim Shu --- target/riscv/pmp.c | 4 1 file changed, 4 insertions(+) diff --git a/target/riscv/pmp.c b/target/riscv/pmp.c index ebd874cde3

[PATCH 2/3] target/riscv: add log of PMP permission checking

Like MMU translation, add qemu log of PMP permission checking for debugging. Signed-off-by: Jim Shu --- target/riscv/cpu_helper.c | 12 1 file changed, 12 insertions(+) diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index f6ac63bf0e..c1ecb8a710 100644 --- a

[PATCH 0/3] target/riscv: fix PMP permission checking when softmmu's TLB hits

PMP permission. To fix this issue, this patch set addes the feature to propagate PMP permission to the TLB page and flush TLB pages if PMP permission has been changed. The patch set is tested on Zephyr RTOS userspace testsuite on QEMU riscv32 virt machine. Jim Shu (3): target/riscv: propagate PM

[PATCH 1/3] target/riscv: propagate PMP permission to TLB page

Currently, PMP permission checking of TLB page is bypassed if TLB hits Fix it by propagating PMP permission to TLB page permission. PMP permission checking also use MMU-style API to change TLB permission and size. Signed-off-by: Jim Shu --- target/riscv/cpu_helper.c | 84

[PATCH 1/3] target/riscv: propagate PMP permission to TLB page

Currently, PMP permission checking of TLB page is bypassed if TLB hits Fix it by propagating PMP permission to TLB page permission. PMP permission checking also use MMU-style API to change TLB permission and size. Signed-off-by: Jim Shu --- target/riscv/cpu_helper.c | 84

[PATCH 1/2] hw/riscv: Support to load DTB after 3GB memory on 64-bit system.

Larger initrd image will overlap the DTB at 3GB address. Since 64-bit system doesn't have 32-bit addressable issue, we just load DTB to the end of dram in 64-bit system. Signed-off-by: Jim Shu --- hw/riscv/boot.c| 8 ++-- hw/riscv/microchip_pfsoc.c | 4 ++-- hw/riscv/sifiv

[PATCH 2/2] hw/riscv: Support different address-cells for initrd

The cells of 'initrd-start/end' should follow the '#address-cell'. QEMU API could support 1 and 2 cells. Signed-off-by: Jim Shu --- hw/riscv/boot.c | 14 -- 1 file changed, 12 insertions(+), 2 deletions(-) diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c index ad

[PATCH 0/2] Support 64-bit address of initrd

Support to load DTB after 3GB on RV64 system, so that larger initrd doesn't be overlapped to DTB. Update initrd DT to support different "#address-cells". Verify the patch via running 4GB initramfs on the virt machine. Jim Shu (2): hw/riscv: Support to load DTB after 3GB memory o

Re: [PATCH 1/2] hw/riscv: Support to load DTB after 3GB memory on 64-bit system.

On Mon, Oct 21, 2024 at 9:42 PM Daniel Henrique Barboza wrote: > > > > On 10/21/24 1:09 AM, Jim Shu wrote: > > Larger initrd image will overlap the DTB at 3GB address. Since 64-bit > > system doesn't have 32-bit addressable issue, we just load DTB to the end

Re: [PATCH 2/2] hw/riscv: Support different address-cells for initrd

in.com/linux/v6.11.4/source/drivers/of/fdt.c#L785 [2] https://elixir.bootlin.com/linux/v6.11.4/source/drivers/of/fdt.c#L857 Thanks, Jim Shu On Tue, Oct 22, 2024 at 3:30 AM Daniel Henrique Barboza wrote: > > > > On 10/21/24 1:09 AM, Jim Shu wrote: > > The cells of 'initrd-

Re: [PATCH 2/2] target/riscv/kvm: Update kvm exts to Linux v6.11

Reviewed-by: Jim Shu On Tue, Sep 24, 2024 at 9:24 PM Andrew Jones wrote: > > On Tue, Sep 24, 2024 at 04:30:01PM GMT, zhouq...@iscas.ac.cn wrote: > > From: Quan Zhou > > > > Add support for a few Zc* extensions, Zimop, Zcmop and Zawrs. > > > > Signed-off-by:

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