Having recently written a driver for the Goldfish TTY for NetBSD, I found it a
bit odd (and a little annoying) that the device has a PUT_CHAR register but not
a GET_CHAR register, something particularly useful for early-console or
in-kernel debugger use. As it stands, to get a single character
> On Jan 10, 2024, at 8:01 AM, Philippe Mathieu-Daudé wrote:
>
> IIUC Goldfish virtual HW is maintained externally by Google
> https://android.googlesource.com/platform/external/qemu/+/master/docs/GOLDFISH-VIRTUAL-HARDWARE.TXT
>
> I suppose the spec needs to be updated before the change can be
Don't include system headers. Instead, provide standalone definitions
and declarations of types needed and functions used by the PALcode that
are compatible with the standard Alpha / GCC ABI.
Signed-off-by: Jason Thorpe
---
init.c | 2 --
memcpy.c | 2 +-
memset.c | 2 +-
printf.c
In the unaligned access exception vector, actually pass the return PC
in the exception frame. This is required in order for unaligned access
fixup handlers in the operating system to work.
Signed-off-by: Jason Thorpe
---
pal.S | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a
is allowed by the architecture specification.
Signed-off-by: Jason Thorpe
---
init.c | 25 -
pal.S | 13 ++---
2 files changed, 26 insertions(+), 12 deletions(-)
diff --git a/init.c b/init.c
index aee5cef..bfe4d96 100644
--- a/init.c
+++ b/init.c
@@ -313,14
Block in the HWRPB.
Jason Thorpe (8):
Make qemu-palcode build environment standalone. NFC.
Fix delivery of unaligned access exceptions.
Fix initialization of the hwrpb.hwrpb.cpuid field.
Make some PCI macros available to other files. NFC.
Fix incorrect initialization of PCI BARs
include
some configuration flags, in addition to the CPU count, and define
a flag to mirror the "-nographics" option.
- We need to initialize the HWRPB *after* initializing VGA, so that
we'll know if a VGA device is present and in which slot for filling
out the CTB.
Signe
.
Signed-off-by: Jason Thorpe
---
pci.c | 20 +++-
sys-clipper.h | 27 +++
2 files changed, 46 insertions(+), 1 deletion(-)
diff --git a/pci.c b/pci.c
index 5e9c906..e3cab26 100644
--- a/pci.c
+++ b/pci.c
@@ -29,6 +29,7 @@
#include "protos.h"
Initialize the hwrpb.hwrpb.cpuid field with the primary CPU ID, not
the processor type, as per the architecture specification. Some
operating systems check and assert this.
Improve a couple of comments.
Signed-off-by: Jason Thorpe
---
init.c | 29 ++---
1 file changed
Move PCI_DEVFN(), PCI_BUS(), PCI_SLOT(), and PCI_FUNC() to pci.h.
Signed-off-by: Jason Thorpe
---
pci.c | 4
pci.h | 5 +
2 files changed, 5 insertions(+), 4 deletions(-)
diff --git a/pci.c b/pci.c
index 87a101c..ba05adb 100644
--- a/pci.c
+++ b/pci.c
@@ -31,10 +31,6 @@
#include
Only program a BAR as a 64-bit MEM BAR if it really is a 64-bit MEM BAR.
Fixes an issue with the CMD646 IDE controller under NetBSD.
Improve some debug/info messages.
Signed-off-by: Jason Thorpe
---
pci.c | 7 ---
1 file changed, 4 insertions(+), 3 deletions(-)
diff --git a/pci.c b/pci.c
> On Oct 14, 2020, at 2:52 PM, Richard Henderson
> wrote:
>
> I'm certainly open to these changes. But it'll need to be split up -- one
> patch per bullet, basically.
That's fine. What's the convention for patches that stack on top of one
another?
-- thorpej
> On Aug 18, 2021, at 12:58 AM, Mark Cave-Ayland
> wrote:
>
> On 31/07/2021 16:41, Jason Thorpe wrote:
>
> (added Michael on CC)
>
> Hi Jason,
>
> Thanks for looking at this! I've had previous discussions with Martin trying
> to figure out why v
> On Jun 3, 2021, at 2:24 AM, Philippe Mathieu-Daudé wrote:
>
> Hi Jason,
>
> On 6/3/21 5:53 AM, Jason Thorpe wrote:
>> Only program a BAR as a 64-bit MEM BAR if it really is a 64-bit MEM BAR.
>> Fixes an issue with the CMD646 IDE controller under N
> On Jun 6, 2021, at 12:27 PM, Richard Henderson
> wrote:
>
> On 6/2/21 8:53 PM, Jason Thorpe wrote:
>> + hwrpb.hwrpb.ctbt_offset = offsetof(struct hwrpb_combine, ctb);
>> + hwrpb.hwrpb.ctb_size = sizeof(hwrpb.ctb);
>> + if (have_vg
guess based on available documentation and observed
behavior of real machines, and is sufficient for the BSD operating systems.
Jason Thorpe (1):
Provide a minimal Console Terminal Block in the HWRPB.
hwrpb.h | 54 ++
init.c | 36
ng VGA, so that
we'll know if a VGA device is present and in which slot for filling
out the CTB.
Signed-off-by: Jason Thorpe
---
hwrpb.h | 54 ++
init.c | 36 +---
protos.h | 2 ++
vgaio.c | 2 ++
4 fi
datasheet.
Signed-off-by: Jason Thorpe
---
hw/rtc/mc146818rtc.c | 4
1 file changed, 4 deletions(-)
diff --git a/hw/rtc/mc146818rtc.c b/hw/rtc/mc146818rtc.c
index 4fbafddb22..366b8f13de 100644
--- a/hw/rtc/mc146818rtc.c
+++ b/hw/rtc/mc146818rtc.c
@@ -155,10 +155,6 @@ static uint32_t
ion is not specified.
Jason Thorpe (4):
mc146818rtc: Make PF independent of PIE
alpha: Set minimum PCI device ID to 1 to match Clipper IRQ mappings.
alpha: Provide a PCI-ISA bridge device node for guest OS's that expect
it
alpha: Provide console information to the PALcode at start-u
devices if a PCI-ISA or PCI-EISA bridge is found.
Signed-off-by: Jason Thorpe
---
hw/alpha/typhoon.c | 111 -
1 file changed, 109 insertions(+), 2 deletions(-)
diff --git a/hw/alpha/typhoon.c b/hw/alpha/typhoon.c
index fa31a2f286..de01828d23 100644
--- a
us().
- In clipper_init(), pass PCI_DEVFN(1, 0) as the minimum PCI device
ID/function.
Signed-off-by: Jason Thorpe
---
hw/alpha/alpha_sys.h | 2 +-
hw/alpha/dp264.c | 5 +++--
hw/alpha/typhoon.c | 5 +++--
3 files changed, 7 insertions(+), 5 deletions(-)
diff --git a/hw/alpha/alpha_sys.h
Redefine the a2 register passed by Qemu at start-up to also include
some configuration flags, in addition to the CPU count, and define
a flag to mirror the "-nographics" option.
Signed-off-by: Jason Thorpe
---
hw/alpha/dp264.c | 11 +++
1 file changed, 11 insertions(+)
diff
Hey folks —
I’d like to be able to use VirtIO with qemu-system-alpha but, at least on a
NetBSD x86_64 host, it does not currently work. This is because
virtio_bus_device_plugged() in hw/virtio/virtio-bus.c ends up picking
address_space_memory as the DMA address space for the VirtIODevice. Thi
> On Jun 13, 2021, at 2:09 PM, Jason Thorpe wrote:
>
> but there is still some research going on about how
> real DEC SRM initializes a particular field in various circumstances;
> this is my best guess based on available documentation and observed
> behavior of rea
> On Jun 14, 2021, at 9:20 PM, Richard Henderson
> wrote:
>
> On 6/13/21 2:15 PM, Jason Thorpe wrote:
>> +/* The following was copied from hw/isa/i82378.c and modified to provide
>> + only the minimal PCI device node. */
>> +
>> +/*
>> + * QEMU
> On Jun 14, 2021, at 9:24 PM, Jason Thorpe wrote:
>> Why can't we just use the existing device model?
>> Certainly duplicating code like this isn't the best way.
>
> Yah, I’m not super happy with that, either, tbh. When I first started
> working on this se
an i82378 instance, and connect its
PIC output to the ISA IRQ input provided by typhoon_init(). Remove
the explicit instantiations of i8254 and i82374, as these devices
are subsumed by the i82378.
Signed-off-by: Jason Thorpe
---
hw/alpha/Kconfig | 1 +
hw/alpha/alpha_sys.h | 2 +-
hw
> On Jun 14, 2021, at 9:17 PM, Richard Henderson
> wrote:
>
> Cc: paolo and mst
>
> On 6/13/21 2:15 PM, Jason Thorpe wrote:
>> Make the PF flag behave like real hardware by always running the
>> periodic timer without regard to the setting of the PIE bit, so
&
> On Jun 19, 2021, at 8:56 AM, Philippe Mathieu-Daudé wrote:
>
> Hi Jason,
>
> Do you mind reposting this single patch including the DS quote
> in the description?
Sure, no problem. Will do so shortly.
-- thorpej
datasheet.
Signed-off-by: Jason Thorpe
---
hw/rtc/mc146818rtc.c | 21 ++---
1 file changed, 18 insertions(+), 3 deletions(-)
diff --git a/hw/rtc/mc146818rtc.c b/hw/rtc/mc146818rtc.c
index 4fbafddb22..85abdfd9d1 100644
--- a/hw/rtc/mc146818rtc.c
+++ b/hw/rtc/mc146818rtc.c
@@ -155,9
> On Jun 21, 2021, at 10:10 AM, Richard Henderson
> wrote:
>
> This bit is used by NetBSD for lazy fpu migration.
>
> Reported-by: Jason Thorpe
> Resolves: https://gitlab.com/qemu-project/qemu/-/issues/438
> Signed-off-by: Richard Henderson
Applied patch loca
> On Jun 21, 2021, at 7:46 AM, Paolo Bonzini wrote:
> I agree that there's obviously a bug in QEMU. However, I'm worried of two
> things with this patch.
>
> First, the RTC device model has a complicated mechanism to deliver missed
> ticks of the periodic timer. This is used with old vers
As a "learn the internals of Qemu a little better" exercise, I am planning to
write models for some older Alpha systems, initially for one based on the
LCA45. One of the quirks of these old systems, though, is lack of byte/word
load/store. So, to support 8- and 16-bit accesses to I/O devices,
> On Jun 23, 2021, at 5:42 PM, Philippe Mathieu-Daudé wrote:
>
>> I'm trying to wrap my head around how to achieve this in Qemu. I don't see
>> an obvious way from my initial study of how the PCI code and memory regions
>> work. Some guidance would be appreciated!
>
> Is bitband_ops[] usef
incorrectly.
- When configuring the PCI bus, program system-specific interrupt routing
information into the PCI device "line" register (as SRM does).
- When building the PALcode, don't include outside header files; put everything
that's needed in protos.h.
Signed-off-by:
operating sytems are not picky about the specific
model.
- Modify the mc146818rtc emulation to ensure the timer is started as soon
as the device is realized, and update the PF bit in REG_C even if it is
not going to result in raising an interrupt, as the real hardware does.
Signed-off-by: J
> On Oct 6, 2020, at 9:42 PM, Philippe Mathieu-Daudé wrote:
>
> Hi Jason,
>
> Well, this is not the correct way to do that, so this patch
> is unlikely to be accepted. We don't want Frankenstein models.
>
> What is it you miss from the i82378? Why not implement the cy82c693ub?
>
> The code y
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