Initialize the hwrpb.hwrpb.cpuid field with the primary CPU ID, not
the processor type, as per the architecture specification. Some
operating systems check and assert this.
Improve a couple of comments.
Signed-off-by: Jason Thorpe <thor...@me.com>
---
init.c | 29 ++++++++++++++++++++++-------
1 file changed, 22 insertions(+), 7 deletions(-)
diff --git a/init.c b/init.c
index 429a9ad..b3919b6 100644
--- a/init.c
+++ b/init.c
@@ -141,6 +141,7 @@ init_hwrpb (unsigned long memsize, unsigned long cpus)
unsigned long pal_pages;
unsigned long amask;
unsigned long i;
+ unsigned long proc_type = EV4_CPU;
hwrpb.hwrpb.phys_addr = PA(&hwrpb);
@@ -162,12 +163,12 @@ init_hwrpb (unsigned long memsize, unsigned long cpus)
switch (__builtin_alpha_implver())
{
case 0: /* EV4 */
- hwrpb.hwrpb.cpuid = EV4_CPU;
+ proc_type = EV4_CPU;
hwrpb.hwrpb.max_asn = 63;
break;
case 1: /* EV5 */
- hwrpb.hwrpb.cpuid
+ proc_type
= ((amask & 0x101) == 0x101 ? PCA56_CPU /* MAX+BWX */
: amask & 1 ? EV56_CPU /* BWX */
: EV5_CPU);
@@ -175,11 +176,16 @@ init_hwrpb (unsigned long memsize, unsigned long cpus)
break;
case 2: /* EV6 */
- hwrpb.hwrpb.cpuid = (amask & 4 ? EV67_CPU : EV6_CPU); /* CIX */
+ proc_type = (amask & 4 ? EV67_CPU : EV6_CPU); /* CIX */
hwrpb.hwrpb.max_asn = 255;
break;
}
+ /* This field is the WHAMI of the primary CPU. Just initialize
+ this to 0; CPU #0 is always the primary on real Alpha systems
+ (except for the TurboLaser). */
+ hwrpb.hwrpb.cpuid = 0;
+
hwrpb.hwrpb.pagesize = PAGE_SIZE;
hwrpb.hwrpb.pa_bits = 40;
hwrpb.hwrpb.sys_type = SYS_TYPE;
@@ -187,9 +193,18 @@ init_hwrpb (unsigned long memsize, unsigned long cpus)
hwrpb.hwrpb.sys_revision = SYS_REVISION;
for (i = 0; i < cpus; ++i)
{
- /* ??? Look up these bits. Snagging the value examined by the kernel. */
+ /* Set the following PCS flags:
+ (bit 2) Processor Available
+ (bit 3) Processor Present
+ (bit 6) PALcode Valid
+ (bit 7) PALcode Memory Valid
+ (bit 8) PALcode Loaded
+
+ ??? We really should be intializing the PALcode memory and
+ scratch space fields if we're setting PMV, or not set PMV,
+ but Linux checks for it, so... */
hwrpb.processor[i].flags = 0x1cc;
- hwrpb.processor[i].type = hwrpb.hwrpb.cpuid;
+ hwrpb.processor[i].type = proc_type;
}
hwrpb.hwrpb.intr_freq = HZ * 4096;
@@ -257,8 +272,8 @@ init_i8259 (void)
outb(0x04, PORT_PIC1_DATA); /* ICW3: slave control INTC2 */
outb(0x01, PORT_PIC1_DATA); /* ICW4 */
- /* Initialize level triggers. The CY82C693UB that's on real alpha
- hardware doesn't have this; this is a PIIX extension. However,
+ /* Initialize level triggers. The CY82C693UB that's on some real alpha
+ systems controls these differently; we assume a PIIX here. However,
QEMU doesn't implement regular level triggers. */
outb(0xff, PORT_PIC2_ELCR);
outb(0xff, PORT_PIC1_ELCR);
--
2.30.2
