Currently, the size of the "regs" array is 0x2000, which is too large. So far,
it only uses "GICINT128 to `GICINT134", and the offsets from 0 to 0x1000 are
unused. To save code size and avoid mapping large unused gaps, update to only
map the useful set of registers:
INTC register [0x1000 – 0x1804]
Currently, these IRQ tables support from GIC 128 - 136 for AST2700 A0.
These IRQ tables can be reused for AST2700 A1 from GIC 192 - 197.
Updates the interrupt mapping to include support for AST2700 A1 by extending
the existing mappings to the new GIC range.
Signed-off-by: Jamin Lin
---
hw/arm/as
Signed-off-by: Jamin Lin
---
tests/functional/test_aarch64_aspeed.py | 12 ++--
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/tests/functional/test_aarch64_aspeed.py
b/tests/functional/test_aarch64_aspeed.py
index 07b0c7c1fd..8df6a97a28 100755
--- a/tests/functional/test_
The previous implementation set the "aspeed_intc_ops" struct, containing read
and write callbacks, to be used when I/O is performed on the INTC region.
Both "aspeed_intc_read" and "aspeed_intc_write" callback functions were used
for INTC (CPU Die).
To support the INTCIO (IO Die) model, introduces
Signed-off-by: Jamin Lin
---
tests/functional/test_aarch64_aspeed.py | 10 ++
1 file changed, 10 insertions(+)
diff --git a/tests/functional/test_aarch64_aspeed.py
b/tests/functional/test_aarch64_aspeed.py
index 8df6a97a28..c25c966278 100755
--- a/tests/functional/test_aarch64_aspeed.py
The memory map for AST2700 A1 remains compatible with AST2700 A0. However, the
IRQ mapping has been updated for AST2700 A1, with GIC interrupts now ranging
from 192 to 201. Add a new IRQ map table for AST2700 A1.
Add "aspeed_soc_ast2700a1_class_init" to initialize the AST2700 A1 SoC.
Introduce "asp
The behavior of the INTC set IRQ is almost identical between INTC and INTCIO.
To reduce duplicated code, introduce the "aspeed_intc_set_irq_handler" function
to handle both INTC and INTCIO IRQ behavior. No functional change.
Signed-off-by: Jamin Lin
Reviewed-by: Cédric Le Goater
---
hw/intc/asp
Added new definitions for AST2700_A1_SILICON_REV and AST2750_A1_SILICON_REV to
identify the A1 silicon revisions.
Signed-off-by: Jamin Lin
Reviewed-by: Cédric Le Goater
---
include/hw/misc/aspeed_scu.h | 2 ++
hw/misc/aspeed_scu.c | 2 ++
2 files changed, 4 insertions(+)
diff --git a/i
Currently, the size of the regs array is 0x2000, which is too large. So far,
it only use GICINT128 - GICINT134, and the offsets from 0 to 0x1000 are unused.
To save code size, introduce a new class attribute "reg_size" to set the
different register sizes for the INTC models in AST2700 and add a reg
v1: This patch series is from
https://patchwork.kernel.org/project/qemu-devel/cover/20250213033531.3367697-1-jamin_...@aspeedtech.com/.
To expedite the review process, I have separated the SCU fix patches
a. Fix the hw-strap and revision ID for SCU and SCUIO
b. ix boot issue for AST2700
Ja
Currently, ASPEED_DEV_SPI_BOOT is set to "0x4", which is the DRAM start
address, and the QEMU loader is used to load the U-Boot binary into this
address.
However, if users want to install FMC flash contents as a boot ROM, the DRAM
address 0x4 would be overwritten with Boot ROM dat
According to the design of the AST2600, it has a Silicon Revision ID Register,
specifically SCU004 and SCU014, to set the Revision ID for the AST2600.
For the AST2600 A3, SCU004 is set to 0x05030303 and SCU014 is set to 0x05030303.
In the "aspeed_ast2600_scu_reset" function, the hardcoded value
"AS
There is one hw-strap1 register in the SCU (CPU DIE) and another hw-strap1
register in the SCUIO (IO DIE). The values of these two registers should not be
the same. To reuse the current design of hw-strap, hw-strap1 is assigned to the
SCU and sets the value in the SCU hw-strap1 register, while hw-s
There is one hw_strap1 register in the SCU (CPU DIE) and another hw_strap1
register in the SCUIO (IO DIE).
In the "ast2700_a0_resets" function, the hardcoded value "0x0800" is set in
SCU hw-strap1 (CPU DIE), and in "ast2700_a0_resets_io" the hardcoded value
"0x0504" is set in SCUIO hw-stra
Setting BIT6 in VGA0 SCRATCH register will indicate that the ddr traning
is done, therefore skipping the u-boot-spl dram_init() process.
Signed-off-by: Jamin Lin
Signed-off-by: Troy Lee
---
hw/misc/aspeed_scu.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/hw/misc/aspeed_scu.c b/hw/misc
Separate HW Strap Registers for SCU and SCUIO.
AST2700_EVB_HW_STRAP1 is used for the SCU (CPU Die) hw-strap1.
AST2700_EVB_HW_STRAP2 is used for the SCUIO (IO Die) hw-strap1.
Additionally, both default values are updated based on the dump from the EVB.
Signed-off-by: Jamin Lin
---
hw/arm/aspeed.
v1:
1. Refactor INTC model to support both INTC0 and INTC1.
2. Support AST2700 A1.
3. Create ast2700a0-evb machine.
v2:
To streamline the review process, split the following patch series into
three parts.
https://patchwork.kernel.org/project/qemu-devel/cover/20250121070424.2465942-1-jam
v1:
1. Refactor INTC model to support both INTC0 and INTC1.
2. Support AST2700 A1.
3. Create ast2700a0-evb machine.
v2:
To streamline the review process, split the following patch series into
three parts.
https://patchwork.kernel.org/project/qemu-devel/cover/20250121070424.2465942-1-jam
Added new definitions for AST2700_A1_SILICON_REV and AST2750_A1_SILICON_REV to
identify the A1 silicon revisions.
Signed-off-by: Jamin Lin
Reviewed-by: Cédric Le Goater
---
include/hw/misc/aspeed_scu.h | 2 ++
hw/misc/aspeed_scu.c | 2 ++
2 files changed, 4 insertions(+)
diff --git a/i
Rename the variables "status_addr" to "status_reg" and "addr" to "reg" because
they are used as register index. This change makes the code more appropriate
and improves readability.
Signed-off-by: Jamin Lin
Reviewed-by: Cédric Le Goater
---
hw/intc/aspeed_intc.c | 38 +++
In ASPEED SDK v09.05, the naming convention for pre-built images has been
updated. The pre-built image for AST2700 A0 has been renamed to
ast2700-a0-default, while ast2700-default is now used for AST2700 A1.
Signed-off-by: Jamin Lin
Reviewed-by: Cédric Le Goater
---
tests/functional/test_aarch6
Currently, the size of the "regs" array is 0x2000, which is too large. To save
code size and avoid mapping large unused gaps, will update it to only map the
useful set of registers. This update will support multiple sub-regions with
different sizes.
To address the redundant size issue, replace the
The INTC controller supports GICINT128 to GICINT136, mapping 1:1 to input and
output IRQs 0 to 8. Previously, the formula "address & 0x0f00" was used to
derive the IRQ index numbers.
However, the INTC controller also supports GICINT192_201, mapping 1 input IRQ
pin to 10 output IRQ pins. The pin nu
Refactors the INTC to distinguish between input and output pin indices,
improving interrupt handling clarity and accuracy.
Updated the functions to handle both input and output pin indices.
Added detailed logging for input and output pin indices in trace events.
These changes ensure that the INTC
The INTC controller supports GICINT128 to GICINT136, mapping 1:1 to input and
output IRQs 0 to 8. Previously, the formula "address & 0x0f00" was used to
derive the IRQ index numbers.
However, the INTC controller also supports GICINT192_201, mapping 1 input IRQ
pin to 10 output IRQ pins. The pin nu
The previous implementation set the "aspeed_intc_ops" struct, containing read
and write callbacks, to be used when I/O is performed on the INTC region.
Both "aspeed_intc_read" and "aspeed_intc_write" callback functions were used
for INTC (CPU Die).
To support the INTCIO (IO Die) model, introduces
According to the AST2700 datasheet, the INTC(CPU DIE) controller has 16KB
(0x4000) of register space, and the INTCIO (I/O DIE) controller has 1KB (0x400)
of register space.
Introduced a new class attribute "mem_size" to set different memory sizes for
the INTC models in AST2700.
Signed-off-by: Jam
Currently, the size of the "regs" array is 0x2000, which is too large. So far,
it only uses "GICINT128 to `GICINT134", and the offsets from 0 to 0x1000 are
unused. To save code size and avoid mapping large unused gaps, update to only
map the useful set of registers:
INTC register [0x1000 – 0x1804]
The design of INTC controllers has significantly changed in AST2700 A1.
There are a total of 480 interrupt sources in AST2700 A1. For interrupt numbers
from 0 to 127, they can route directly to PSP, SSP, and TSP. Due to the
limitation of interrupt numbers of processors, the interrupts are merged e
Introduce "aspeed_machine_ast2700a1_evb_class_init" to initialize the
AST2700 A1 EVB.
Signed-off-by: Jamin Lin
Reviewed-by: Cédric Le Goater
---
hw/arm/aspeed.c | 24
1 file changed, 24 insertions(+)
diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c
index 18f7c450da..82f4
Add AST2700 INTC design guidance and its block diagram.
Signed-off-by: Jamin Lin
Reviewed-by: Cédric Le Goater
---
docs/specs/aspeed-intc.rst | 136 +
docs/specs/index.rst | 1 +
2 files changed, 137 insertions(+)
create mode 100644 docs/specs/aspeed
Currently, these IRQ tables support from GIC 128 - 136 for AST2700 A0.
These IRQ tables can be reused for AST2700 A1 from GIC 192 - 197.
Updates the interrupt mapping to include support for AST2700 A1 by extending
the existing mappings to the new GIC range.
Signed-off-by: Jamin Lin
Reviewed-by: C
Introduce a new ast2700 INTCIO class to support AST2700 INTCIO.
Added new register definitions for INTCIO, including enable and status
registers for IRQs GICINT192 through GICINT197.
Created a dedicated IRQ array for INTCIO, supporting six input pins and six
output pins, aligning with the newly def
This update introduces support for handling multi-output IRQs in the AST2700
interrupt controller (INTC), specifically for GICINT192_201. GICINT192_201 maps
1:10 to input IRQ 0 and output IRQs 0 to 9. Each status bit corresponds to a
specific IRQ.
Implemented "aspeed_intc_set_irq_handler_multi_out
Currently, these trace events only refer to INTC. To simplify the INTC model,
both INTC(CPU Die) and INTCIO(IO Die) will share the same helper functions.
However, it is difficult to recognize whether these trace events are comes from
INTC or INTCIO. To make these trace events more readable, adds o
The behavior of the INTC set IRQ is almost identical between INTC and INTCIO.
To reduce duplicated code, introduce the "aspeed_intc_set_irq_handler" function
to handle both INTC and INTCIO IRQ behavior. No functional change.
Signed-off-by: Jamin Lin
Reviewed-by: Cédric Le Goater
---
hw/intc/asp
Updated Aspeed27x0SoCState to include an intc[2] array instead of a single
AspeedINTCState instance. Modified aspeed_soc_ast2700_get_irq and
aspeed_soc_ast2700_get_irq_index to correctly reference the corresponding
interrupt controller instance and OR gate index.
Currently, only GIC 192 to 201 are
Added support for multiple output pins in the INTC controller to
accommodate the AST2700 A1.
Introduced "num_outpins" to represent the number of output pins. Updated the
IRQ handling logic to initialize and connect output pins separately from input
pins. Modified the "aspeed_soc_ast2700_realize" f
Added a new method "start_ast2700_test" to the "AST2x00MachineSDK" class and
this method centralizes the logic for starting the AST2700 test, making it
reusable for different test cases.
Signed-off-by: Jamin Lin
Reviewed-by: Cédric Le Goater
---
tests/functional/test_aarch64_aspeed.py | 29
Currently, AST2700 SoC only supports A0. To support AST2700 A1, rename its IRQ
table and machine name.
To follow the machine deprecation rule, the initial machine "ast2700-evb" is
aliased to "ast2700a0-evb." In the future, we will alias "ast2700-evb" to new
SoCs, such as "ast2700a1-evb."
Signed-o
To improve readability, sort the IRQ table by IRQ number.
Signed-off-by: Jamin Lin
Reviewed-by: Cédric Le Goater
---
hw/arm/aspeed_ast27x0.c | 50 -
1 file changed, 25 insertions(+), 25 deletions(-)
diff --git a/hw/arm/aspeed_ast27x0.c b/hw/arm/aspeed_as
The behavior of the enable and status registers is almost identical between
INTC(CPU Die) and INTCIO(IO Die). To reduce duplicated code, adds
"aspeed_intc_enable_handler" functions to handle enable register write
behavior and "aspeed_intc_status_handler" functions to handle status
register write be
Modified the temperature hwmon path to use a wildcard to handle different SDK
versions: "cat /sys/bus/i2c/devices/1-004d/hwmon/hwmon*/temp1_input".
Signed-off-by: Jamin Lin
Reviewed-by: Cédric Le Goater
---
tests/functional/test_aarch64_aspeed.py | 4 ++--
1 file changed, 2 insertions(+), 2 del
Currently, the size of the regs array is 0x2000, which is too large. So far,
it only use GICINT128 - GICINT134, and the offsets from 0 to 0x1000 are unused.
To save code size, introduce a new class attribute "reg_size" to set the
different register sizes for the INTC models in AST2700 and add a reg
Refactors the INTC to distinguish between input and output pin indices,
improving interrupt handling clarity and accuracy.
Updated the functions to handle both input and output pin indices.
Added detailed logging for input and output pin indices in trace events.
These changes ensure that the INTC
Separate HW Strap Registers for SCU and SCUIO.
AST2700_EVB_HW_STRAP1 is used for the SCU (CPU Die) hw-strap1.
AST2700_EVB_HW_STRAP2 is used for the SCUIO (IO Die) hw-strap1.
Additionally, both default values are updated based on the dump from the EVB.
Signed-off-by: Jamin Lin
Reviewed-by: Cédric
There is one hw_strap1 register in the SCU (CPU DIE) and another hw_strap1
register in the SCUIO (IO DIE).
In the "ast2700_a0_resets" function, the hardcoded value "0x0800" is set in
SCU hw-strap1 (CPU DIE), and in "ast2700_a0_resets_io" the hardcoded value
"0x0504" is set in SCUIO hw-stra
There is one hw-strap1 register in the SCU (CPU DIE) and another hw-strap1
register in the SCUIO (IO DIE). The values of these two registers should not be
the same. To reuse the current design of hw-strap, hw-strap1 is assigned to the
SCU and sets the value in the SCU hw-strap1 register, while hw-s
Setting BIT6 in VGA0 SCRATCH register will indicate that the ddr traning
is done, therefore skipping the u-boot-spl dram_init() process.
Signed-off-by: Jamin Lin
Signed-off-by: Troy Lee
Reviewed-by: Cédric Le Goater
---
hw/misc/aspeed_scu.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a
v1: This patch series is from
https://patchwork.kernel.org/project/qemu-devel/cover/20250213033531.3367697-1-jamin_...@aspeedtech.com/.
To expedite the review process, I have separated the SCU fix patches
a. Fix the hw-strap and revision ID for SCU and SCUIO
b. ix boot issue for AST2700
v2:
a
Currently, ASPEED_DEV_SPI_BOOT is set to "0x4", which is the DRAM start
address, and the QEMU loader is used to load the U-Boot binary into this
address.
However, if users want to install FMC flash contents as a boot ROM, the DRAM
address 0x4 would be overwritten with Boot ROM dat
According to the design of the AST2600, it has a Silicon Revision ID Register,
specifically SCU004 and SCU014, to set the Revision ID for the AST2600.
For the AST2600 A3, SCU004 is set to 0x05030303 and SCU014 is set to 0x05030303.
In the "aspeed_ast2600_scu_reset" function, the hardcoded value
"AS
Currently, these trace events only refer to INTC. To simplify the INTC model,
both INTC(CPU Die) and INTCIO(IO Die) will share the same helper functions.
However, it is difficult to recognize whether these trace events are comes from
INTC or INTCIO. To make these trace events more readable, adds o
Currently, the size of the "regs" array is 0x2000, which is too large. So far,
it only uses "GICINT128 to `GICINT134", and the offsets from 0 to 0x1000 are
unused. To save code size and avoid mapping large unused gaps, update to only
map the useful set of registers:
INTC register [0x1000 – 0x1804]
Currently, the size of the regs array is 0x2000, which is too large. So far,
it only use GICINT128 - GICINT134, and the offsets from 0 to 0x1000 are unused.
To save code size, introduce a new class attribute "reg_size" to set the
different register sizes for the INTC models in AST2700 and add a reg
Added a new method "start_ast2700_test" to the "AST2x00MachineSDK" class and
this method centralizes the logic for starting the AST2700 test, making it
reusable for different test cases.
Signed-off-by: Jamin Lin
---
tests/functional/test_aarch64_aspeed.py | 29 +
1 file c
Added support for multiple output pins in the INTC controller to
accommodate the AST2700 A1.
Introduced "num_outpins" to represent the number of output pins. Updated the
IRQ handling logic to initialize and connect output pins separately from input
pins. Modified the "aspeed_soc_ast2700_realize" f
Add AST2700 INTC design guidance and its block diagram.
Signed-off-by: Jamin Lin
Reviewed-by: Cédric Le Goater
---
docs/specs/aspeed-intc.rst | 136 +
docs/specs/index.rst | 1 +
2 files changed, 137 insertions(+)
create mode 100644 docs/specs/aspeed
The design of INTC controllers has significantly changed in AST2700 A1.
There are a total of 480 interrupt sources in AST2700 A1. For interrupt numbers
from 0 to 127, they can route directly to PSP, SSP, and TSP. Due to the
limitation of interrupt numbers of processors, the interrupts are merged e
Currently, AST2700 SoC only supports A0. To support AST2700 A1, rename its IRQ
table and machine name.
To follow the machine deprecation rule, the initial machine "ast2700-evb" is
aliased to "ast2700a0-evb." In the future, we will alias "ast2700-evb" to new
SoCs, such as "ast2700a1-evb."
Signed-o
Signed-off-by: Jamin Lin
Reviewed-by: Cédric Le Goater
---
tests/functional/test_aarch64_aspeed.py | 10 ++
1 file changed, 10 insertions(+)
diff --git a/tests/functional/test_aarch64_aspeed.py
b/tests/functional/test_aarch64_aspeed.py
index 8df6a97a28..c25c966278 100755
--- a/tests/fu
The behavior of the INTC set IRQ is almost identical between INTC and INTCIO.
To reduce duplicated code, introduce the "aspeed_intc_set_irq_handler" function
to handle both INTC and INTCIO IRQ behavior. No functional change.
Signed-off-by: Jamin Lin
Reviewed-by: Cédric Le Goater
---
hw/intc/asp
Rename the variables "status_addr" to "status_reg" and "addr" to "reg" because
they are used as register index. This change makes the code more appropriate
and improves readability.
Signed-off-by: Jamin Lin
---
hw/intc/aspeed_intc.c | 38 +++---
1 file changed, 19
Currently, these IRQ tables support from GIC 128 - 136 for AST2700 A0.
These IRQ tables can be reused for AST2700 A1 from GIC 192 - 197.
Updates the interrupt mapping to include support for AST2700 A1 by extending
the existing mappings to the new GIC range.
Signed-off-by: Jamin Lin
Reviewed-by: C
To improve readability, sort the IRQ table by IRQ number.
Signed-off-by: Jamin Lin
Reviewed-by: Cédric Le Goater
---
hw/arm/aspeed_ast27x0.c | 50 -
1 file changed, 25 insertions(+), 25 deletions(-)
diff --git a/hw/arm/aspeed_ast27x0.c b/hw/arm/aspeed_as
This update introduces support for handling multi-output IRQs in the AST2700
interrupt controller (INTC), specifically for GICINT192_201. GICINT192_201 maps
1:10 to input IRQ 0 and output IRQs 0 to 9. Each status bit corresponds to a
specific IRQ.
Implemented "aspeed_intc_set_irq_handler_multi_out
Currently, the size of the "regs" array is 0x2000, which is too large. To save
code size and avoid mapping large unused gaps, will update it to only map the
useful set of registers. This update will support multiple sub-regions with
different sizes.
To address the redundant size issue, replace the
The behavior of the enable and status registers is almost identical between
INTC(CPU Die) and INTCIO(IO Die). To reduce duplicated code, adds
"aspeed_intc_enable_handler" functions to handle enable register write
behavior and "aspeed_intc_status_handler" functions to handle status
register write be
Modified the temperature hwmon path to use a wildcard to handle different SDK
versions: "cat /sys/bus/i2c/devices/1-004d/hwmon/hwmon*/temp1_input".
Signed-off-by: Jamin Lin
---
tests/functional/test_aarch64_aspeed.py | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/tests/f
To improve readability, sort the memmap table by mapping address
Signed-off-by: Jamin Lin
---
hw/arm/aspeed_ast27x0.c | 54 -
1 file changed, 27 insertions(+), 27 deletions(-)
diff --git a/hw/arm/aspeed_ast27x0.c b/hw/arm/aspeed_ast27x0.c
index 7439512b83
In ASPEED SDK v09.05, the naming convention for pre-built images has been
updated. The pre-built image for AST2700 A0 has been renamed to
ast2700-a0-default, while ast2700-default is now used for AST2700 A1.
Signed-off-by: Jamin Lin
Reviewed-by: Cédric Le Goater
---
tests/functional/test_aarch6
The previous implementation set the "aspeed_intc_ops" struct, containing read
and write callbacks, to be used when I/O is performed on the INTC region.
Both "aspeed_intc_read" and "aspeed_intc_write" callback functions were used
for INTC (CPU Die).
To support the INTCIO (IO Die) model, introduces
According to the AST2700 datasheet, the INTC(CPU DIE) controller has 16KB
(0x4000) of register space, and the INTCIO (I/O DIE) controller has 1KB (0x400)
of register space.
Introduced a new class attribute "mem_size" to set different memory sizes for
the INTC models in AST2700.
Signed-off-by: Jam
Introduce "aspeed_machine_ast2700a1_evb_class_init" to initialize the
AST2700 A1 EVB.
Signed-off-by: Jamin Lin
---
hw/arm/aspeed.c | 24
1 file changed, 24 insertions(+)
diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c
index 18f7c450da..82f42582fa 100644
--- a/hw/arm/aspe
The memory map for AST2700 A1 remains compatible with AST2700 A0. However, the
IRQ mapping has been updated for AST2700 A1, with GIC interrupts now ranging
from 192 to 201. Add a new IRQ map table for AST2700 A1.
Add "aspeed_soc_ast2700a1_class_init" to initialize the AST2700 A1 SoC.
Signed-off-by
Updated Aspeed27x0SoCState to include an intc[2] array instead of a single
AspeedINTCState instance. Modified aspeed_soc_ast2700_get_irq and
aspeed_soc_ast2700_get_irq_index to correctly reference the corresponding
interrupt controller instance and OR gate index.
Currently, only GIC 192 to 201 are
Introduce a new ast2700 INTCIO class to support AST2700 INTCIO.
Added new register definitions for INTCIO, including enable and status
registers for IRQs GICINT192 through GICINT197.
Created a dedicated IRQ array for INTCIO, supporting six input pins and six
output pins, aligning with the newly def
The memory map for AST2700 A1 remains compatible with AST2700 A0. However, the
IRQ mapping has been updated for AST2700 A1, with GIC interrupts now ranging
from 192 to 201. Add a new IRQ map table for AST2700 A1.
Add "aspeed_soc_ast2700a1_class_init" to initialize the AST2700 A1 SoC.
Signed-off-by
To support AST2700 A1, some registers of the INTC(CPU Die) support one input
pin to multiple output pins. Renamed "num_ints" to "num_inpins" in the INTC
controller code for better clarity and consistency in naming conventions.
Signed-off-by: Jamin Lin
Reviewed-by: Cédric Le Goater
---
include/h
To support AST2700 A1, some registers of the INTC(CPU Die) support one input
pin to multiple output pins. Renamed "num_ints" to "num_inpins" in the INTC
controller code for better clarity and consistency in naming conventions.
Signed-off-by: Jamin Lin
Reviewed-by: Cédric Le Goater
---
include/h
Introduce a new ast2700 class to support AST2700.
Signed-off-by: Jamin Lin
Reviewed-by: Andrew Jeffery
---
include/hw/misc/aspeed_hace.h | 1 +
hw/misc/aspeed_hace.c | 20
2 files changed, 21 insertions(+)
diff --git a/include/hw/misc/aspeed_hace.h b/include/hw/mi
Fix coding style issues from checkpatch.pl.
Signed-off-by: Jamin Lin
Reviewed-by: Cédric Le Goater
---
hw/misc/aspeed_hace.c | 12
1 file changed, 8 insertions(+), 4 deletions(-)
diff --git a/hw/misc/aspeed_hace.c b/hw/misc/aspeed_hace.c
index e3f7df2e86..18b85081c7 100644
--- a/h
This patch series is from
https://patchwork.kernel.org/project/qemu-devel/cover/20250213033531.3367697-1-jamin_...@aspeedtech.com/.
To expedite the review process, I have separated the HACE patches portion from
the
https://patchwork.kernel.org/project/qemu-devel/cover/20250213033531.3367697-1-j
The HACE controller between AST2600 and AST2700 are almost identical.
The HACE controller registers base address starts at 0x1207_ and
its alarm interrupt is connected to GICINT4.
Signed-off-by: Jamin Lin
Reviewed-by: Andrew Jeffery
---
hw/arm/aspeed_ast27x0.c | 15 +++
1 file c
Currently, it does not support the CRYPT command. Instead, it only sends an
interrupt to notify the firmware that the crypt command has completed.
It is a temporary workaround to resolve the boot issue in the Crypto Manager
Self Test.
Introduce a new "use_crypt_workaround" class attribute and set
Enable accumulative mode for direct access mode operations. In direct access
mode, only a single source buffer is used, so the "iovec" count is set to 1.
If "acc_mode" is enabled:
1. Accumulate "total_req_len" with the current request length ("plen").
2. Check for padding and determine whether this
In the previous design, the I2C model would update I2CC_DMA_LEN (0x54) based on
the value of I2CM_DMA_LEN (0x1C) when the firmware set either I2CM_DMA_TX_ADDR
(0x30) or I2CM_DMA_RX_ADDR (0x34). However, this only worked correctly if the
firmware set I2CM_DMA_LEN before setting I2CM_DMA_TX_ADDR or I
The AST2700 CPU, based on the Cortex-A35, is a 64-bit processor with a 64-bit
DRAM address space. To support future AST2700 updates, a new "digest_addr"
variable is introduced with a 64-bit data type.
Signed-off-by: Jamin Lin
---
hw/misc/aspeed_hace.c | 4 +++-
1 file changed, 3 insertions(+), 1
Currently, if the program encounters an unsupported algorithm, it does not set
the HASH_IRQ bit in the status register and send an interrupt to indicate
command completion. As a result, the FW gets stuck waiting for a completion
signal from the HACE module.
Additionally, in do_hash_operation, if a
Added "HACE_HASH_SRC_HI" and "HACE_HASH_DIGEST_HI", "HACE_HASH_KEY_BUFF_HI"
registers to store upper 32 bits.
Updated "write_regs" to handle 64-bit source and digest addresses.
Signed-off-by: Jamin Lin
---
tests/qtest/aspeed-hace-utils.h | 3 +++
tests/qtest/aspeed-hace-utils.c | 2 ++
2 files c
Link:
https://patchwork.kernel.org/project/qemu-devel/patch/20250509175047.26066-1-faro...@suse.de/
Signed-off-by: Jamin Lin
---
tests/qtest/aspeed_smc-test.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/tests/qtest/aspeed_smc-test.c b/tests/qtest/aspeed_smc-test.c
index 4e1389385d.
v1:
1. Added support for 64-bit DMA in the HACE model
2. Refactored the do_hash operation in the HACE model
3. Fixed a crash caused by out-of-bound memory access in HACE
4. Added more trace events and implemented dumping of source hash data and
resulting digests to improve debugging
5. Ref
Currently, users define multiple local variables within different if-statements.
To improve readability and maintain consistency in variable naming, rename the
variables accordingly.
Introduced "sg_addr" to clearly indicate the scatter-gather mode buffer address.
Signed-off-by: Jamin Lin
---
hw/
To improve code readability and maintainability, this commit refactors the hash
buffer preparation logic from "do_hash_operation()" into two helper functions:
- "hash_prepare_direct_iov()": handles non-scatter-gather (direct) mode.
- "hash_prepare_sg_iov()": handles scatter-gather mode with accumu
Renaming R_HASH_DEST to R_HASH_DIGEST for better semantic clarity.
The AST2700 CPU, based on the Cortex-A35, features a 64-bit DRAM address space.
To prepare for future AST2700 support, this change introduces a new helper
function hash_get_digest_addr() to encapsulate digest address extraction log
The AST2700 CPU, based on the Cortex-A35, is a 64-bit processor, and its DRAM
address space is also 64-bit. To support future AST2700 updates, the source
hash buffer address data type is being updated to 64-bit.
Introduces the "hash_get_source_addr()" helper function to extract the source
hash
bu
Enable accumulative mode for direct access mode operations. In direct access
mode, only a single source buffer is used, so the "iovec" count is set to 1.
If "acc_mode" is enabled:
1. Accumulate "total_req_len" with the current request length ("plen").
2. Check for padding and determine whether this
Dynamically allocate the register array by removing the hardcoded
ASPEED_HACE_NR_REGS macro.
To support different register sizes across SoC variants, introduce a new
"nr_regs" class attribute and replace the static "regs" array with dynamically
allocated memory.
Add a new "aspeed_hace_unrealize"
1. Added "hace_hexdump()" to dump a contiguous buffer using qemu_hexdump.
2. Added "hace_iov_hexdump()" to flatten and dump scatter-gather source vectors.
3. Introduced a new trace event: "aspeed_hace_hexdump".
Signed-off-by: Jamin Lin
---
hw/misc/aspeed_hace.c | 46 +
Refactor "do_hash_operation()" by extracting hash execution and result handling
into dedicated helper functions:
- "hash_write_digest_and_unmap_iov()": Writes the digest result to memory and
unmaps IOVs after processing.
- "hash_execute_non_acc_mode()": Handles one-shot (non-accumulated) hash
501 - 600 of 685 matches
Mail list logo
