t x86 does a sync in its kvm_arch_stop_on_emulation_error()
function so at least for emulation errors is unaffected.
Signed-off-by: James Hogan
Cc: Gleb Natapov
Cc: Paolo Bonzini
Cc: k...@vger.kernel.org
---
kvm-all.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/kvm-all.c b/kvm-all.c
On 23/08/13 13:58, Gleb Natapov wrote:
> On Fri, Aug 23, 2013 at 01:26:00PM +0100, James Hogan wrote:
>> When a KVM internal error occurs QEMU dumps the CPU state, however it
>> doesn't synchronise the state from KVM first so the dumped state is out
>> of date. Add the sy
Hi Andreas,
On 23/08/13 12:08, Andreas Färber wrote:
> Am 23.08.2013 09:59, schrieb Leon Alrae:
>> From: James Hogan
>>
>> Commit a427338 (mips_malta: correct reading MIPS revision at 0x1fc00010)
>> altered the behaviour of the monitor flash mapping at the reset addres
MIPS) can take advantage of it.
This requires kvm_cpu_synchronize_state() and cpu_synchronize_state() to
be moved out of the #ifdef NEED_CPU_H in so that they're
accessible to qom/cpu.c.
Signed-off-by: James Hogan
Cc: Andreas Färber
Cc: Alexander Graf
Cc: Gleb Natapov
Cc: qemu-...@nongn
g/patch/2207251/
Signed-off-by: James Hogan
Cc: Andreas Färber
Cc: Sanjay Lal
Cc: qemu-sta...@nongnu.org
---
configure | 7 ++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/configure b/configure
index 0a55c20..a765a9f 100755
--- a/configure
+++ b/configure
@@ -1415,7 +1415,1
On 1 July 2013 04:30, Mike Frysinger wrote:
> This avoids needing to execute a program and keeping an (incomplete)
> list when cross-compiling.
>
> Signed-off-by: Mike Frysinger
This fixes mipsel cross compiling. I also checked it detected a mips
(be) compiler as big endian.
Test
On 27/08/13 19:39, Richard Henderson wrote:
> On 08/27/2013 09:02 AM, James Hogan wrote:
>> The configure script was setting HOST_WORDS_BIGENDIAN for all $cpu =
>> mips|mips64 when cross compiling, since endianness cannot be detected by
>> running a test program. This includ
On 27/08/13 20:48, Richard Henderson wrote:
> On 08/27/2013 09:48 AM, Yongbok Kim wrote:
>> #if 0
>> -qemu_log(TARGET_FMT_lx " %d %d => " TARGET_FMT_lx " %d (%d)\n",
>> +qemu_log(TARGET_FMT_lx " %d %d => %" HWADDR_PRIx " %d (%d)\n",
>> address, rw, access_type, *physical, *pro
|RD_s|RD_t, 0,
> I32R6},
I don't think these need to be at the beginning of the table since
they're normal instructions, unlike "nop" for example which is encoded
as a "sll".
Otherwise
Reviewed-by: James Hogan
Cheers
James
Hi Leon,
On 27/06/14 16:21, Leon Alrae wrote:
> diff --git a/target-mips/translate.c b/target-mips/translate.c
> index 931a580..bb95f7b 100644
> --- a/target-mips/translate.c
> +++ b/target-mips/translate.c
> @@ -189,6 +189,9 @@ enum {
> OPC_MOVZ = 0x0A | OPC_SPECIAL,
> OPC_MOVN
case OPC_DDIV_G_2E ... OPC_DDIVU_G_2E:
> case OPC_DMULT_G_2E ... OPC_DMULTU_G_2E:
> -case OPC_DMOD_G_2E ... OPC_DMODU_G_2E:
> +case OPC_DMODU_G_2E:
> +check_insn_opc_removed(ctx, ISA_MIPS32R6);
AFAICT you remove this check_insn_opc_removed line again in patch 6, so
I don't think you need to add it here.
Otherwise
Reviewed-by: James Hogan
Cheers
James
On 26/09/14 13:45, Leon Alrae wrote:
> Hi James,
>
> On 26/09/2014 13:03, James Hogan wrote:
>> Hi Leon,
>>
>> On 27/06/14 16:21, Leon Alrae wrote:
>>> /* MIPS64 MIPS-3D ASE support. */
>>> #define I16 INSN_MIPS16
>>> @@ -1209,6 +1
From: Sanjay Lal
Implement the main KVM arch API for MIPS.
Signed-off-by: Sanjay Lal
Signed-off-by: James Hogan
Cc: Aurelien Jarno
Cc: Gleb Natapov
Cc: Paolo Bonzini
Cc: Andreas Färber
Cc: Peter Maydell
---
Changes in v5:
- Rename kvm_arch_reset_vcpu to kvm_mips_reset_vcpu based on
er as stopped so that CP0_Count is modified directly.
Signed-off-by: Sanjay Lal
[james.ho...@imgtec.com: Update after "target-mips: Reset CPU timer
consistently" which moves timer start to reset time]
Signed-off-by: James Hogan
Cc: Aurelien Jarno
Cc: Paolo Bonzini
---
Changes in v5:
mode both the guest kernel and guest userspace
execute in useg:
Guest User address space: 0x..0x3fff
Guest Kernel Unmapped: 0x4000..0x5fff
Guest Kernel Mapped:0x6000..0x7fff
Signed-off-by: Sanjay Lal
Signed-off-by: James Hogan
Cc: Aurelien
When KVM is enabled call kvm_mips_reset_vcpu() from mips_cpu_reset() as
done for other targets since commit 50a2c6e55fa2 (kvm: reset state from
the CPU's reset method).
Signed-off-by: James Hogan
Cc: Aurelien Jarno
Cc: Paolo Bonzini
Cc: Gleb Natapov
---
Changes in v5:
- New patch, bas
U interrupts and
the CPU timer, so env->timer will be NULL. This case is handled
explicitly in cpu_mips_store_count(), treating the timer as disabled
(which will also be the right thing to do when KVM support is added).
Reported-by: Paolo Bonzini
Signed-off-by: James Hogan
Cc: Aurelien Jarno
From: Sanjay Lal
Enable KVM support for MIPS in the build system.
Signed-off-by: Sanjay Lal
Signed-off-by: James Hogan
Reviewed-by: Aurelien Jarno
---
Changes in v2:
- Expand commit message
- Remove GIC code
- Create asm-mips symlink using generic code and move above default
case
dard kseg0 or kseg2
address before doing the normal address translation. The real virtual
address is still used for TLB lookups.
Signed-off-by: James Hogan
Cc: Aurelien Jarno
---
target-mips/helper.c | 33 ++---
1 file changed, 26 insertions(+), 7 deletions(-)
diff -
rom kvm_arch_init(). Otherwise default to 8
bytes.
Signed-off-by: James Hogan
Cc: Aurelien Jarno
Cc: Sanjay Lal
Cc: Gleb Natapov
Cc: Paolo Bonzini
Cc: Peter Maydell
---
Changes in v3:
- Rewrote to allow sigmask length to be set by kvm_arch_init(), so that
MIPS can set it to 16 as it has
In KVM mode the bootrom is loaded and executed from the last 1MB of
DRAM.
Based on "[PATCH 12/12] KVM/MIPS: General KVM support and support for
SMP Guests" by Sanjay Lal .
Signed-off-by: James Hogan
Reviewed-by: Aurelien Jarno
Cc: Peter Maydell
Cc: Sanjay Lal
---
Changes in v5
From: Sanjay Lal
COP0 emulation is in-kernel for KVM, so inject IRQ2 (I/O) interrupts via
ioctls.
Signed-off-by: Sanjay Lal
Signed-off-by: James Hogan
Reviewed-by: Aurelien Jarno
Reviewed-by: Andreas Färber
---
Changes in v5:
- Fix typo in subject (s/interupts/interrupts/)
Changes in v3
Add preprocessor definitions for 32bit segment bases for use in
get_physical_address(). These will also be taken advantage of in the
next patch which adds KVM awareness.
Signed-off-by: James Hogan
Reviewed-by: Aurelien Jarno
---
target-mips/helper.c | 18 --
1 file changed, 12
Add MAINTAINERS entry for MIPS KVM.
Signed-off-by: James Hogan
---
Changes in v4:
- Add MAINTAINERS entry for MIPS KVM.
---
MAINTAINERS | 5 +
1 file changed, 5 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index 51a6f51842be..0a637c90c679 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
Peter Maydell)
- Remove redundant check of target_name = cpu = mips
- Remove mipsel cross compilation fix, which is now fixed by commit
61cc919f73ea (configure: detect endian via compile test)
- Add translation of guest kernel segments to allow an attached gdb to
see kernel memory correctly
Jame
From: Sanjay Lal
Add VMStateDescription for GT64120 PCI emulation used by the Malta
platform, to allow it to work with savevm/loadvm and live migration.
Signed-off-by: Sanjay Lal
[james.ho...@imgtec.com: Convert to VMState]
Signed-off-by: James Hogan
Cc: Aurelien Jarno
---
This is based on
On 19/06/14 16:25, Aurelien Jarno wrote:
> On Wed, Jun 18, 2014 at 12:10:02AM +0100, James Hogan wrote:
>> From: Sanjay Lal
>>
>> Add VMStateDescription for GT64120 PCI emulation used by the Malta
>> platform, to allow it to work with savevm/loadvm and live migration.
Hi,
On 20/06/14 07:07, Paolo Bonzini wrote:
> - Messaggio originale -
>> Da: "Aurelien Jarno"
>> A: "Sanjay Lal"
>> Cc: "James Hogan" , qemu-devel@nongnu.org, "Peter
>> Maydell" ,
>> k...@vger.kernel.org, "
On 19/06/14 22:47, Aurelien Jarno wrote:
> On Thu, Jun 19, 2014 at 12:34:24PM -0700, Sanjay Lal wrote:
>>
>> On Jun 19, 2014, at 9:27 AM, Aurelien Jarno wrote:
>>
>>> On Tue, Jun 17, 2014 at 11:10:35PM +0100, James Hogan wrote:
>>>> In KVM mode the bootro
...@imgtec.com: Convert to VMState]
Signed-off-by: James Hogan
Cc: Aurelien Jarno
---
This is based on "[Patch 03/12] KVM/MIPS: Add save/restore state APIs
for saving/restoring KVM guests."[1].
Changes in v3:
- Save entire register array using VMSTATE_UINT32_ARRAY (which is fixed
On 20/06/14 11:25, James Hogan wrote:
> From: Sanjay Lal
>
> Add VMStateDescription for GT64120 PCI emulation used by the Malta
> platform, to allow it to work with savevm/loadvm and live migration.
>
> The entire register array is saved/restored using VMSTATE_UINT32_ARR
On 20/06/14 12:19, Aurelien Jarno wrote:
> On Fri, Jun 20, 2014 at 12:38:30PM +0200, Paolo Bonzini wrote:
>> Il 20/06/2014 11:10, Aurelien Jarno ha scritto:
My idea was to add a machines-specific option umkernel=on, and require it
in order to run KVM. Later we can add umkernel=on support
since booting from flash will fail.
Reported-by: Aurelien Jarno
Signed-off-by: James Hogan
Cc: Paolo Bonzini
---
hw/mips/mips_malta.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/hw/mips/mips_malta.c b/hw/mips/mips_malta.c
index 8bc5392b4223..91b0ce566111 100644
--- a/hw/mips/mips_
On 20/06/14 14:17, Andreas Färber wrote:
> Hi,
>
> Am 20.06.2014 13:47, schrieb James Hogan:
>> In KVM trap & emulate (T&E) mode the flash reset region at 0xbfc0
>> isn't executable, which is why the minimal kernel bootloader is loaded
>> and ex
fail.
Reported-by: Aurelien Jarno
Signed-off-by: James Hogan
Reviewed-by: Andreas Färber
Cc: Paolo Bonzini
---
Changes in v2:
- Remove mention of T&E. There is currently no distinction since VZ
isn't supported, and technically the limitation isn't T&E specific.
(Andre
...@imgtec.com: Convert to VMState]
Signed-off-by: James Hogan
Cc: Aurelien Jarno
Cc: Andreas Färber
---
This is based on "[Patch 03/12] KVM/MIPS: Add save/restore state APIs
for saving/restoring KVM guests."[1].
Changes in v4:
- Drop redundant "hw/mips:" prefix from subject l
0x00687c9c in pty_chr_write (chr=0xf37788, buf=0x70b3c008 , len=538720)
at qemu/qemu-char.c:1063
#107496 0x00684cc4 in qemu_chr_fe_write (s=0xf37788, buf=0x70b3c008 , len=538720)
at qemu/qemu-char.c:118
...
Signed-off-by: James Hogan
Cc: Michael Roth
Cc: Anthony Liguori
---
Note th
definition for rotl_i32
Invalid op definition for rotr_i32
Invalid op definition for deposit_i32
Invalid op definition for bswap16_i32
Invalid op definition for bswap32_i32
tcg/tcg.c:1196: tcg fatal error
Fix with ifdefs like the i386 backend does for movcond_i32.
Signed-off-by: James Hogan
Cc
On 08/08/13 17:10, Richard Henderson wrote:
> On 08/08/2013 04:40 AM, James Hogan wrote:
>> tcg/mips/tcg-target.h defines various operations conditionally depending
>> upon the isa revision, however these operations are included in
>> mips_op_defs[] unconditionally resul
On 12 August 2013 20:44, Aurelien Jarno wrote:
> Since commit c658b94f6e8c206c59d02aa6fbac285b86b53d2c, MIPS raises
> exceptions when accessing invalid memory. This is not the correct
> behaviour for MIPS Malta Core LV, as the GT-64120A system controller
> just ignore undecoded access. This featur
update cycle (244uS).
It's clear from periodic_timer_update() that only a 32.768KHz clock
source is expected, so correct the hold time to 244uS + 1984uS = 73
32.768KHz clock cycles.
Signed-off-by: James Hogan
Cc: Andreas Färber
Cc: Anthony Liguori
Cc: Igor Mammedov
Cc: Paolo Bonzini
Cc: Yang
Hi Petar,
On Friday 16 May 2014 20:13:34 Petar Jovanovic wrote:
> From: Petar Jovanovic
>
> From MIPS documentation (Volume III):
>
> UserLocal Register (CP0 Register 4, Select 2)
> Compliance Level: Recommended.
>
> The UserLocal register is a read-write register that is not interpreted by
>
On Friday 16 May 2014 20:13:34 Petar Jovanovic wrote:
> diff --git a/target-mips/cpu.h b/target-mips/cpu.h
> index 6c2014e..bb18fb8 100644
> --- a/target-mips/cpu.h
> +++ b/target-mips/cpu.h
> @@ -227,6 +227,7 @@ struct CPUMIPSState {
> target_ulong CP0_EntryLo0;
> target_ulong CP0_EntryL
Hi,
On 14/07/14 10:55, Yongbok Kim wrote:
> +union wr_t {
> +int8_t b[MSA_WRLEN/8];
> +int16_t h[MSA_WRLEN/16];
> +int32_t w[MSA_WRLEN/32];
> +int64_t d[MSA_WRLEN/64];
This is incorrect on a big endian host. The least significant bits of
the lowest indexed element should always a
0x18 << 16) | OPC_MSA_2RF,
> +OPC_MSA_FINT_U_df = (0x1A << 16) | OPC_MSA_2RF,
the manual calls these two FTINT rather than FINT
Otherwise
Reviewed-by: James Hogan
Cheers
James
Hi,
On 14/07/14 10:55, Yongbok Kim wrote:
> +typedef struct CPUMIPSMSAContext CPUMIPSMSAContext;
> +struct CPUMIPSMSAContext {
> +int32_t msair;
> +int32_t msacsr;
> +int32_t msaaccess;
> +int32_t msasave;
> +int32_t msamodify;
> +int32_t msarequest;
> +int32_t msama
Hi,
On 14/07/14 10:55, Yongbok Kim wrote:
> +static const char * const msaregnames[] = {
> +"w0.d0", "w0.d1", "w1.d0", "w1.d1",
> +"w2.d0", "w2.d1", "w3.d0", "w3.d1",
> +"w4.d0", "w4.d1", "w4.d0", "w4.d1",
I think those last 2 should be w5.d0 and w5.d1
> +static inline int c
On 14/07/14 10:55, Yongbok Kim wrote:
> +#define B(pwr, i) (((wr_t *)pwr)->b[i])
> +#define BR(pwr, i) (((wr_t *)pwr)->b[i])
> +#define BL(pwr, i) (((wr_t *)pwr)->b[i + MSA_WRLEN/16])
macro argument references should be enclosed in brackets really (to
avoid precedence problems).
> +
> +#define A
Hi Yongbok,
I know you're preparing another patchset, but thought I may as well
continue reviewing this patchset until that one lands, sorry it's taken
me a while to get round to it.
On Mon, Jul 14, 2014 at 10:55:52AM +0100, Yongbok Kim wrote:
> +static void determ_zero_element(TCGv tresult, uint
_t ws,
> +uint32_t i8)
> +{
> +void *pwd = &(env->active_fpu.fpr[wd]);
> +void *pws = &(env->active_fpu.fpr[ws]);
> +ALL_B_ELEMENTS(i, MSA_WRLEN) {
> +BIT_SELECT(B(pwd, i), B(pws, i), i8, DF_BYTE);
> +} DONE_ALL_ELEMENTS;
> +if (env->active_msa.msair & MSAIR_WRP_BIT) {
> +env->active_msa.msamodify |= (1 << wd);
> +}
> +}
I reckon the functions above could all be done easily enough in TCG by
repeating i8 up to 64-bits (at translation time) and doing the
operations on 64-bit quantities. Out of interest, was there a particular
motivation to do it with helpers?
In any case, that can always be an experiment for a later patch, and it
all looks technically correct.
Reviewed-by: James Hogan
Cheers
James
_Flags)
MSACSR_Flags is inconsistently named. Maybe MSACSR_CEF?
Otherwise:
Reviewed-by: James Hogan
Cheers
James
On Wed, Oct 29, 2014 at 01:41:50AM +, Yongbok Kim wrote:
> add MSA exceptions
>
> Signed-off-by: Yongbok Kim
Reviewed-by: James Hogan
Cheers
James
> ---
> target-mips/helper.c | 10 ++
> 1 files changed, 10 insertions(+), 0 deletions(-)
>
> diff --git
as well as op_helper.c.
Otherwise,
Reviewed-by: James Hogan
Cheers
James
> ---
> target-mips/cpu.h |4
> target-mips/gdbstub.c |7 ---
> target-mips/op_helper.c |4 ++--
> 3 files changed, 6 insertions(+), 9 deletions(-)
>
> diff --git a/targe
On Wed, Oct 29, 2014 at 01:41:52AM +, Yongbok Kim wrote:
>
> Signed-off-by: Yongbok Kim
You seem to have lost the commit message compared to v1.
Patch looks fine to me, but IMO it's worth squashing this into patch 18,
since that's the only place they're used.
Cheers
James
> ---
> target-
On Wed, Oct 29, 2014 at 01:41:53AM +, Yongbok Kim wrote:
> stop translation as ctc1 instruction can change hflags
>
> Signed-off-by: Yongbok Kim
Reviewed-by: James Hogan
Cheers
James
> ---
> target-mips/translate.c |6 ++
> 1 files changed, 6 insertio
On Wed, Oct 29, 2014 at 01:41:55AM +, Yongbok Kim wrote:
> add msa_reset() and global msa register (d type only)
>
> Signed-off-by: Yongbok Kim
Reviewed-by: James Hogan
Cheers
James
> ---
> target-mips/translate.c | 56
> +++
On Wed, Oct 29, 2014 at 01:41:56AM +, Yongbok Kim wrote:
> add msa_helper.c
>
> Signed-off-by: Yongbok Kim
Reviewed-by: James Hogan
Cheers
James
> ---
> target-mips/Makefile.objs |2 +-
> target-mips/msa_helper.c | 49
> +++
On Wed, Oct 29, 2014 at 01:41:57AM +, Yongbok Kim wrote:
> add MSA branch instructions
>
> Signed-off-by: Yongbok Kim
Reviewed-by: James Hogan
Cheers
James
> ---
> target-mips/translate.c | 333
> +++
> 1 files ch
On Wed, Oct 29, 2014 at 01:41:58AM +, Yongbok Kim wrote:
> add MSA I8 format instructions
>
> Reviewed-by: James Hogan
The patch has changed quite a lot, so probably worth dropping
Reviewed-by in those cases in future.
> Signed-off-by: Yongbok Kim
> +#define MSA_FN_
Hi Yongbok,
On Wed, Oct 29, 2014 at 01:41:59AM +, Yongbok Kim wrote:
> +DEF_HELPER_5(msa_addvi_df, void, env, i32, i32, i32, s64)
> +DEF_HELPER_5(msa_ceqi_df, void, env, i32, i32, i32, s64)
> +DEF_HELPER_5(msa_clei_s_df, void, env, i32, i32, i32, s64)
> +DEF_HELPER_5(msa_clei_u_df, void, env,
On Tue, Jul 01, 2014 at 05:43:05PM +0100, Yongbok Kim wrote:
> Commit 240ce26a broke MIPS16 and microMIPS support as it didn't
> care those branches and jumps don't have delay slot in
> MIPS16 and microMIPS.
>
> This patch introduces a new argument delayslot_size to the
> gen_compute_branch() indi
Hi Peter,
On 10/07/14 13:17, Peter Maydell wrote:
> On 17 June 2014 23:10, James Hogan wrote:
>> The patchset depends on v4 of "target-mips: implement UserLocal
>> Register". I'm aiming for QEMU 2.1, hopefully it isn't too late to get
>> some final
On 14/07/14 15:35, Peter Maydell wrote:
> On 14 July 2014 14:33, James Hogan wrote:
>> On 10/07/14 13:17, Peter Maydell wrote:
>>> More generally, there doesn't really seem to be provision in the
>>> KVM KVM_EXIT_MMIO API for returning "this access failed&qu
gered with Malta emulation by making the guest
write to the reset region at physical address 0x1bf0, since it is
marked read-only which is treated as unassigned for writes.
Signed-off-by: James Hogan
Cc: Aurelien Jarno
Cc: Peter Maydell
Cc: Paolo Bonzini
Cc: Gleb Natapov
Cc: Christoffer Dal
Commit a07c67dfccb1 (Implement AT_CLKTCK.) back in March 2008 added a
new auxvec entry but didn't increment DLINFO_ITEMS, so it's been out of
sync ever since.
Bump it up to 14 so that it matches the number of NEW_AUX_ENT's that
need to be counted in create_elf_tables().
Signe
TARGET_NR__llseek as TARGET_NR_llseek.
Signed-off-by: James Hogan
Cc: Riku Voipio
Cc: Jia Liu
---
linux-user/syscall.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/linux-user/syscall.c b/linux-user/syscall.c
index 2eac6d5..8dbe39b 100644
--- a/linux-user/syscall.c
+++ b/linux-user/syscall.c
Assert that the amount of stack space used for auxvec, envp & argv
exactly matches the amount allocated. This catches if DLINFO_ITEMS isn't
updated when another NEW_AUX_ENT is added.
Signed-off-by: James Hogan
Cc: Riku Voipio
Cc: Peter Maydell
---
This should be applied after &q
On Tuesday 25 March 2014 22:20:04 Peter Maydell wrote:
> On 25 March 2014 21:47, James Hogan wrote:
> > Commit a07c67dfccb1 (Implement AT_CLKTCK.) back in March 2008 added a
> > new auxvec entry but didn't increment DLINFO_ITEMS, so it's been out of
> > sync ever s
On Tuesday 25 March 2014 23:51:39 Peter Maydell wrote:
> On 25 March 2014 23:40, James Hogan wrote:
> > I've already re-factored a bunch of this code to handle stacks which grow
> > upwards (as used for HPPA and Meta arches)
>
> ...we don't support either of
Hi Peter,
On 21/12/13 18:59, Peter Maydell wrote:
>> @@ -4526,6 +4529,7 @@ case "$target_name" in
>>\( "$target_name" = "ppc64" -a "$cpu" = "ppc" \) -o \
>>\( "$target_name" = "ppc"-a "$cpu" = "ppc64" \) -o \
>>\( "$target_name" = "ppcemb" -a "$cpu" = "ppc64" \) -o \
>
On 21/12/13 20:42, Peter Maydell wrote:
> On 16 December 2013 14:12, James Hogan wrote:
>> +#include "linux/kvm.h"
>
> You can't include linux/kvm.h like this -- on Linux this will pull in
> whatever the host's system kvm.h happens to be, and on non-Linux
Hi Andreas,
On 10/02/14 14:07, Andreas Färber wrote:
>> +#define dprintf(fmt, ...) \
>
> dprintf is the name of a stdio.h function, so DPRINTF may be a better name.
Okay.
>> +int kvm_arch_init_vcpu(CPUState *env)
>
> Please use "env" only for CPUMIPSState, use "cpu" or "cs" here. The
> usual c
arget_name = cpu = mips
- Remove mipsel cross compilation fix, which is now fixed by commit
61cc919f73ea (configure: detect endian via compile test)
- Add translation of guest kernel segments to allow an attached gdb to
see kernel memory correctly
James Hogan (3):
target-mips: get_physica
Add preprocessor definitions for 32bit segment bases for use in
get_physical_address(). These will also be taken advantage of in the
next patch which adds KVM awareness.
Signed-off-by: James Hogan
Cc: Aurelien Jarno
---
target-mips/helper.c | 18 --
1 file changed, 12
From: Sanjay Lal
COP0 emulation is in-kernel for KVM, so inject IRQ2 (I/O) interrupts via
ioctls.
Signed-off-by: Sanjay Lal
Signed-off-by: James Hogan
Cc: Aurelien Jarno
---
Changes in v2:
- Expand commit message
- Remove #ifdef CONFIG_KVM since it's guarded by kvm_enabled() al
-by: James Hogan
Cc: Gleb Natapov
Cc: Paolo Bonzini
---
Changes in v2:
- Expand commit message
- Reword comment
---
kvm-all.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/kvm-all.c b/kvm-all.c
index 4478969..c831326 100644
--- a/kvm-all.c
+++ b/kvm-all.c
@@ -2044,7 +2044,12 @@
From: Sanjay Lal
Enable KVM support for MIPS in the build system.
Signed-off-by: Sanjay Lal
Signed-off-by: James Hogan
Cc: Aurelien Jarno
---
Changes in v2:
- Expand commit message
- Remove GIC code
- Create asm-mips symlink using generic code and move above default
case (Peter Maydell
Signed-off-by: James Hogan
Cc: Aurelien Jarno
---
Changes in v2:
- Expand commit message
---
target-mips/mips-defs.h | 5 +
1 file changed, 5 insertions(+)
diff --git a/target-mips/mips-defs.h b/target-mips/mips-defs.h
index bf094a3..473ddf8 100644
--- a/target-mips/mips-defs.h
+++ b/target
In KVM mode the bootrom is loaded and executed from the last 1MB of
DRAM.
Based on "[PATCH 12/12] KVM/MIPS: General KVM support and support for
SMP Guests" by Sanjay Lal .
Signed-off-by: James Hogan
Cc: Aurelien Jarno
---
Changes in v2:
- Removal of cps / GIC / SMP support
From: Sanjay Lal
Compare/Count timer interrupts are handled in-kernel for KVM, so don't
bother starting it in QEMU.
Signed-off-by: Sanjay Lal
Signed-off-by: James Hogan
Cc: Aurelien Jarno
---
Changes in v2:
- Expand commit message
- Rebase on v1.7.0
- Wrap comment
---
hw/mips/cputi
From: Sanjay Lal
Implement the main KVM arch API for MIPS.
Signed-off-by: Sanjay Lal
Signed-off-by: James Hogan
Cc: Aurelien Jarno
Cc: Gleb Natapov
Cc: Paolo Bonzini
---
Changes in v2:
- Expand commit message
- Checkpatch cleanups.
- Some interrupt bug fixes from Yann Le Du
- Add get
address space: 0x..0x3fff
Guest Kernel Unmapped: 0x4000..0x5fff
Guest Kernel Mapped:0x6000..0x7fff
Signed-off-by: Sanjay Lal
Signed-off-by: James Hogan
Cc: Aurelien Jarno
---
Changes in v2:
- Expand commit message
- Remove unnecessary include
dard kseg0 or kseg2
address before doing the normal address translation. The real virtual
address is still used for TLB lookups.
Signed-off-by: James Hogan
Cc: Aurelien Jarno
---
target-mips/helper.c | 33 ++---
1 file changed, 26 insertions(+), 7 deletions(-)
diff -
Hi Nancy,
On 15/11/13 09:48, Nancy wrote:
> I notes the smp based on kvm implement, but there do not have kvm
> implement under target-mips? how this smp implement? Is there any
> document record the QEMU MIPS smp internal?
The KVM patchset added a binary blob of the CPS bootloader to support
mul
From: Sanjay Lal
COP0 emulation is in-kernel for KVM, so inject IRQ2 (I/O) interrupts via
ioctls.
Signed-off-by: Sanjay Lal
Signed-off-by: James Hogan
Reviewed-by: Aurelien Jarno
Cc: Andreas Färber
---
Changes in v3:
- Pass MIPSCPU to kvm_mips_set_[ipi_]interrupt (Andreas Färber).
Changes
Add preprocessor definitions for 32bit segment bases for use in
get_physical_address(). These will also be taken advantage of in the
next patch which adds KVM awareness.
Signed-off-by: James Hogan
Reviewed-by: Aurelien Jarno
---
target-mips/helper.c | 18 --
1 file changed, 12
From: Sanjay Lal
Compare/Count timer interrupts are handled in-kernel for KVM, so don't
bother starting it in QEMU.
Signed-off-by: Sanjay Lal
Signed-off-by: James Hogan
Reviewed-by: Aurelien Jarno
---
Changes in v2:
- Expand commit message
- Rebase on v1.7.0
- Wrap comment
---
hw
address space: 0x..0x3fff
Guest Kernel Unmapped: 0x4000..0x5fff
Guest Kernel Mapped:0x6000..0x7fff
Signed-off-by: Sanjay Lal
Signed-off-by: James Hogan
Reviewed-by: Aurelien Jarno
---
Changes in v2:
- Expand commit message
- Remove unnecessary
From: Sanjay Lal
Implement the main KVM arch API for MIPS.
Signed-off-by: Sanjay Lal
Signed-off-by: James Hogan
Cc: Aurelien Jarno
Cc: Gleb Natapov
Cc: Paolo Bonzini
Cc: Andreas Färber
Cc: Peter Maydell
---
Changes in v3:
- s/dprintf/DPRINTF/ (Andreas Färber).
- Use "cs" r
From: Sanjay Lal
Enable KVM support for MIPS in the build system.
Signed-off-by: Sanjay Lal
Signed-off-by: James Hogan
Reviewed-by: Aurelien Jarno
---
Changes in v2:
- Expand commit message
- Remove GIC code
- Create asm-mips symlink using generic code and move above default
case
g generic code and move above default
case (Peter Maydell)
- Remove redundant check of target_name = cpu = mips
- Remove mipsel cross compilation fix, which is now fixed by commit
61cc919f73ea (configure: detect endian via compile test)
- Add translation of guest kernel segments
dard kseg0 or kseg2
address before doing the normal address translation. The real virtual
address is still used for TLB lookups.
Signed-off-by: James Hogan
Cc: Aurelien Jarno
---
target-mips/helper.c | 33 ++---
1 file changed, 26 insertions(+), 7 deletions(-)
diff -
rom kvm_arch_init(). Otherwise default to 8
bytes.
Signed-off-by: James Hogan
Cc: Aurelien Jarno
Cc: Sanjay Lal
Cc: Gleb Natapov
Cc: Paolo Bonzini
Cc: Peter Maydell
---
Changes in v3:
- Rewrote to allow sigmask length to be set by kvm_arch_init(), so that
MIPS can set it to 16 as it has
In KVM mode the bootrom is loaded and executed from the last 1MB of
DRAM.
Based on "[PATCH 12/12] KVM/MIPS: General KVM support and support for
SMP Guests" by Sanjay Lal .
Signed-off-by: James Hogan
Reviewed-by: Aurelien Jarno
Cc: Peter Maydell
Cc: Sanjay Lal
---
Changes in v3:
Hi Andreas,
On 13/03/14 21:28, Andreas Färber wrote:
>> diff --git a/target-mips/kvm.c b/target-mips/kvm.c
>> new file mode 100644
>> index 000..0ec343d
>> --- /dev/null
>> +++ b/target-mips/kvm.c
> [...]
>> +static inline int kvm_mips_put_one_reg(CPUState *cs, int reg_id, int32
>> *addr)
>
On 13/03/14 22:35, Peter Maydell wrote:
> On 13 March 2014 21:28, Andreas Färber wrote:
>> I'm not sure if we have a policy about __u64 etc. in KVM code. Since
>> it'll be Linux-only I don't see problems currently; for cross-platform
>> parts we prefer uint64_t. Suggest to leave as is unless told
rom kvm_arch_init(). Otherwise default to 8
bytes.
Signed-off-by: James Hogan
Cc: Aurelien Jarno
Cc: Sanjay Lal
Cc: Gleb Natapov
Cc: Paolo Bonzini
Cc: Peter Maydell
---
Changes in v3:
- Rewrote to allow sigmask length to be set by kvm_arch_init(), so that
MIPS can set it to 16 as it has
From: Sanjay Lal
Compare/Count timer interrupts are handled in-kernel for KVM, so don't
bother starting it in QEMU.
Signed-off-by: Sanjay Lal
Signed-off-by: James Hogan
Reviewed-by: Aurelien Jarno
---
Changes in v2:
- Expand commit message
- Rebase on v1.7.0
- Wrap comment
---
hw
From: Sanjay Lal
COP0 emulation is in-kernel for KVM, so inject IRQ2 (I/O) interrupts via
ioctls.
Signed-off-by: Sanjay Lal
Signed-off-by: James Hogan
Reviewed-by: Aurelien Jarno
Reviewed-by: Andreas Färber
---
Changes in v3:
- Pass MIPSCPU to kvm_mips_set_[ipi_]interrupt (Andreas Färber
Add preprocessor definitions for 32bit segment bases for use in
get_physical_address(). These will also be taken advantage of in the
next patch which adds KVM awareness.
Signed-off-by: James Hogan
Reviewed-by: Aurelien Jarno
---
target-mips/helper.c | 18 --
1 file changed, 12
1 - 100 of 323 matches
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