Hi Aleksandar,
> I am glad that you want to include QEMU disas support for R5900 - this
> area usually gets forgotten.
>
> But, as you can see, this MIPS feature is partially broken - it doesn't
> handle well overlapping opcodes, and the field "membership" is not taken
> into account at all. I th
Hi Aleksandar,
> I think the following code would be even better:
>
> case OPC_SC:
> check_insn(ctx, ISA_MIPS2);
> check_insn_opc_removed(ctx, ISA_MIPS32R6);
> if (ctx->insn_flags & INSN_R5900) {
> check_insn_opc_user_only(ctx, INSN_R5900);
> }
>
MFLO1, MFHI1, MTLO1 and MTHI1 are generated in gen_HILO1_tx79 instead of
the generic gen_HILO.
Signed-off-by: Fredrik Noring
---
target/mips/translate.c | 51 -
1 file changed, 40 insertions(+), 11 deletions(-)
diff --git a/target/mips/translate.c b
")
Cc: Jia Liu
Reported-by: Maciej W. Rozycki
Signed-off-by: Fredrik Noring
---
target/mips/translate.c | 36
1 file changed, 4 insertions(+), 32 deletions(-)
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 3ddd70043a..19ae7d2f1c 1006
O 32-bit truncation with the MIPS64 DSP ASE
- Decode special R5900 opcodes in decode_opc_special_tx79
- Guard check_insn_opc_user_only with INSN_R5900 check
- Guard check_insn with INSN_R5900 check
Fredrik Noring (6):
target/mips: Fix decoding mechanism of R5900 MFLO1, MFHI1, MTLO1 and MTHI1
tar
DIV1 and DIVU1 are generated in gen_div1_tx79 instead of the generic
gen_muldiv.
Signed-off-by: Fredrik Noring
Reviewed-by: Philippe Mathieu-Daudé
---
target/mips/translate.c | 65 +
1 file changed, 59 insertions(+), 6 deletions(-)
diff --git a/target
MOVN, MOVZ, MFHI, MFLO, MTHI, MTLO, MULT, MULTU, DIV, DIVU, DMULT,
DMULTU, DDIV, DDIVU and JR are decoded in decode_opc_special_tx79
instead of the generic decode_opc_special_legacy.
Signed-off-by: Fredrik Noring
---
target/mips/translate.c | 54 ++---
1 file
Signed-off-by: Fredrik Noring
---
target/mips/translate.c | 16
1 file changed, 12 insertions(+), 4 deletions(-)
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 45ad70c097..c3ed4c21ce 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
Signed-off-by: Fredrik Noring
---
target/mips/translate.c | 7 +--
1 file changed, 5 insertions(+), 2 deletions(-)
diff --git a/target/mips/translate.c b/target/mips/translate.c
index c3ed4c21ce..007dfd2975 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -28329,8
-m64 x mipsn32el-linux-user
in addition successfully completing the R5900 test suite
cd tests/tcg/mips/mipsr5900 && make check
cd tests/tcg/mips/mipsn32r5900 && make check
Fredrik Noring (2):
linux-user/mips: Support the n32 ABI for the R5900
tests/tcg/mips: Test use
Recognise the R5900, which reports itself as MIPS III, as a 64-bit CPU
supporting the n32 ABI.
Signed-off-by: Fredrik Noring
---
linux-user/mips64/target_elf.h | 3 +++
1 file changed, 3 insertions(+)
diff --git a/linux-user/mips64/target_elf.h b/linux-user/mips64/target_elf.h
index ec55d8542a
The R5900 reports itself as MIPS III but does not implement DMULT.
Verify that DMULT is emulated properly in user mode by multiplying
two 64-bit numbers to produce a 128-bit number.
Signed-off-by: Fredrik Noring
---
tests/tcg/mips/mipsn32r5900/Makefile | 25 +
tests/tcg/mips
Hi Aleksandar,
> Fredrik, do you know by any chance if a document exists that would justify
> inclusion of non-R5900 DMULT, DMULTU, DDIV, DDIVU in R5900 executables by
> gcc for R5900? Is it included by cross-gcc or by native gcc, or by both?
>
> I think gcc folks must have had a good reason for
Hi Aleksandar,
> > The R5900 reports itself as MIPS III ...
>
> This is very unclear. What do you mean by this? How does R5900 do that? I
> can't find any trace of such intentions in R5900 docs.
In QEMU, we have previously defined the R5900 as MIPS III by
#define CPU_R5900 (CPU_MIPS3 | INSN_R59
Hi Aleksandar,
> Tx79 mentions the opposite: that DDIV, DDIVU, DMULT, DMULTU are not
> included in R5900 set.
>
> I think that the best solution that you exclude DDIV, DDIVU, DMULT, DMULTU
> in a separate patch - there is no document to support their inclusion.
As Maciej noted, the 64-bit MIPS L
Hi Philippe,
On Tue, Nov 13, 2018 at 11:51:54PM +0100, Philippe Mathieu-Daudé wrote:
> On Tue, Nov 13, 2018 at 8:29 PM Philippe Mathieu-Daudé
> wrote:
> > On Tue, Nov 13, 2018 at 8:08 PM Aleksandar Markovic
> > wrote:
> > >
> > > From: Aleksandar Markovic
> > >
> > > Disable R5900 support. Ther
l requires and emulates LL and SC for the R5900 too. The
special --without-llsc default for the R5900 is therefore not applicable
in that case.
Reviewed-by: Maciej W. Rozycki
2018-11-12 Fredrik Noring
gcc/
* config.gcc: Update with-llsc defaults for MIPS r5900.
git-svn-id: svn+ssh:/
Hi Alex,
> This fails to build glibc, but doesn't exactly give much info:
>
>* Log: /var/log/portage/cross-mipsr5900el-unknown-linux-gnu-binutils.log
>* Emerging cross-binutils ...[
> ok ]
>* Log:
> /var/log/portage/cross-mipsr5900el-unkno
Hi Maciej,
> Of course you can instead just set the default manually by using
> `--with-llsc' when configuring GCC or specify `-mllsc' explicitly in
> CFLAGS with a compiler that has been already built without that set by
> default.
There are ways to pass such flags to the crossdev command, b
:
- Update mips_defs array with R5900 values
- LL/SC and FPU are user only
Fredrik Noring (7):
target/mips: Define R5900 instructions and CPU preprocessor constants
target/mips: Support R5900 specific three-operand MULT and MULTU
target/mips: Support R5900 instructions MOVN, MOVZ and PREF from M
specific pipeline 1 instruction variants MULT1,
MULTU1, DIV1, DIVU1, MADD1, MADDU1, MFHI1, MFLO1, MTHI1 and MTLO1
are omitted here as well.
Signed-off-by: Fredrik Noring
Reviewed-by: Philippe Mathieu-Daudé
---
target/mips/translate.c | 73 +
1 file
follow-up to the R5900. There
are a few notable differences in that the R5900 FPU
- is not IEEE 754-1985 compliant,
- does not implement double format, and
- its machine code is nonstandard.
Signed-off-by: Fredrik Noring
Reviewed-by: Philippe Mathieu-Daudé
---
target/mips/mips-defs.h | 2 ++
1
: Fredrik Noring
Reviewed-by: Philippe Mathieu-Daudé
---
target/mips/translate_init.inc.c | 59
1 file changed, 59 insertions(+)
diff --git a/target/mips/translate_init.inc.c b/target/mips/translate_init.inc.c
index b3320b9dc7..b5dacf4ffe 100644
--- a/target/mips
This kind of ELF for the R5900 relies on an IEEE 754-1985 compliant FPU.
The R5900 FPU hardware is noncompliant and it is therefore emulated in
software by the Linux kernel. QEMU emulates a compliant FPU accordingly.
Signed-off-by: Fredrik Noring
Reviewed-by: Philippe Mathieu-Daudé
---
linux
for flagged CPUs in QEMU system mode.
The MIPS III instructions DMULT[U], DDIV[U], LL[D] and SC[D] are not
implemented in R5900 hardware. They are trapped and emulated by the
Linux kernel and, accordingly, therefore QEMU user only instructions.
Signed-off-by: Fredrik Noring
Reviewed-by: Philippe
The R5900 is taken to be MIPS III with certain modifications. From
MIPS IV it implements the instructions MOVN, MOVZ and PREF.
Signed-off-by: Fredrik Noring
Reviewed-by: Philippe Mathieu-Daudé
---
target/mips/translate.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a
: Maciej W. Rozycki
Signed-off-by: Fredrik Noring
Reviewed-by: Philippe Mathieu-Daudé
---
include/elf.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/include/elf.h b/include/elf.h
index 312f68af81..2510fc7be4 100644
--- a/include/elf.h
+++ b/include/elf.h
@@ -76,7 +76,7
Hi Philippe,
> --- a/target/mips/translate.c
> +++ b/target/mips/translate.c
> @@ -3843,6 +3843,46 @@ static void gen_mul_txx9(DisasContext *ctx, uint32_t
> opc,
What about documenting MADD and MADDU along with MULT and MULTU in the
note above?
> +case OPC_MADD:
This case is unreachable, b
Hi Philippe,
> That's true it is not reachable, it lacks the INSN_R3900 definition,
> used by the R3900 mips_def_t.
>
> I'll stop bothering with this until the code is reachable (my branch posted).
I would be happy if your patch could be merged soon. Adding the following
five lines to it would m
Hi Maciej, Philippe,
> So results of individual operations are as in the comments with this
> code:
>
> mthi$0 # HI <- 0
> mtlo$0 # LO <- 0
> addiu $2, $0, 1 # $2 <- 1
> lui $3, 0x4000 # $3 <- 0x4000
> maddu
Hi Aleksandar,
> A peculiar case of DMULTU would be interesting.
Agreed, DMULTU would be good to test as well. (DMULTU isn't part of the
R5900 ISA, though.)
> It would be nice to implement just a single instruction from MMI, let's
> say PAND, and have a test for it.
Most if not all multimedia i
Hi Richard,
> > /* global register indices */
> > static TCGv cpu_gpr[32], cpu_PC;
> > static TCGv cpu_HI[MIPS_DSP_ACC], cpu_LO[MIPS_DSP_ACC];
> >
> > One option is to create a new array such as
> >
> > static TCGv_i64 mmi_gpr[32];
> >
> > that represents the upper 64 bits of each GPR. Then cpu
Hi Maciej,
> The C790 is a follow-up to the R5900. The R5900 has an FPU that is not
> compliant to the IEEE 754 standard for floating-point arithmetic. It
> doesn't implement exceptions, infinities, NaNs or denormals. It doesn't
> implement the the double format either, but that is really t
Hi Aleksandar,
> Your series is getting better and better with each version, which is very
> good. For a change, I don't have any objection about the title. :)
Good!
> Patch 7 will be integrated shortly in the MIPS queue, you don't need to
> worry about it.
Thanks!
> With this series you are n
EGBITS and PABITS
- Fix indentation
Changes in v3:
- Apply to HEAD
- Remove the word "initial" from subject line
Changes in v2:
- Update mips_defs array with R5900 values
- LL/SC and FPU are user only
Fredrik Noring (38):
target/mips: Define R5900 instructions and CPU preprocessor co
the R5900. There
are a few notable differences in that the R5900 FPU
- is not IEEE 754-1985 compliant,
- does not implement double format, and
- its machine code is nonstandard.
Signed-off-by: Fredrik Noring
Reviewed-by: Philippe Mathieu-Daudé
---
target/mips/mips-defs.h | 2 ++
1 file changed, 2
Signed-off-by: Fredrik Noring
---
target/mips/translate.c | 51 +
1 file changed, 51 insertions(+)
diff --git a/target/mips/translate.c b/target/mips/translate.c
index e205c3eaef..ae988177a1 100644
--- a/target/mips/translate.c
+++ b/target/mips
Signed-off-by: Fredrik Noring
---
disas/mips.c | 8
1 file changed, 8 insertions(+)
diff --git a/disas/mips.c b/disas/mips.c
index 97f661a37e..ae72059c46 100644
--- a/disas/mips.c
+++ b/disas/mips.c
@@ -611,6 +611,9 @@ struct mips_opcode
/* ST Microelectronics Loongson 2F
Signed-off-by: Fredrik Noring
---
target/mips/translate.c | 40
1 file changed, 40 insertions(+)
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 32d1d2d83f..e205c3eaef 100644
--- a/target/mips/translate.c
+++ b/target/mips
Signed-off-by: Fredrik Noring
---
target/mips/translate.c | 44 +
1 file changed, 44 insertions(+)
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 242f2df2e2..e233b87324 100644
--- a/target/mips/translate.c
+++ b/target/mips
Signed-off-by: Fredrik Noring
---
target/mips/translate.c | 161
1 file changed, 161 insertions(+)
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 3a0bdd55c8..32d1d2d83f 100644
--- a/target/mips/translate.c
+++ b/target/mips
Signed-off-by: Fredrik Noring
---
target/mips/translate.c | 51 +
1 file changed, 51 insertions(+)
diff --git a/target/mips/translate.c b/target/mips/translate.c
index ae988177a1..242f2df2e2 100644
--- a/target/mips/translate.c
+++ b/target/mips
Signed-off-by: Fredrik Noring
---
target/mips/translate.c | 39 +++
1 file changed, 39 insertions(+)
diff --git a/target/mips/translate.c b/target/mips/translate.c
index bd51443ac1..3c6a2c99a6 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
Signed-off-by: Fredrik Noring
---
target/mips/translate.c | 53 -
1 file changed, 52 insertions(+), 1 deletion(-)
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 3c6a2c99a6..19a8abad54 100644
--- a/target/mips/translate.c
+++ b/target
Signed-off-by: Fredrik Noring
---
target/mips/translate.c | 43 -
1 file changed, 42 insertions(+), 1 deletion(-)
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 3b100f2d17..c8080844f1 100644
--- a/target/mips/translate.c
+++ b/target
Signed-off-by: Fredrik Noring
---
target/mips/translate.c | 48 +
1 file changed, 48 insertions(+)
diff --git a/target/mips/translate.c b/target/mips/translate.c
index e233b87324..bd51443ac1 100644
--- a/target/mips/translate.c
+++ b/target/mips
Signed-off-by: Fredrik Noring
---
disas/mips.c| 2 ++
target/mips/translate.c | 38 +-
2 files changed, 35 insertions(+), 5 deletions(-)
diff --git a/disas/mips.c b/disas/mips.c
index 79bd119c51..242bf68b9c 100644
--- a/disas/mips.c
+++ b/disas
Signed-off-by: Fredrik Noring
---
target/mips/translate.c | 36 +++-
1 file changed, 35 insertions(+), 1 deletion(-)
diff --git a/target/mips/translate.c b/target/mips/translate.c
index c8080844f1..28137cdaf4 100644
--- a/target/mips/translate.c
+++ b/target/mips
Signed-off-by: Fredrik Noring
---
target/mips/translate.c | 13 +++--
1 file changed, 11 insertions(+), 2 deletions(-)
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 19a8abad54..2318116d31 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
Signed-off-by: Fredrik Noring
---
target/mips/translate.c | 31 ++-
1 file changed, 30 insertions(+), 1 deletion(-)
diff --git a/target/mips/translate.c b/target/mips/translate.c
index e5ac9f17e0..6d837082a9 100644
--- a/target/mips/translate.c
+++ b/target/mips
Signed-off-by: Fredrik Noring
---
tests/tcg/mips/mipsr5900/multu.c | 43 ++--
1 file changed, 36 insertions(+), 7 deletions(-)
diff --git a/tests/tcg/mips/mipsr5900/multu.c b/tests/tcg/mips/mipsr5900/multu.c
index 3a59675395..f043904d69 100644
--- a/tests/tcg/mips
Signed-off-by: Fredrik Noring
---
target/mips/translate.c | 17 ++---
1 file changed, 14 insertions(+), 3 deletions(-)
diff --git a/target/mips/translate.c b/target/mips/translate.c
index eb7437cc09..df69fa0e9f 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
-specific pipeline 1 instruction variants MULT1,
MULTU1, DIV1, DIVU1, MADD1, MADDU1, MFHI1, MFLO1, MTHI1 and MTLO1
are omitted here as well.
Signed-off-by: Fredrik Noring
Reviewed-by: Philippe Mathieu-Daudé
---
target/mips/translate.c | 74 +
1 file changed, 74
Signed-off-by: Fredrik Noring
---
target/mips/translate.c | 45 -
1 file changed, 44 insertions(+), 1 deletion(-)
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 2318116d31..3b100f2d17 100644
--- a/target/mips/translate.c
+++ b/target
Signed-off-by: Fredrik Noring
---
tests/tcg/mips/mipsr5900/Makefile | 1 +
tests/tcg/mips/mipsr5900/madd.c | 45 +++
2 files changed, 46 insertions(+)
create mode 100644 tests/tcg/mips/mipsr5900/madd.c
diff --git a/tests/tcg/mips/mipsr5900/Makefile
b/tests/tcg
Signed-off-by: Fredrik Noring
---
disas/mips.c| 4
target/mips/translate.c | 23 +--
2 files changed, 21 insertions(+), 6 deletions(-)
diff --git a/disas/mips.c b/disas/mips.c
index ae72059c46..e86a2b8764 100644
--- a/disas/mips.c
+++ b/disas/mips.c
Signed-off-by: Fredrik Noring
---
target/mips/translate.c | 40 +++-
1 file changed, 39 insertions(+), 1 deletion(-)
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 28137cdaf4..e5ac9f17e0 100644
--- a/target/mips/translate.c
+++ b/target
This kind of ELF for the R5900 relies on an IEEE 754-1985 compliant FPU.
The R5900 FPU hardware is noncompliant and it is therefore emulated in
software by the Linux kernel. QEMU emulates a compliant FPU accordingly.
Signed-off-by: Fredrik Noring
Reviewed-by: Philippe Mathieu-Daudé
---
linux
The R5900 is taken to be MIPS III with certain modifications. From
MIPS IV it implements the instructions MOVN, MOVZ and PREF.
Signed-off-by: Fredrik Noring
Reviewed-by: Philippe Mathieu-Daudé
---
target/mips/translate.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a
Signed-off-by: Fredrik Noring
---
tests/tcg/mips/mipsr5900/Makefile | 25
tests/tcg/mips/mipsr5900/mult.c | 47 +++
2 files changed, 72 insertions(+)
create mode 100644 tests/tcg/mips/mipsr5900/Makefile
create mode 100644 tests/tcg/mips/mipsr5900
Signed-off-by: Fredrik Noring
---
disas/mips.c| 4
target/mips/translate.c | 12 +---
2 files changed, 13 insertions(+), 3 deletions(-)
diff --git a/disas/mips.c b/disas/mips.c
index e86a2b8764..79bd119c51 100644
--- a/disas/mips.c
+++ b/disas/mips.c
@@ -2323,6 +2323,8
Signed-off-by: Fredrik Noring
---
disas/mips.c| 2 ++
target/mips/translate.c | 28
2 files changed, 26 insertions(+), 4 deletions(-)
diff --git a/disas/mips.c b/disas/mips.c
index 242bf68b9c..78c4fb6efa 100644
--- a/disas/mips.c
+++ b/disas/mips.c
Signed-off-by: Fredrik Noring
---
tests/tcg/mips/mipsr5900/Makefile | 3 +-
tests/tcg/mips/mipsr5900/div1.c | 73 +++
2 files changed, 75 insertions(+), 1 deletion(-)
create mode 100644 tests/tcg/mips/mipsr5900/div1.c
diff --git a/tests/tcg/mips/mipsr5900
for flagged CPUs in QEMU system mode.
The MIPS III instructions DMULT[U], DDIV[U], LL[D] and SC[D] are not
implemented in R5900 hardware. They are trapped and emulated by the
Linux kernel and, accordingly, therefore QEMU user only instructions.
Signed-off-by: Fredrik Noring
Reviewed-by: Philippe
Signed-off-by: Fredrik Noring
---
tests/tcg/mips/mipsr5900/mult.c | 45 +++--
1 file changed, 37 insertions(+), 8 deletions(-)
diff --git a/tests/tcg/mips/mipsr5900/mult.c b/tests/tcg/mips/mipsr5900/mult.c
index 2c0c16d232..5710b395e6 100644
--- a/tests/tcg/mips
Signed-off-by: Fredrik Noring
---
tests/tcg/mips/mipsr5900/Makefile | 1 +
tests/tcg/mips/mipsr5900/maddu.c | 37 +++
2 files changed, 38 insertions(+)
create mode 100644 tests/tcg/mips/mipsr5900/maddu.c
diff --git a/tests/tcg/mips/mipsr5900/Makefile
b/tests/tcg
Signed-off-by: Fredrik Noring
---
tests/tcg/mips/mipsr5900/Makefile | 1 +
tests/tcg/mips/mipsr5900/multu.c | 39 +++
2 files changed, 40 insertions(+)
create mode 100644 tests/tcg/mips/mipsr5900/multu.c
diff --git a/tests/tcg/mips/mipsr5900/Makefile
b/tests/tcg
Signed-off-by: Fredrik Noring
---
tests/tcg/mips/mipsr5900/Makefile | 1 +
tests/tcg/mips/mipsr5900/mtlohi1.c | 40 ++
2 files changed, 41 insertions(+)
create mode 100644 tests/tcg/mips/mipsr5900/mtlohi1.c
diff --git a/tests/tcg/mips/mipsr5900/Makefile
b/tests
Signed-off-by: Fredrik Noring
---
tests/tcg/mips/mipsr5900/maddu.c | 37 ++--
1 file changed, 35 insertions(+), 2 deletions(-)
diff --git a/tests/tcg/mips/mipsr5900/maddu.c b/tests/tcg/mips/mipsr5900/maddu.c
index e4e552102d..30936fb2b4 100644
--- a/tests/tcg/mips
Signed-off-by: Fredrik Noring
---
tests/tcg/mips/mipsr5900/Makefile | 3 ++-
tests/tcg/mips/mipsr5900/mflohi1.c | 35 ++
2 files changed, 37 insertions(+), 1 deletion(-)
create mode 100644 tests/tcg/mips/mipsr5900/mflohi1.c
diff --git a/tests/tcg/mips/mipsr5900
Signed-off-by: Fredrik Noring
---
tests/tcg/mips/mipsr5900/Makefile | 1 +
tests/tcg/mips/mipsr5900/divu1.c | 48 +++
2 files changed, 49 insertions(+)
create mode 100644 tests/tcg/mips/mipsr5900/divu1.c
diff --git a/tests/tcg/mips/mipsr5900/Makefile
b/tests/tcg
: Fredrik Noring
Reviewed-by: Philippe Mathieu-Daudé
---
target/mips/translate_init.inc.c | 59
1 file changed, 59 insertions(+)
diff --git a/target/mips/translate_init.inc.c b/target/mips/translate_init.inc.c
index acab097820..07a6c81e68 100644
--- a/target/mips
Signed-off-by: Fredrik Noring
---
tests/tcg/mips/mipsr5900/madd.c | 43 +
1 file changed, 38 insertions(+), 5 deletions(-)
diff --git a/tests/tcg/mips/mipsr5900/madd.c b/tests/tcg/mips/mipsr5900/madd.c
index 9ad2ea6dbb..f6f215e1c3 100644
--- a/tests/tcg/mips
Many thanks, Aleksandar,
> I added ASE_MMI flag along with INSN_R5900, I think this fits better in
> the overall MIPS for QEMU design.
Maciej -- can we add "MMI" under "ASEs implemented" in the kernel too,
even if it is a vendor-specific architecture extension that normally
isn't counted as an AS
Hi Aleksandar,
> Pull request with 32 patches from this series is already sent, and I would
> like to avoid sending v2 of that request. Let's wait for some time until
> the pull request is hopefully accepted. There will be most likely another
> one at the beginning of the next week.
>
> We are ap
Hi Maciej,
> I have no authority to approve such a change for the kernel, but it looks
> reasonable to me and I will support you with it, with one reservation
> however. As this is an ISA extension in the vendor-specific space, I
> think it belongs to a vendor-specific namespace, so as to mak
Hi Maciej,
> target/mips/translate.c:4888:38: error: passing argument 3 of
> ‘tcg_gen_add2_i32’ from incompatible pointer type
> [-Werror=incompatible-pointer-types]
> tcg_gen_add2_i32(t2, t3, cpu_LO[acc], cpu_HI[acc], t2, t3);
> ^~
Would you
Hi Peter, Aleksandar,
> Hi: I get compile errors on 32-bit hosts:
>
> /home/petmay01/qemu-for-merges/disas/mips.c:615:35: error: large
> integer implicitly truncated to unsigned type [-Werror=overflow]
> #define INSN_5900 0x1
>^
> /home/
Hi Philippe,
On Wed, Oct 24, 2018 at 12:57:32PM +0200, Philippe Mathieu-Daudé wrote:
> Increase the size of 'membership' holder size to 64 bits. This is
> needed for future extensions since existing bits are almost all used.
> (This change is related to f9c9cd63e3),
I'm queueing your patch to ame
Hi Philippe,
> The three-operand MADD and MADDU are specific to the
> Toshiba TX19/TX39/TX79 cores.
>
> The "32-Bit TX System RISC TX39 Family Architecture manual"
> is available at https://wiki.qemu.org/File:DSAE0022432.pdf
>
> Signed-off-by: Philippe Mathieu-Daudé
I'm queueing your MADD and M
Hi Richard,
> > Option 3: Extend the mips_opcode::membership field.
>
> It's trivial to extend the field to uint64_t.
Is the membership field intended to be used? The opcodes for CLZ and CLO
clash with the R5900 opcodes for MADD1 and MADDU1, resulting in incorrect
disassembly of MADD1 and MADDU1
y: Fredrik Noring
Tested-by: Fredrik Noring
---
target/mips/translate.c | 58 +
1 file changed, 53 insertions(+), 5 deletions(-)
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 18167df26d..add6203c5a 100644
--- a/target/mips/transla
Signed-off-by: Fredrik Noring
---
tests/tcg/mips/mipsr5900/madd.c | 43 +
1 file changed, 38 insertions(+), 5 deletions(-)
diff --git a/tests/tcg/mips/mipsr5900/madd.c b/tests/tcg/mips/mipsr5900/madd.c
index 9ad2ea6dbb..f6f215e1c3 100644
--- a/tests/tcg/mips
R5900 test suite
cd tests/tcg/mips/mipsr5900 && make check
Reference:
[1] "Toshiba TX System RISC TX79 Core Architecture", Toshiba Corporation,
section B.3.2, p. B-4, <https://wiki.qemu.org/File:C790.pdf>.
Fredrik Noring (9):
target/mips: Rename ASE_MMI to ASE_T
Signed-off-by: Fredrik Noring
---
target/mips/translate.c | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 8547a6e6f6..18167df26d 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -26100,7
Signed-off-by: Fredrik Noring
---
tests/tcg/mips/mipsr5900/Makefile | 1 +
tests/tcg/mips/mipsr5900/maddu.c | 37 +++
2 files changed, 38 insertions(+)
create mode 100644 tests/tcg/mips/mipsr5900/maddu.c
diff --git a/tests/tcg/mips/mipsr5900/Makefile
b/tests/tcg
Signed-off-by: Fredrik Noring
---
tests/tcg/mips/mipsr5900/maddu.c | 37 ++--
1 file changed, 35 insertions(+), 2 deletions(-)
diff --git a/tests/tcg/mips/mipsr5900/maddu.c b/tests/tcg/mips/mipsr5900/maddu.c
index e4e552102d..30936fb2b4 100644
--- a/tests/tcg/mips
Signed-off-by: Fredrik Noring
---
tests/tcg/mips/mipsr5900/Makefile | 1 +
tests/tcg/mips/mipsr5900/madd.c | 45 +++
2 files changed, 46 insertions(+)
create mode 100644 tests/tcg/mips/mipsr5900/madd.c
diff --git a/tests/tcg/mips/mipsr5900/Makefile
b/tests/tcg
Amend definition for MIPS ISAs in disassembler with R5900.
Signed-off-by: Fredrik Noring
---
disas/mips.c | 8
1 file changed, 8 insertions(+)
diff --git a/disas/mips.c b/disas/mips.c
index d73d4094d8..9f01fda8bd 100644
--- a/disas/mips.c
+++ b/disas/mips.c
@@ -611,6 +611,9 @@ struct
der size".
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
Tested-by: Fredrik Noring
Signed-off-by: Fredrik Noring
---
disas/mips.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/disas/mips.c b/disas/mips.c
index 97f661a37e..d73d4094d8 100644
--- a/d
Signed-off-by: Fredrik Noring
---
target/mips/translate.c | 12 +---
1 file changed, 9 insertions(+), 3 deletions(-)
diff --git a/target/mips/translate.c b/target/mips/translate.c
index add6203c5a..208a15c0c1 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -4813,7
Several vendors have multimedia instruction (MMI) sets and other
extensions of various kinds. ASE vendor namespaces make it clear these
are not generic architectural features and also avoid name clashes.
Reported-by: Maciej W. Rozycki
Signed-off-by: Fredrik Noring
---
target/mips/mips-defs.h
Disassemble the R5900 instructions DIV1, DIVU1, MFLO1, MTLO1, MFHI1,
MTHI1, MULT1 and MULTU1.
Signed-off-by: Fredrik Noring
---
disas/mips.c | 12
1 file changed, 12 insertions(+)
diff --git a/disas/mips.c b/disas/mips.c
index 9f01fda8bd..eddfb59325 100644
--- a/disas/mips.c
+++ b
Hi Maciej,
> > Is the membership field intended to be used? The opcodes for CLZ and CLO
> > clash with the R5900 opcodes for MADD1 and MADDU1, resulting in incorrect
> > disassembly of MADD1 and MADDU1. For example:
> >
> > 0x70853020 madd1 a2,a0,a1 disassembles into clz a2 or a1,a0
> >
Hi Maciej,
> I'm not sure if every single random vendor-specific instruction (or a
> bunch of) deserves its own ASE designation, be it internal or externally
> exposed. I think the MMI set being a substantial architectural feature
> makes sense to be shown in /proc/cpuinfo (in Linux), but I d
Hi Aleksandar,
> This series renames MMI-related code elements so that they do not
> contain TX79 substring. Tx79 is one of CPUs that support MMI ASE.
> Opcodes and other code elements should be as generic as possible,
> and should not contain CPU name if they are supported by multiple
> CPUs. In
Hi Aleksandar,
> Without TARGET_MIPS64, we can't say we emulate R5900 - we are emulating
> some other CPU that never existed.
>
> Convince me that I am wrong.
R5900 O32 is usable. The R5900 toolchain is not yet ready for N32. Regarding
your proposal to rename TX79_MMI to MMI: what other ISAs do
[ Philippe and Emilio -- thank you for cc-ing me. Good catch, since I'm
not subscribed to the QEMU mailing list. Changes to the R5900 emulation
are certainly of interest. ]
Hi Aleksandar, Philippe,
On Thu, Nov 01, 2018 at 03:31:54PM +0100, Philippe Mathieu-Daudé wrote:
> Cc'ing Fredrik.
>
> On 1
https://wiki.qemu.org/File:C790.pdf>.
Changes in v2:
- Drop rejected rename of ASE_MMI to ASE_TOSHIBA_MMI
- Generate R5900 DIV1 and DIVU1 in gen_div1_tx79
- Generate R5900 MFLO1, MFHI1, MTLO1 and MTHI1 in gen_HILO1_tx79
Fredrik Noring (10):
target/mips: Generate R5900 MFLO1, MFHI1, MTLO1 and
MFLO1, MFHI1, MTLO1 and MTHI1 are generated in gen_HILO1_tx79 instead of
the generic gen_HILO.
Signed-off-by: Fredrik Noring
---
target/mips/translate.c | 67 ++---
1 file changed, 56 insertions(+), 11 deletions(-)
diff --git a/target/mips/translate.c b
1 - 100 of 188 matches
Mail list logo
