[RFC 59/65] target/riscv: rvv-0.9: narrowing floating-point/integer type-convert

From: Frank Chang Signed-off-by: Frank Chang --- target/riscv/helper.h | 30 +--- target/riscv/insn32.decode | 15 ++-- target/riscv/insn_trans/trans_rvv.inc.c | 50 +++-- target/riscv/vector_helper.c| 99 - 4 files

[RFC 41/65] target/riscv: rvv-0.9: floating-point compare instructions

From: Frank Chang Signed-off-by: Frank Chang --- target/riscv/vector_helper.c | 52 1 file changed, 29 insertions(+), 23 deletions(-) diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c index 8d251dee58..11c962431e 100644 --- a/target

[RFC 47/65] target/riscv: rvv-0.9: floating-point slide instructions

From: Frank Chang Add the following instructions: * vfslide1up.vf * vfslide1down.vf Signed-off-by: Frank Chang --- target/riscv/helper.h | 7 target/riscv/insn32.decode | 2 + target/riscv/insn_trans/trans_rvv.inc.c | 4 ++ target/riscv/vector_helper.c

[RFC 64/65] target/riscv: use softfloat lib float16 comparison functions

From: Frank Chang Signed-off-by: Frank Chang --- target/riscv/vector_helper.c | 19 --- 1 file changed, 19 deletions(-) diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c index aac055c6b6..c206b50182 100644 --- a/target/riscv/vector_helper.c +++ b/target

[RFC 48/65] target/riscv: rvv-0.9: narrowing fixed-point clip instructions

From: Frank Chang Signed-off-by: Frank Chang --- target/riscv/helper.h | 24 ++-- target/riscv/insn32.decode | 12 +++--- target/riscv/insn_trans/trans_rvv.inc.c | 12 +++--- target/riscv/vector_helper.c| 52 - 4 files

[RFC 49/65] target/riscv: rvv-0.9: floating-point move instructions

From: Frank Chang Signed-off-by: Frank Chang --- target/riscv/insn_trans/trans_rvv.inc.c | 57 - 1 file changed, 28 insertions(+), 29 deletions(-) diff --git a/target/riscv/insn_trans/trans_rvv.inc.c b/target/riscv/insn_trans/trans_rvv.inc.c index 986f62dabc

Re: [RFC 60/65] softfloat: add fp16 and uint8/int8 interconvert functions

On Fri, Jul 10, 2020 at 8:46 PM Alex Bennée wrote: > > Frank Chang writes: > > > On Fri, Jul 10, 2020 at 8:07 PM Alex Bennée > wrote: > > > >> > >> frank.ch...@sifive.com writes: > >> > >> > From: Frank Chang > >> &

[RFC 55/65] target/riscv: rvv-0.9: remove vmford.vv and vmford.vf

From: Frank Chang Signed-off-by: Frank Chang --- target/riscv/helper.h | 6 -- target/riscv/insn32.decode | 2 -- target/riscv/insn_trans/trans_rvv.inc.c | 2 -- target/riscv/vector_helper.c| 13 - 4 files changed, 23 deletions

[RFC 61/65] fpu: fix float16 nan check

From: Chih-Min Chao 16 15 10 0 |sign | exp | mantissa | qNaN x 1 1x__ The mask should check exp + msb of mantissa Signed-off-by: Chih-Min Chao Signed-off-by: Frank Chang --- fpu/softfloat-specialize.inc.c | 4 ++-- 1 file changed

Re: [RFC 60/65] softfloat: add fp16 and uint8/int8 interconvert functions

On Fri, Jul 10, 2020 at 8:07 PM Alex Bennée wrote: > > frank.ch...@sifive.com writes: > > > From: Frank Chang > > > > Signed-off-by: Frank Chang > > Did I miss the rest of the series somewhere? > > Otherwise this looks fine to me: > > Reviewed-by:

Re: [RFC 00/65] target/riscv: support vector extension v0.9

On Sat, Jul 11, 2020 at 5:53 AM Alistair Francis wrote: > On Fri, Jul 10, 2020 at 5:59 AM wrote: > > > > From: Frank Chang > > > > This patchset implements the vector extension v0.9 for RISC-V on QEMU. > > > > This patchset is sent as RFC because RVV v0

Re: [RFC 14/65] target/riscv: rvv-0.9: stride load and store instructions

ince 0.7.1 will help the reviewer validate that you've gotten all of > the > corner cases. > > I am going to stop reviewing this patch series now, as I expect that most > of > the remaining patches will have similar comments. > > > r~ > Thanks for the reviews. I will rearrange my commits as what you suggest and add more comments in my next patchset. -- Frank Chang

Re: [RFC 13/65] target/riscv: rvv-0.9: configure instructions

> Do not mix this change with anything else. OK~ --- Frank Chang > > +rd = tcg_const_i32(a->rd); > > +rs1 = tcg_const_i32(a->rs1); > > Any time you put a register number into a tcg const, there's probably a > better > way to do things. > > -

Re: [RFC 12/65] target/riscv: rvv-0.9: update check functions

eg(s, a->rs2, false) && > > -vext_check_reg(s, a->rs1, false)); > > with invisible returns > > > +REQUIRE_RVV; > > +VEXT_CHECK_ISA_ILL(s); > > + VEXT_CHECK_SSS(s, a->rd, a->rs1, a->rs2, a->vm, true); > > +return true; > > > r~ > You're right, I will resend the patches with more description and justification. Frank Chang

Re: [RFC 00/65] target/riscv: support vector extension v0.9

On Tue, Jul 14, 2020 at 12:41 AM Richard Henderson < richard.hender...@linaro.org> wrote: > On 7/12/20 7:02 PM, Frank Chang wrote: > > Does decodetree support any feature for multi-version opcodes? > > Or if it can use something like C macros to compile with the opcodes by

Re: [RFC 05/65] target/riscv: remove vsll.vi, vsrl.vi, vsra.vi insns from using gvec

On Sat, Jul 11, 2020 at 12:27 AM Richard Henderson < richard.hender...@linaro.org> wrote: > On 7/10/20 3:48 AM, frank.ch...@sifive.com wrote: > > From: Frank Chang > > > > vsll.vi, vsrl.vi, vsra.vi cannot use shli gvec as it requires the > > shift immediate value

Re: [RFC 05/65] target/riscv: remove vsll.vi, vsrl.vi, vsra.vi insns from using gvec

On Tue, Jul 14, 2020 at 11:35 AM LIU Zhiwei wrote: > > > On 2020/7/14 10:59, Frank Chang wrote: > > On Sat, Jul 11, 2020 at 12:27 AM Richard Henderson < > richard.hender...@linaro.org> wrote: > >> On 7/10/20 3:48 AM, frank.ch...@sifive.com wrote: >>

Re: [RFC 05/65] target/riscv: remove vsll.vi, vsrl.vi, vsra.vi insns from using gvec

On Tue, Jul 14, 2020 at 9:21 PM Richard Henderson < richard.hender...@linaro.org> wrote: > On 7/13/20 7:59 PM, Frank Chang wrote: > > The latest spec specified: > > > > Only the low *lg2(SEW) bits* are read to obtain the shift amount from a > > *register value*.

[RFC v2 00/76] target/riscv: support vector extension v0.9

From: Frank Chang This patchset implements the vector extension v0.9 for RISC-V on QEMU. This patchset is sent as RFC because RVV v0.9 is still in draft state. However, as RVV v1.0 should be ratified soon and there shouldn't be critical changes between RVV v1.0 and RVV v0.9. We would li

[RFC v2 02/76] target/riscv: rvv-0.9: support vector 0.9

From: Frank Chang Signed-off-by: Frank Chang --- target/riscv/cpu.c | 24 ++-- target/riscv/cpu.h | 2 ++ 2 files changed, 20 insertions(+), 6 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 2800953e6c..641c803089 100644 --- a/target/riscv/cpu.c

[RFC v2 01/76] target/riscv: drop vector 0.7.1 support

From: Frank Chang Signed-off-by: Frank Chang --- target/riscv/cpu.c | 24 ++-- target/riscv/cpu.h | 2 -- 2 files changed, 6 insertions(+), 20 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 228b9bdb5d..2800953e6c 100644 --- a/target/riscv/cpu.c

[RFC v2 07/76] target/riscv: Use FIELD_EX32() to extract wd field

From: Frank Chang Signed-off-by: Frank Chang --- target/riscv/vector_helper.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c index 39f44d1029..4c0a6198e7 100644 --- a/target/riscv/vector_helper.c +++ b/target

[RFC v2 03/76] target/riscv: fix rsub gvec tcg_assert_listed_vecop assertion

From: Frank Chang gvec should provide vecop_list to avoid: "tcg_tcg_assert_listed_vecop: code should not be reached bug" assertion. Signed-off-by: Frank Chang --- target/riscv/insn_trans/trans_rvv.inc.c | 5 + 1 file changed, 5 insertions(+) diff --git a/target/riscv/

[RFC v2 04/76] target/riscv: correct the gvec IR called in gen_vec_rsub16_i64()

From: Frank Chang Signed-off-by: Frank Chang --- target/riscv/insn_trans/trans_rvv.inc.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/riscv/insn_trans/trans_rvv.inc.c b/target/riscv/insn_trans/trans_rvv.inc.c index 433cdacbe1..7cd08f0868 100644 --- a/target/riscv

[RFC v2 09/76] target/riscv: rvv-0.9: add sstatus VS field

From: LIU Zhiwei Signed-off-by: LIU Zhiwei Signed-off-by: Frank Chang --- target/riscv/cpu_bits.h | 1 + target/riscv/csr.c | 2 +- 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index a8b3120883..5b0be0bb88 100644 --- a

[RFC v2 08/76] target/riscv: rvv-0.9: add mstatus VS field

From: LIU Zhiwei Signed-off-by: LIU Zhiwei Signed-off-by: Frank Chang --- target/riscv/cpu.h| 6 ++ target/riscv/cpu_bits.h | 1 + target/riscv/cpu_helper.c | 16 +++- target/riscv/csr.c| 25 - 4 files changed, 46 insertions(+), 2

[RFC v2 06/76] target/riscv: fix vill bit index in vtype register

From: Frank Chang vill bit is at vtype[XLEN-1]. Signed-off-by: Frank Chang --- target/riscv/cpu.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 378f6e82bf..27ce075e50 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h

[RFC v2 05/76] target/riscv: fix return value of do_opivx_widen()

From: Frank Chang do_opivx_widen() should return false if check function returns false. Signed-off-by: Frank Chang --- target/riscv/insn_trans/trans_rvv.inc.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/riscv/insn_trans/trans_rvv.inc.c b/target/riscv/insn_trans

[RFC v2 10/76] target/riscv: rvv-0.9: add translation-time vector context status

From: LIU Zhiwei Signed-off-by: LIU Zhiwei Signed-off-by: Frank Chang --- target/riscv/insn_trans/trans_rvv.inc.c | 69 - target/riscv/translate.c| 33 2 files changed, 90 insertions(+), 12 deletions(-) diff --git a/target/riscv/insn_trans

[RFC v2 13/76] target/riscv: rvv-0.9: add vlenb register

From: Greentime Hu Signed-off-by: Greentime Hu Signed-off-by: Frank Chang --- target/riscv/cpu_bits.h | 1 + target/riscv/csr.c | 7 +++ 2 files changed, 8 insertions(+) diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index 7afdd4814b..fe055b67a6 100644 --- a/target

[RFC v2 15/76] target/riscv: rvv-0.9: add fractional LMUL

From: Frank Chang Introduce the concepts of fractional LMUL, EEW and EMUL for RVV 0.9. Signed-off-by: Frank Chang --- target/riscv/cpu.h | 16 ++-- target/riscv/insn_trans/trans_rvv.inc.c | 17 ++--- target/riscv/internals.h| 11

[RFC v2 11/76] target/riscv: rvv-0.9: remove vxrm and vxsat fields from fcsr register

From: Frank Chang Remove VXRM and VXSAT fields from FCSR register as they are only presented in VCSR register. Signed-off-by: Frank Chang --- target/riscv/csr.c | 8 1 file changed, 8 deletions(-) diff --git a/target/riscv/csr.c b/target/riscv/csr.c index ab4a4fc132..33c77be06e

[RFC v2 17/76] target/riscv: rvv-0.9: update check functions

From: Frank Chang Update check functions with RVV 0.9 rules. Signed-off-by: Frank Chang --- target/riscv/insn_trans/trans_rvv.inc.c | 706 1 file changed, 474 insertions(+), 232 deletions(-) diff --git a/target/riscv/insn_trans/trans_rvv.inc.c b/target/riscv

[RFC v2 14/76] target/riscv: rvv-0.9: remove MLEN calculations

From: Frank Chang As in RVV 0.9 design, MLEN is hardcoded with value 1 (Section 4.5). Thus, remove all MLEN related calculations. Signed-off-by: Frank Chang --- target/riscv/insn_trans/trans_rvv.inc.c | 35 +--- target/riscv/internals.h| 9 +- target/riscv/translate.c

[RFC v2 12/76] target/riscv: rvv-0.9: add vcsr register

From: LIU Zhiwei Signed-off-by: LIU Zhiwei Signed-off-by: Frank Chang --- target/riscv/cpu_bits.h | 7 +++ target/riscv/csr.c | 21 + 2 files changed, 28 insertions(+) diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index 5b0be0bb88..7afdd4814b

[RFC v2 18/76] target/riscv: introduce more imm value modes in translator functions

From: Frank Chang Immediate value in translator function is extended not only zero-extended and sign-extended but with more modes to be applicable with multiple formats of vector instructions. * IMM_ZX: Zero-extended * IMM_SX: Sign-extended * IMM_TRUNC_SEW: Truncate to log(SEW

[RFC v2 38/76] target/riscv: rvv-0.9: register gather instructions

From: Frank Chang Signed-off-by: Frank Chang --- target/riscv/insn_trans/trans_rvv.inc.c | 7 --- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/target/riscv/insn_trans/trans_rvv.inc.c b/target/riscv/insn_trans/trans_rvv.inc.c index 6b4b7f6574..af19561e7d 100644 --- a

[RFC v2 19/76] target/riscv: rvv-0.9: add narrower_nanbox_fpr helper

From: Frank Chang For floating-point operations, the scalar can be taken from a scalar f register. If FLEN > SEW, the value in the f registers is checked for a valid NaN-boxed value, in which case the least-significant SEW bits of the f register are used, else the canonical NaN value is u

[RFC v2 16/76] target/riscv: rvv-0.9: add VMA and VTA

From: Frank Chang Introduce the concepts of VMA and VTA for RVV 0.9. Signed-off-by: Frank Chang --- target/riscv/cpu.h | 11 +- target/riscv/insn_trans/trans_rvv.inc.c | 62 + target/riscv/internals.h| 6 +- target/riscv/translate.c

[RFC v2 20/76] target/riscv: rvv-0.9: apply narrower nanbox helper in opfvf_trans

From: Frank Chang If SEW < FLEN, call narrower_nanbox_fpr helper to generate the correspond NaN-boxed value. Signed-off-by: Frank Chang --- target/riscv/insn_trans/trans_rvv.inc.c | 13 - 1 file changed, 12 insertions(+), 1 deletion(-) diff --git a/target/riscv/insn_tr

[RFC v2 39/76] target/riscv: rvv-0.9: integer scalar move instructions

From: Frank Chang * Remove "vmv.s.x: dothing if rs1 == 0" constraint. * Add vmv.x.s instruction. Signed-off-by: Frank Chang --- target/riscv/insn32.decode | 3 +- target/riscv/insn_trans/trans_rvv.inc.c | 46 - 2 files changed, 40 insert

[RFC v2 25/76] target/riscv: rvv-0.9: fault-only-first unit stride load

From: Frank Chang Signed-off-by: Frank Chang --- target/riscv/helper.h | 27 +++- target/riscv/insn32.decode | 14 +++ target/riscv/insn_trans/trans_rvv.inc.c | 31 -- target/riscv/vector_helper.c| 56

[RFC v2 21/76] target/riscv: rvv-0.9: configure instructions

From: Frank Chang Signed-off-by: Frank Chang --- target/riscv/insn_trans/trans_rvv.inc.c | 12 target/riscv/vector_helper.c| 10 +- 2 files changed, 17 insertions(+), 5 deletions(-) diff --git a/target/riscv/insn_trans/trans_rvv.inc.c b/target/riscv

[RFC v2 40/76] target/riscv: rvv-0.9: floating-point move instruction

From: Frank Chang NaN-boxed the scalar floating-point register based on RVV 0.9's rules. Signed-off-by: Frank Chang --- target/riscv/insn_trans/trans_rvv.inc.c | 16 +++- 1 file changed, 15 insertions(+), 1 deletion(-) diff --git a/target/riscv/insn_trans/trans_rvv.inc

[RFC v2 27/76] target/riscv: rvv-0.9: load/store whole register instructions

From: Frank Chang Add the following instructions: * vl1r.v * vs1r.v Signed-off-by: Frank Chang --- target/riscv/helper.h | 3 ++ target/riscv/insn32.decode | 4 ++ target/riscv/insn_trans/trans_rvv.inc.c | 61 + target/riscv

[RFC v2 22/76] target/riscv: rvv-0.9: stride load and store instructions

From: Frank Chang Signed-off-by: Frank Chang --- target/riscv/helper.h | 129 +++--- target/riscv/insn32.decode | 43 +++-- target/riscv/insn_trans/trans_rvv.inc.c | 214 +++- target/riscv/vector_helper.c| 175

[RFC v2 24/76] target/riscv: rvv-0.9: fix address index overflow bug of indexed load/store insns

From: Frank Chang Replace ETYPE from signed int to unsigned int to prevent index overflow issue, which would lead to wrong index address. Signed-off-by: Frank Chang --- target/riscv/vector_helper.c | 8 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/target/riscv

[RFC v2 28/76] target/riscv: rvv-0.9: update vext_max_elems() for load/store insns

From: Frank Chang Unlike other vector instructions, load/store vector instructions return the maximum vector size calculated with EMUL. For other vector instructions, return VLMAX as the maximum vector size. Signed-off-by: Frank Chang --- target/riscv/vector_helper.c | 118

[RFC v2 23/76] target/riscv: rvv-0.9: index load and store instructions

From: Frank Chang Signed-off-by: Frank Chang --- target/riscv/helper.h | 67 + target/riscv/insn32.decode | 21 ++- target/riscv/insn_trans/trans_rvv.inc.c | 177 +--- target/riscv/vector_helper.c| 84 ++- 4

[RFC v2 48/76] target/riscv: rvv-0.9: widening integer multiply-add instructions

From: Frank Chang Signed-off-by: Frank Chang --- target/riscv/insn32.decode | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index bc6c788edf..c6a7145aa5 100644 --- a/target/riscv/insn32.decode +++ b/target/riscv

[RFC v2 31/76] target/riscv: rvv-0.9: floating-point classify instructions

From: Frank Chang Signed-off-by: Frank Chang --- target/riscv/insn32.decode | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index 1d34fa647b..7ad936e605 100644 --- a/target/riscv/insn32.decode +++ b/target/riscv/insn32

[RFC v2 29/76] target/riscv: rvv-0.9: take fractional LMUL into vector max elements calculation

From: Frank Chang Update vext_get_vlmax() and MAXSZ() to take fractional LMUL into calculation for RVV 0.9. Signed-off-by: Frank Chang --- target/riscv/cpu.h | 32 +++-- target/riscv/insn_trans/trans_rvv.inc.c | 11 - 2 files changed, 29

[RFC v2 32/76] target/riscv: rvv-0.9: mask population count instruction

From: Frank Chang Signed-off-by: Frank Chang --- target/riscv/helper.h | 2 +- target/riscv/insn32.decode | 2 +- target/riscv/insn_trans/trans_rvv.inc.c | 7 --- target/riscv/vector_helper.c| 6 +++--- 4 files changed, 9 insertions(+), 8

[RFC v2 50/76] target/riscv: rvv-0.9: single-width saturating add and subtract instructions

From: Frank Chang Sign-extend vsaddu.vi immediate value. Signed-off-by: Frank Chang --- target/riscv/insn_trans/trans_rvv.inc.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/riscv/insn_trans/trans_rvv.inc.c b/target/riscv/insn_trans/trans_rvv.inc.c index

[RFC v2 34/76] target/riscv: rvv-0.9: set-X-first mask bit instructions

From: Frank Chang Signed-off-by: Frank Chang --- target/riscv/insn32.decode | 6 +++--- target/riscv/insn_trans/trans_rvv.inc.c | 5 - target/riscv/vector_helper.c| 4 3 files changed, 7 insertions(+), 8 deletions(-) diff --git a/target/riscv/insn32.decode b

[RFC v2 33/76] target/riscv: rvv-0.9: find-first-set mask bit instruction

From: Frank Chang Signed-off-by: Frank Chang --- target/riscv/helper.h | 2 +- target/riscv/insn32.decode | 2 +- target/riscv/insn_trans/trans_rvv.inc.c | 4 ++-- target/riscv/vector_helper.c| 6 +++--- 4 files changed, 7 insertions(+), 7 deletions

[RFC v2 26/76] target/riscv: rvv-0.9: amo operations

From: Frank Chang Signed-off-by: Frank Chang --- target/riscv/helper.h | 100 --- target/riscv/insn32-64.decode | 18 +- target/riscv/insn32.decode | 36 +++- target/riscv/insn_trans/trans_rvv.inc.c | 212 +++--- target/riscv

[RFC v2 30/76] target/riscv: rvv-0.9: floating-point square-root instruction

From: Frank Chang Signed-off-by: Frank Chang --- target/riscv/insn32.decode | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index e3f0fba912..1d34fa647b 100644 --- a/target/riscv/insn32.decode +++ b/target/riscv/insn32

[RFC v2 36/76] target/riscv: rvv-0.9: element index instruction

From: Frank Chang Signed-off-by: Frank Chang --- target/riscv/insn32.decode | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index 4560bc4379..01316c908d 100644 --- a/target/riscv/insn32.decode +++ b/target/riscv/insn32

[RFC v2 55/76] target/riscv: rvv-0.9: single-width integer reduction instructions

From: Frank Chang Remove clear function from helper function as the tail elements are unchanged in RVV 0.9. Signed-off-by: Frank Chang --- target/riscv/vector_helper.c | 69 +--- 1 file changed, 33 insertions(+), 36 deletions(-) diff --git a/target/riscv

[RFC v2 37/76] target/riscv: rvv-0.9: allow load element with sign-extended

From: Frank Chang For some vector instructions (e.g. vmv.s.x), the element is loaded with sign-extended. Signed-off-by: Frank Chang --- target/riscv/insn_trans/trans_rvv.inc.c | 26 ++--- 1 file changed, 19 insertions(+), 7 deletions(-) diff --git a/target/riscv

[RFC v2 56/76] target/riscv: rvv-0.9: widening integer reduction instructions

From: Frank Chang Remove clear function from helper function as the tail elements are unchanged in RVV 0.9. Signed-off-by: Frank Chang --- target/riscv/vector_helper.c | 12 ++-- 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/target/riscv/vector_helper.c b/target/riscv

[RFC v2 42/76] target/riscv: rvv-0.9: whole register move instructions

From: Frank Chang Add the following instructions: * vmv1r.v * vmv2r.v * vmv4r.v * vmv8r.v Signed-off-by: Frank Chang --- target/riscv/insn32.decode | 4 target/riscv/insn_trans/trans_rvv.inc.c | 27 + 2 files changed, 31 insertions(+) diff --git a

[RFC v2 43/76] target/riscv: rvv-0.9: integer extension instructions

From: Frank Chang Add the following instructions: * vzext.vf2 * vzext.vf4 * vzext.vf8 * vsext.vf2 * vsext.vf4 * vsext.vf8 Signed-off-by: Frank Chang --- target/riscv/helper.h | 14 target/riscv/insn32.decode | 8 +++ target/riscv/insn_trans

[RFC v2 35/76] target/riscv: rvv-0.9: iota instruction

From: Frank Chang Signed-off-by: Frank Chang --- target/riscv/insn32.decode | 2 +- target/riscv/vector_helper.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index 37b2582981..4560bc4379 100644 --- a/target

[RFC v2 52/76] fpu: implement full set compare for fp16

From: Kito Cheng Signed-off-by: Kito Cheng Signed-off-by: Chih-Min Chao Signed-off-by: Frank Chang --- fpu/softfloat.c | 28 include/fpu/softfloat.h | 41 + 2 files changed, 69 insertions(+) diff --git a/fpu

[RFC v2 62/76] target/riscv: rvv-0.9: single-width floating-point reduction

From: Frank Chang Separate the implementation of vfredsum.vs and vfredosum.vs. Introduce propagate NaN feature for vfredsum.vs as implementations are permitted to canonicalize the NaN and, if the NaN is signaling, set the invalid exception flag. Signed-off-by: Frank Chang --- target/riscv

[RFC v2 41/76] target/riscv: rvv-0.9: floating-point scalar move instructions

From: Frank Chang NaN-boxed the scalar floating-point register based on RVV 0.9's rules. Signed-off-by: Frank Chang --- target/riscv/insn32.decode | 4 +-- target/riscv/insn_trans/trans_rvv.inc.c | 45 - 2 files changed, 31 insertions(+), 18 dele

[RFC v2 54/76] target/riscv: rvv-0.9: floating-point compare instructions

From: Frank Chang Clear tail elements only if VTA is agnostic. Signed-off-by: Frank Chang --- target/riscv/vector_helper.c | 52 1 file changed, 29 insertions(+), 23 deletions(-) diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c

[RFC v2 44/76] target/riscv: rvv-0.9: single-width averaging add and subtract instructions

From: Frank Chang Add the following instructions: * vaaddu.vv * vaaddu.vx * vasubu.vv * vasubu.vx Remove the following instructions: * vadd.vi Signed-off-by: Frank Chang --- target/riscv/helper.h | 16 ++ target/riscv/insn32.decode | 13 +++-- target

[RFC v2 68/76] fpu: add api to handle alternative sNaN propagation

;& ft2 == sNaN The ieee754 spec allows both implementation and some architecture such as riscv choose differenct defintion in two spec versions. (riscv-spec-v2.2 use original one, riscv-spec-20191213 changes to alternative one) Signed-off-by: Chih-Min Chao Signed-off-by: Fra

[RFC v2 57/76] target/riscv: rvv-0.9: mask-register logical instructions

From: Frank Chang Clear tail elements only if VTA is agnostic. Signed-off-by: Frank Chang --- target/riscv/insn_trans/trans_rvv.inc.c | 3 ++- target/riscv/vector_helper.c| 7 +-- 2 files changed, 7 insertions(+), 3 deletions(-) diff --git a/target/riscv/insn_trans

[RFC v2 63/76] target/riscv: rvv-0.9: widening floating-point reduction instructions

From: Frank Chang Separate the implementation of vfwredsum.vs and vfwredosum.vs. Introduce propagate NaN feature for vfwredsum.vs as implementations are permitted to canonicalize the NaN and, if the NaN is signaling, set the invalid exception flag. Signed-off-by: Frank Chang --- target/riscv

[RFC v2 58/76] target/riscv: rvv-0.9: slide instructions

From: Frank Chang * Fix offset overflow issue. * Remove clear function from helper functions as the tail elements are unchanged in RVV 0.9. Signed-off-by: Frank Chang --- target/riscv/vector_helper.c | 83 1 file changed, 37 insertions(+), 46 deletions

[RFC v2 70/76] softfloat: add fp16 and uint8/int8 interconvert functions

From: Frank Chang Signed-off-by: Frank Chang Reviewed-by: Alex Bennée --- fpu/softfloat.c | 34 ++ include/fpu/softfloat.h | 8 2 files changed, 42 insertions(+) diff --git a/fpu/softfloat.c b/fpu/softfloat.c index e1661f22a5..89634267db

[RFC v2 45/76] target/riscv: rvv-0.9: single-width bit shift instructions

From: Frank Chang Truncate vsll.vi, vsrl.vi, vsra.vi's immediate values to lg2(SEW) bits. Signed-off-by: Frank Chang --- target/riscv/insn_trans/trans_rvv.inc.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/target/riscv/insn_trans/trans_rvv.inc.c b/target/

[RFC v2 46/76] target/riscv: rvv-0.9: integer add-with-carry/subtract-with-borrow

From: Frank Chang Clear tail elements only if VTA is agnostic. Signed-off-by: Frank Chang --- target/riscv/insn32.decode | 20 +- target/riscv/insn_trans/trans_rvv.inc.c | 2 +- target/riscv/vector_helper.c| 50 ++--- 3 files changed, 40

[RFC v2 69/76] target/riscv: rvv-0.9: floating-point min/max instructions

From: Frank Chang Signed-off-by: Frank Chang --- target/riscv/vector_helper.c | 24 1 file changed, 12 insertions(+), 12 deletions(-) diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c index 49e6a91859..4c6755db97 100644 --- a/target/riscv

[RFC v2 76/76] target/riscv: gdb: support vector registers for rv32

From: Greentime Hu This patch adds vector support for rv32 gdb. It allows gdb client to access vector registers correctly. Signed-off-by: Greentime Hu Signed-off-by: Frank Chang --- configure | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/configure b/configure index

[RFC v2 61/76] target/riscv: rvv-0.9: floating-point/integer type-convert instructions

From: Frank Chang Add the following instructions: * vfcvt.rtz.xu.f.v * vfcvt.rtz.x.f.v Signed-off-by: Frank Chang --- target/riscv/helper.h | 6 target/riscv/insn32.decode | 11 --- target/riscv/insn_trans/trans_rvv.inc.c | 2 ++ target/riscv

[RFC v2 47/76] target/riscv: rvv-0.9: narrowing integer right shift instructions

From: Frank Chang Signed-off-by: Frank Chang --- target/riscv/helper.h | 24 ++-- target/riscv/insn32.decode | 12 +- target/riscv/insn_trans/trans_rvv.inc.c | 30 - target/riscv/vector_helper.c| 24

[RFC v2 72/76] target/riscv: rvv-0.9: narrowing floating-point/integer type-convert

From: Frank Chang Signed-off-by: Frank Chang --- target/riscv/helper.h | 30 +--- target/riscv/insn32.decode | 15 ++-- target/riscv/insn_trans/trans_rvv.inc.c | 50 +++-- target/riscv/vector_helper.c| 99 - 4 files

[RFC v2 64/76] target/riscv: rvv-0.9: single-width scaling shift instructions

From: Frank Chang Zero-extend vssra.vi immediate value. Signed-off-by: Frank Chang --- target/riscv/insn_trans/trans_rvv.inc.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/riscv/insn_trans/trans_rvv.inc.c b/target/riscv/insn_trans/trans_rvv.inc.c index

[RFC v2 49/76] target/riscv: rvv-0.9: quad-widening integer multiply-add instructions

From: Frank Chang Add the following instructions: * vqmaccu.vv * vqmaccu.vx * vqmacc.vv * vqmacc.vx * vqmaccsu.vv * vqmaccsu.vx * vqmaccus.vx Signed-off-by: Frank Chang --- target/riscv/helper.h | 15 target/riscv/insn32.decode | 7 ++ target/riscv

[RFC v2 65/76] target/riscv: rvv-0.9: remove widening saturating scaled multiply-add

From: Frank Chang Signed-off-by: Frank Chang --- target/riscv/helper.h | 22 --- target/riscv/insn32.decode | 7 - target/riscv/insn_trans/trans_rvv.inc.c | 9 -- target/riscv/vector_helper.c| 205 4 files changed, 243

[RFC v2 51/76] target/riscv: rvv-0.9: integer comparison instructions

From: Frank Chang Sign-extend vmselu.vi and vmsgtu.vi immediate values. Signed-off-by: Frank Chang --- target/riscv/insn_trans/trans_rvv.inc.c | 4 +- target/riscv/vector_helper.c| 86 + 2 files changed, 48 insertions(+), 42 deletions(-) diff --git a

[RFC v2 67/76] target/riscv: rvv-0.9: remove integer extract instruction

From: Frank Chang Signed-off-by: Frank Chang --- target/riscv/insn32.decode | 1 - target/riscv/insn_trans/trans_rvv.inc.c | 23 --- 2 files changed, 24 deletions(-) diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index 47337abe52

[RFC v2 53/76] target/riscv: use softfloat lib float16 comparison functions

From: Frank Chang Signed-off-by: Frank Chang --- target/riscv/vector_helper.c | 19 --- 1 file changed, 19 deletions(-) diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c index dc883e0352..95cce063d0 100644 --- a/target/riscv/vector_helper.c +++ b/target

[RFC v2 59/76] target/riscv: rvv-0.9: floating-point slide instructions

From: Frank Chang Add the following instructions: * vfslide1up.vf * vfslide1down.vf Signed-off-by: Frank Chang --- target/riscv/helper.h | 7 target/riscv/insn32.decode | 2 + target/riscv/insn_trans/trans_rvv.inc.c | 4 ++ target/riscv/vector_helper.c

[RFC v2 71/76] target/riscv: rvv-0.9: widening floating-point/integer type-convert

From: Frank Chang Signed-off-by: Frank Chang --- target/riscv/helper.h | 6 target/riscv/insn32.decode | 13 +--- target/riscv/insn_trans/trans_rvv.inc.c | 43 +++-- target/riscv/vector_helper.c| 29 - 4

[RFC v2 74/76] target/riscv: gdb: modify gdb csr xml file to align with csr register map

From: Hsiangkai Wang Signed-off-by: Hsiangkai Wang Signed-off-by: Frank Chang --- gdb-xml/riscv-32bit-csr.xml | 11 ++- gdb-xml/riscv-64bit-csr.xml | 11 ++- target/riscv/gdbstub.c | 4 ++-- 3 files changed, 14 insertions(+), 12 deletions(-) diff --git a/gdb-xml/riscv

[RFC v2 60/76] target/riscv: rvv-0.9: narrowing fixed-point clip instructions

From: Frank Chang Signed-off-by: Frank Chang --- target/riscv/helper.h | 24 ++-- target/riscv/insn32.decode | 12 +++--- target/riscv/insn_trans/trans_rvv.inc.c | 12 +++--- target/riscv/vector_helper.c| 52 - 4 files

[RFC v2 66/76] target/riscv: rvv-0.9: remove vmford.vv and vmford.vf

From: Frank Chang Signed-off-by: Frank Chang --- target/riscv/helper.h | 6 -- target/riscv/insn32.decode | 2 -- target/riscv/insn_trans/trans_rvv.inc.c | 2 -- target/riscv/vector_helper.c| 13 - 4 files changed, 23 deletions

[RFC v2 73/76] fpu: fix float16 nan check

From: Chih-Min Chao 16 15 10 0 |sign | exp | mantissa | qNaN x 1 1x__ The mask should check exp + msb of mantissa Signed-off-by: Chih-Min Chao Signed-off-by: Frank Chang --- fpu/softfloat-specialize.inc.c | 4 ++-- 1 file changed

[RFC v2 75/76] target/riscv: gdb: support vector registers for rv64

From: Hsiangkai Wang Signed-off-by: Hsiangkai Wang Signed-off-by: Frank Chang --- configure | 2 +- gdb-xml/riscv-64bit-csr.xml | 7 gdb-xml/riscv-64bit-vector-128b.xml | 59 +++ gdb-xml/riscv-64bit-vector-256b.xml | 59

Re: [RFC v2 15/76] target/riscv: rvv-0.9: add fractional LMUL

able. > desc only saves the raw LMUL bits. (total 3 bits, I've packed the fractional LMUL bit together with two other LMUL bits in cpu_get_tb_cpu_state()) The helper here is to convert the 3-bits LMUL into the actual fractional number it represents. > r~ > Frank Chang

Re: [RFC v2 16/76] target/riscv: rvv-0.9: add VMA and VTA

e don't have to pass the values in > translate either. > > Which is exactly what is recommended in the 4th paragraph of the notes > following the VTA/VMA description. > > I was trying to keep these codes as an option for the user to specify the behaviors of VTA. But as long as it's easier for QEMU to just treat VTA/VMA as agnostic(no changes)/undisturbed. I will remove all the clean functions in my next patchset. > > r~ > Frank Chang

Re: [RFC v2 19/76] target/riscv: rvv-0.9: add narrower_nanbox_fpr helper

On Thu, Jul 23, 2020 at 3:15 AM Richard Henderson < richard.hender...@linaro.org> wrote: > On 7/22/20 2:15 AM, frank.ch...@sifive.com wrote: > > From: Frank Chang > > > > For floating-point operations, the scalar can be taken from a scalar > > f register.

Re: [RFC v2 01/76] target/riscv: drop vector 0.7.1 support

On Tue, Jul 28, 2020 at 4:05 AM Alistair Francis wrote: > On Mon, Jul 27, 2020 at 12:54 PM Palmer Dabbelt > wrote: > > > > On Wed, 22 Jul 2020 02:15:24 PDT (-0700), frank.ch...@sifive.com wrote: > > > From: Frank Chang > > > > > > Signed-off-by: Fra

Re: [RFC v2 43/76] target/riscv: rvv-0.9: integer extension instructions

ns in this table. As far > as I > can see, the only NULLs should be at [*][0]. > > > r~ > As source EEW has to be 1/2, 1/4, 1/8 of SEW and the source EEW must be a supported width (Section 12.3). Shouldn't it impossible to have the cases, e.g. vzext.vf4 with SEW = 16, i.e. EEW = SEW / 4 = 4 bits vzext.vf8 with SEW = 16, i.e. EEW = SEW / 8 = 2 bits vzext.vf8 with SEW = 32, i.e. EEW = SEW / 8 = 4 bits Frank Chang

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