[PATCH v11 52/77] target/riscv: rvv-1.0: narrowing fixed-point clip instructions

From: Frank Chang Signed-off-by: Frank Chang Reviewed-by: Richard Henderson --- target/riscv/helper.h | 24 ++-- target/riscv/insn32.decode | 12 +++--- target/riscv/insn_trans/trans_rvv.c.inc | 12 +++--- target/riscv/vector_helper.c| 52

[PATCH v11 43/77] target/riscv: rvv-1.0: integer add-with-carry/subtract-with-borrow

From: Frank Chang * Only do carry-in or borrow-in if is masked (vm=0). * Remove clear function from helper functions as the tail elements are unchanged in RVV 1.0. Signed-off-by: Frank Chang Reviewed-by: Alistair Francis --- target/riscv/insn32.decode | 20

[PATCH v11 59/77] target/riscv: rvv-1.0: floating-point min/max instructions

From: Frank Chang Signed-off-by: Frank Chang Reviewed-by: Richard Henderson --- target/riscv/vector_helper.c | 24 1 file changed, 12 insertions(+), 12 deletions(-) diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c index aed230e1ad..cc95b69255

[PATCH v11 60/77] target/riscv: introduce floating-point rounding mode enum

From: Frank Chang Signed-off-by: Frank Chang Reviewed-by: Richard Henderson --- target/riscv/fpu_helper.c | 12 ++-- target/riscv/insn_trans/trans_rvv.c.inc | 18 +- target/riscv/internals.h| 9 + 3 files changed, 24 insertions

[PATCH v11 53/77] target/riscv: rvv-1.0: single-width floating-point reduction

From: Frank Chang Signed-off-by: Frank Chang Reviewed-by: Richard Henderson --- target/riscv/insn_trans/trans_rvv.c.inc | 12 +--- target/riscv/vector_helper.c| 12 ++-- 2 files changed, 15 insertions(+), 9 deletions(-) diff --git a/target/riscv/insn_trans

[PATCH v11 61/77] target/riscv: rvv-1.0: floating-point/integer type-convert instructions

From: Frank Chang Add the following instructions: * vfcvt.rtz.xu.f.v * vfcvt.rtz.x.f.v Also adjust GEN_OPFV_TRANS() to accept multiple floating-point rounding modes. Signed-off-by: Frank Chang Reviewed-by: Alistair Francis --- target/riscv/insn32.decode | 11 ++-- target/riscv

[PATCH v11 65/77] target/riscv: rvv-1.0: relax RV_VLEN_MAX to 1024-bits

From: Frank Chang Signed-off-by: Frank Chang Reviewed-by: Alistair Francis --- target/riscv/cpu.h | 2 +- target/riscv/insn_trans/trans_rvv.c.inc | 4 ++-- target/riscv/vector_helper.c| 2 +- 3 files changed, 4 insertions(+), 4 deletions(-) diff --git a

[PATCH v11 58/77] target/riscv: rvv-1.0: remove integer extract instruction

From: Frank Chang Signed-off-by: Frank Chang Reviewed-by: Richard Henderson --- target/riscv/insn32.decode | 1 - target/riscv/insn_trans/trans_rvv.c.inc | 23 --- 2 files changed, 24 deletions(-) diff --git a/target/riscv/insn32.decode b/target/riscv/insn32

[PATCH v11 71/77] target/riscv: rvv-1.0: rename r2_zimm to r2_zimm11

From: Frank Chang Rename r2_zimm to r2_zimm11 for the upcoming vsetivli instruction. vsetivli has 10-bits of zimm but vsetvli has 11-bits of zimm. Signed-off-by: Frank Chang Reviewed-by: Alistair Francis --- target/riscv/insn32.decode | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions

[PATCH v11 73/77] target/riscv: rvv-1.0: add evl parameter to vext_ldst_us()

From: Frank Chang Add supports of Vector unit-stride mask load/store instructions (vlm.v, vsm.v), which has: evl (effective vector length) = ceil(env->vl / 8). The new instructions operate the same as unmasked byte loads and stores. Add evl parameter to reuse vext_ldst_us(). Signed-off

[PATCH v11 63/77] target/riscv: add "set round to odd" rounding mode helper function

From: Frank Chang helper_set_rounding_mode() is responsible for SIGILL, and "round to odd" should be an interface private to translation, so add a new independent helper_set_rod_rounding_mode(). Signed-off-by: Frank Chang Acked-by: Alistair Francis --- target/riscv/fpu_he

[PATCH v11 72/77] target/riscv: rvv-1.0: add vsetivli instruction

From: Frank Chang Signed-off-by: Frank Chang Reviewed-by: Alistair Francis --- target/riscv/insn32.decode | 2 ++ target/riscv/insn_trans/trans_rvv.c.inc | 27 + 2 files changed, 29 insertions(+) diff --git a/target/riscv/insn32.decode b/target/riscv

[PATCH v11 75/77] target/riscv: rvv-1.0: rename vmandnot.mm and vmornot.mm to vmandn.mm and vmorn.mm

From: Frank Chang Signed-off-by: Frank Chang Reviewed-by: Alistair Francis --- target/riscv/helper.h | 4 ++-- target/riscv/insn32.decode | 4 ++-- target/riscv/insn_trans/trans_rvv.c.inc | 4 ++-- target/riscv/vector_helper.c| 4 ++-- 4 files

[PATCH v11 64/77] target/riscv: rvv-1.0: narrowing floating-point/integer type-convert

From: Frank Chang Signed-off-by: Frank Chang Acked-by: Alistair Francis --- target/riscv/helper.h | 22 - target/riscv/insn32.decode | 15 --- target/riscv/insn_trans/trans_rvv.c.inc | 59 + target/riscv/vector_helper.c

[PATCH v11 66/77] target/riscv: rvv-1.0: implement vstart CSR

From: Frank Chang * Update and check vstart value for vector instructions. * Add whole register move instruction helper functions as we have to call helper function for case where vstart is not zero. * Remove probe_pages() calls in vector load/store instructions (except fault-only-first

[PATCH v11 67/77] target/riscv: rvv-1.0: trigger illegal instruction exception if frm is not valid

From: Frank Chang If the frm field contains an invalid rounding mode (101-111), attempting to execute any vector floating-point instruction, even those that do not depend on the rounding mode, will raise an illegal instruction exception. Call gen_set_rm() with DYN rounding mode to check and

[PATCH v11 70/77] target/riscv: rvv-1.0: floating-point reciprocal estimate instruction

From: Frank Chang Implement the floating-point reciprocal estimate to 7 bits instruction. Signed-off-by: Frank Chang Acked-by: Alistair Francis --- target/riscv/helper.h | 4 + target/riscv/insn32.decode | 1 + target/riscv/insn_trans/trans_rvv.c.inc | 1

[PATCH v11 76/77] target/riscv: rvv-1.0: update opivv_vadc_check() comment

From: Frank Chang Vector Integer Add-with-Carry / Subtract-with-Borrow Instructions is moved to Section 11.4 in RVV v1.0 spec. Update the comment, no functional changes. Signed-off-by: Frank Chang Reviewed-by: Alistair Francis --- target/riscv/insn_trans/trans_rvv.c.inc | 2 +- 1 file

[PATCH v11 77/77] target/riscv: rvv-1.0: Add ELEN checks for widening and narrowing instructions

From: Frank Chang SEW has the limitation which cannot exceed ELEN. Widening instructions have a destination group with EEW = 2*SEW and narrowing instructions have a source operand with EEW = 2*SEW. Both of the instructions have the limitation of: 2*SEW <= ELEN. Signed-off-by: Frank Ch

Re: [PATCH] hw/pci-host: Allow extended config space access for Designware PCIe host

Reviewed-by: Frank Chang On Wed, Aug 9, 2023 at 6:23 PM Jason Chien wrote: > In pcie_bus_realize(), a root bus is realized as a PCIe bus and a non-root > bus is realized as a PCIe bus if its parent bus is a PCIe bus. However, > the child bus "dw-pcie" is realized before t

Re: [PATCH] target/riscv: Add Zihintntl extension ISA string to DTS

Reviewed-by: Frank Chang On Tue, Jul 4, 2023 at 4:41 PM Jason Chien wrote: > RVA23 Profiles states: > The RVA23 profiles are intended to be used for 64-bit application > processors that will run rich OS stacks from standard binary OS > distributions and with a substantial number of

Re: [ PATCH v3 08/10] target/riscv: Add sscofpmf extension support

_bit_mask = MHPMEVENT_BIT_OF; > +} > + > +counter = &env->pmu_ctrs[ctr_idx]; > +if (counter->irq_overflow_left > 0) { > +irq_trigger_at = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + > +counter->irq_overflow_left; > +

[PATCH] hw/sd: Add SDHC support for SD card SPI-mode

From: Frank Chang In SPI-mode, SD card's OCR register: Card Capacity Status (CCS) bit is not set to 1 correclty when the assigned SD image size is larger than 2GB (SDHC). This will cause the SD card to be indentified as SDSC incorrectly. CCS bit should be set to 1 if we are using SDHC. Als

[PATCH v2] hw/sd: Add SDHC support for SD card SPI-mode

From: Frank Chang In SPI-mode, SD card's OCR register: Card Capacity Status (CCS) bit is not set to 1 correclty when the assigned SD image size is larger than 2GB (SDHC). This will cause the SD card to be indentified as SDSC incorrectly. CCS bit should be set to 1 if we are using SDHC. Als

[PATCH 0/3] Fix RVV calling incorrect RFV/RVD check functions bug

From: Frank Chang For vector widening and narrowing floating-point instructions, we should use require_scale_rvf() instead of require_rvf() to check whether the correspond RVF/RVD is enabled if either source or destination floating-point operand is double-width of SEW. Otherwise, illegal

[PATCH 1/3] target/riscv: rvv-1.0: Call the correct RVF/RVD check funtion for widening fp insns

From: Frank Chang Vector widening floating-point instructions should use require_scale_rvf() instead of require_rvf() to check whether RVF/RVD is enabled. --- target/riscv/insn_trans/trans_rvv.c.inc | 12 1 file changed, 8 insertions(+), 4 deletions(-) diff --git a/target/riscv

[PATCH 3/3] target/riscv: rvv-1.0: Call the correct RVF/RVD check funtion for narrowing fp/int type-convert insns

From: Frank Chang vfncvt.f.xu.w, vfncvt.f.x.w convert double-width integer to single-width floating-point. Therefore, should use require_rvf() to check whether RVF/RVD is enabled. vfncvt.f.f.w, vfncvt.rod.f.f.w convert double-width floating-point to single-width integer. Therefore, should use

[PATCH 2/3] target/riscv: rvv-1.0: Call the correct RVF/RVD check funtion for widening fp/int type-convert insns

From: Frank Chang vfwcvt.xu.f.v, vfwcvt.x.f.v, vfwcvt.rtz.xu.f.v and vfwcvt.rtz.x.f.v convert single-width floating-point to double-width integer. Therefore, should use require_rvf() to check whether RVF/RVD is enabled. vfwcvt.f.xu.v, vfwcvt.f.x.v convert single-width integer to double-width

[PATCH 00/17] Add RISC-V RVV Zve32f and Zve64f extensions

From: Frank Chang In RVV v1.0 spec, several Zve* vector extensions for embedded processors are defined in Chapter 18.2: https://github.com/riscv/riscv-v-spec/blob/v1.0/v-spec.adoc#zve-vector-extensions-for-embedded-processors This patchset implements Zve32f and Zve64f extensions. The port is

[PATCH 01/17] target/riscv: rvv-1.0: Add Zve64f extension into RISC-V

From: Frank Chang Signed-off-by: Frank Chang --- target/riscv/cpu.c| 4 target/riscv/cpu.h| 1 + target/riscv/cpu_helper.c | 5 - target/riscv/csr.c| 6 +- target/riscv/translate.c | 2 ++ 5 files changed, 16 insertions(+), 2 deletions(-) diff --git a

[PATCH 03/17] target/riscv: rvv-1.0: Add Zve64f support for load and store insns

From: Frank Chang All Zve* extensions support all vector load and store instructions, except Zve64* extensions do not support EEW=64 for index values when XLEN=32. Signed-off-by: Frank Chang --- target/riscv/insn_trans/trans_rvv.c.inc | 17 + 1 file changed, 13 insertions

[PATCH 11/17] target/riscv: rvv-1.0: Add Zve32f extension into RISC-V

From: Frank Chang Signed-off-by: Frank Chang --- target/riscv/cpu.c| 4 ++-- target/riscv/cpu.h| 1 + target/riscv/cpu_helper.c | 2 +- target/riscv/csr.c| 2 +- target/riscv/translate.c | 2 ++ 5 files changed, 7 insertions(+), 4 deletions(-) diff --git a/target

[PATCH 02/17] target/riscv: rvv-1.0: Add Zve64f support for configuration insns

From: Frank Chang All Zve* extensions support the vector configuration instructions. Signed-off-by: Frank Chang --- target/riscv/insn_trans/trans_rvv.c.inc | 6 -- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv

[PATCH 04/17] target/riscv: rvv-1.0: Add Zve64f support for vmulh variant insns

From: Frank Chang All Zve* extensions support all vector integer instructions, except that the vmulh integer multiply variants that return the high word of the product (vmulh.vv, vmulh.vx, vmulhu.vv, vmulhu.vx, vmulhsu.vv, vmulhsu.vx) are not included for EEW=64 in Zve64*. Signed-off-by: Frank

[PATCH 05/17] target/riscv: rvv-1.0: Add Zve64f support for vsmul.vv and vsmul.vx insns

From: Frank Chang All Zve* extensions support all vector fixed-point arithmetic instructions, except that vsmul.vv and vsmul.vx are not supported for EEW=64 in Zve64*. Signed-off-by: Frank Chang --- target/riscv/insn_trans/trans_rvv.c.inc | 27 +++-- 1 file changed, 25

[PATCH 12/17] target/riscv: rvv-1.0: Add Zve32f support for configuration insns

From: Frank Chang All Zve* extensions support the vector configuration instructions. Signed-off-by: Frank Chang --- target/riscv/insn_trans/trans_rvv.c.inc | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv

[PATCH 08/17] target/riscv: rvv-1.0: Add Zve64f support for widening type-convert insns

From: Frank Chang Vector widening conversion instructions are provided to and from all supported integer EEWs for Zve64f extension. Signed-off-by: Frank Chang --- target/riscv/insn_trans/trans_rvv.c.inc | 32 +++-- 1 file changed, 25 insertions(+), 7 deletions(-) diff

[PATCH 07/17] target/riscv: rvv-1.0: Add Zve64f support for single-width fp reduction insns

From: Frank Chang Vector single-width floating-point reduction operations for EEW=32 are supported for Zve64f extension. Signed-off-by: Frank Chang --- target/riscv/insn_trans/trans_rvv.c.inc | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/target/riscv/insn_trans

[PATCH 06/17] target/riscv: rvv-1.0: Add Zve64f support for scalar fp insns

From: Frank Chang Zve64f extension requires the scalar processor to implement the F extension and implement all vector floating-point instructions for floating-point operands with EEW=32 (i.e., no widening floating-point operations). Signed-off-by: Frank Chang --- target/riscv/insn_trans

[PATCH 10/17] target/riscv: rvv-1.0: Allow Zve64f extension to be turned on

From: Frank Chang Signed-off-by: Frank Chang --- target/riscv/cpu.c | 1 + 1 file changed, 1 insertion(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 01239620ca..38cd11a8ae 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -636,6 +636,7 @@ static Property

[PATCH 09/17] target/riscv: rvv-1.0: Add Zve64f support for narrowing type-convert insns

From: Frank Chang Vector narrowing conversion instructions are provided to and from all supported integer EEWs for Zve64f extension. Signed-off-by: Frank Chang --- target/riscv/insn_trans/trans_rvv.c.inc | 9 ++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/target/riscv

[PATCH 16/17] target/riscv: rvv-1.0: Add Zve32f support for narrowing type-convert insns

From: Frank Chang Vector narrowing conversion instructions are provided to and from all supported integer EEWs for Zve32f extension. Signed-off-by: Frank Chang --- target/riscv/insn_trans/trans_rvv.c.inc | 3 +++ 1 file changed, 3 insertions(+) diff --git a/target/riscv/insn_trans

[PATCH 14/17] target/riscv: rvv-1.0: Add Zve32f support for single-width fp reduction insns

From: Frank Chang Vector single-width floating-point reduction operations for EEW=32 are supported for Zve32f extension. Signed-off-by: Frank Chang --- target/riscv/insn_trans/trans_rvv.c.inc | 1 + 1 file changed, 1 insertion(+) diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target

[PATCH 13/17] target/riscv: rvv-1.0: Add Zve32f support for scalar fp insns

From: Frank Chang Zve32f extension requires the scalar processor to implement the F extension and implement all vector floating-point instructions for floating-point operands with EEW=32 (i.e., no widening floating-point operations). Signed-off-by: Frank Chang --- target/riscv/insn_trans

[PATCH 15/17] target/riscv: rvv-1.0: Add Zve32f support for widening type-convert insns

From: Frank Chang Vector widening conversion instructions are provided to and from all supported integer EEWs for Zve32f extension. Signed-off-by: Frank Chang --- target/riscv/insn_trans/trans_rvv.c.inc | 18 ++ 1 file changed, 18 insertions(+) diff --git a/target/riscv

[PATCH 17/17] target/riscv: rvv-1.0: Allow Zve32f extension to be turned on

From: Frank Chang Signed-off-by: Frank Chang --- target/riscv/cpu.c | 1 + 1 file changed, 1 insertion(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 5e98860a09..2b54c64f56 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -636,6 +636,7 @@ static Property

Re: [PATCH 0/3] Fix RVV calling incorrect RFV/RVD check functions bug

於 2021年12月29日 週三 上午10:13寫道： > From: Frank Chang > > For vector widening and narrowing floating-point instructions, we should > use require_scale_rvf() instead of require_rvf() to check whether the > correspond RVF/RVD is enabled if either source or destination > floating-point

Re: [PATCH 0/3] Fix RVV calling incorrect RFV/RVD check functions bug

On Wed, Dec 29, 2021 at 10:43 AM Frank Chang wrote: > 於 2021年12月29日 週三 上午10:13寫道： > >> From: Frank Chang >> >> For vector widening and narrowing floating-point instructions, we should >> use require_scale_rvf() instead of require_rvf() to check whether the >&

[PATCH v6 10/17] target/riscv: rvb: shift ones

From: Kito Cheng Signed-off-by: Kito Cheng Signed-off-by: Frank Chang Reviewed-by: Richard Henderson --- target/riscv/insn32.decode | 8 target/riscv/insn_trans/trans_rvb.c.inc | 52 + target/riscv/translate.c| 14 +++ 3 files

[PATCH v6 15/17] target/riscv: rvb: add/shift with prefix zero-extend

From: Kito Cheng Signed-off-by: Kito Cheng Signed-off-by: Frank Chang Reviewed-by: Richard Henderson --- target/riscv/insn32.decode | 3 +++ target/riscv/insn_trans/trans_rvb.c.inc | 26 + target/riscv/translate.c| 6 ++ 3 files

[PATCH v6 00/17] support subsets of bitmanip extension

From: Frank Chang This patchset implements RISC-V B-extension v0.93 version Zba, Zbb and Zbs subset instructions. Some Zbp instructions are also implemented as they have similar behavior with their Zba-, Zbb- and Zbs-family instructions or for Zbb pseudo instructions (e.g. rev8, orc.b

[PATCH v6 03/17] target/riscv: rvb: count bits set

From: Frank Chang Signed-off-by: Kito Cheng Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis Signed-off-by: Frank Chang --- target/riscv/insn32.decode | 2 ++ target/riscv/insn_trans/trans_rvb.c.inc | 13 + target/riscv/translate.c| 6

[PATCH v6 11/17] target/riscv: rvb: rotate (left/right)

From: Kito Cheng Signed-off-by: Kito Cheng Signed-off-by: Frank Chang Reviewed-by: Richard Henderson --- target/riscv/insn32.decode | 6 target/riscv/insn_trans/trans_rvb.c.inc | 39 + target/riscv/translate.c| 36

[PATCH v6 12/17] target/riscv: rvb: generalized reverse

From: Frank Chang Signed-off-by: Frank Chang Reviewed-by: Richard Henderson --- target/riscv/bitmanip_helper.c | 64 + target/riscv/helper.h | 4 ++ target/riscv/insn32.decode | 4 ++ target/riscv/insn_trans/trans_rvb.c.inc

[PATCH v6 01/17] target/riscv: reformat @sh format encoding for B-extension

From: Kito Cheng Signed-off-by: Kito Cheng Signed-off-by: Frank Chang Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/insn32.decode | 10 +- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/target/riscv/insn32.decode b/target/riscv/insn32

[PATCH v6 06/17] target/riscv: rvb: min/max instructions

From: Kito Cheng Signed-off-by: Kito Cheng Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis Signed-off-by: Frank Chang --- target/riscv/insn32.decode | 4 target/riscv/insn_trans/trans_rvb.c.inc | 24 2 files changed, 28 insertions

[PATCH v6 14/17] target/riscv: rvb: address calculation

From: Kito Cheng Signed-off-by: Kito Cheng Signed-off-by: Frank Chang Reviewed-by: Richard Henderson --- target/riscv/insn32.decode | 6 + target/riscv/insn_trans/trans_rvb.c.inc | 24 +++ target/riscv/translate.c| 32

[PATCH v6 02/17] target/riscv: rvb: count leading/trailing zeros

From: Kito Cheng Signed-off-by: Kito Cheng Signed-off-by: Frank Chang Reviewed-by: Richard Henderson --- target/riscv/cpu.h | 1 + target/riscv/insn32.decode | 11 ++- target/riscv/insn_trans/trans_rvb.c.inc | 44 + target/riscv

[PATCH v6 08/17] target/riscv: add gen_shifti() and gen_shiftiw() helper functions

From: Frank Chang Add gen_shifti() and gen_shiftiw() helper functions to reuse the same interfaces for immediate shift instructions. Signed-off-by: Frank Chang Reviewed-by: Richard Henderson --- target/riscv/insn_trans/trans_rvi.c.inc | 54 ++--- target/riscv/translate.c

[PATCH v6 17/17] target/riscv: rvb: add b-ext version cpu option

From: Frank Chang Default b-ext version is v0.93. Signed-off-by: Frank Chang --- target/riscv/cpu.c | 23 +++ target/riscv/cpu.h | 3 +++ 2 files changed, 26 insertions(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 1b3c5ba1480..32469f7c891 100644 --- a

[PATCH v6 04/17] target/riscv: rvb: logic-with-negate

From: Kito Cheng Signed-off-by: Kito Cheng Signed-off-by: Frank Chang Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/insn32.decode | 3 +++ target/riscv/insn_trans/trans_rvb.c.inc | 18 ++ 2 files changed, 21 insertions(+) diff

[PATCH v6 05/17] target/riscv: rvb: pack two words into one register

From: Kito Cheng Signed-off-by: Kito Cheng Signed-off-by: Frank Chang Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/insn32.decode | 6 target/riscv/insn_trans/trans_rvb.c.inc | 32 target/riscv/translate.c

[PATCH v6 07/17] target/riscv: rvb: sign-extend instructions

From: Kito Cheng Signed-off-by: Kito Cheng Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis Signed-off-by: Frank Chang --- target/riscv/insn32.decode | 3 +++ target/riscv/insn_trans/trans_rvb.c.inc | 12 2 files changed, 15 insertions(+) diff --git a

[PATCH v6 09/17] target/riscv: rvb: single-bit instructions

From: Frank Chang Signed-off-by: Kito Cheng Signed-off-by: Frank Chang Reviewed-by: Richard Henderson --- target/riscv/insn32.decode | 17 + target/riscv/insn_trans/trans_rvb.c.inc | 97 + target/riscv/translate.c| 61

[PATCH v6 13/17] target/riscv: rvb: generalized or-combine

From: Frank Chang Signed-off-by: Frank Chang Reviewed-by: Richard Henderson --- target/riscv/bitmanip_helper.c | 26 + target/riscv/helper.h | 2 ++ target/riscv/insn32.decode | 4 target/riscv/insn_trans/trans_rvb.c.inc

[PATCH v6 16/17] target/riscv: rvb: support and turn on B-extension from command line

From: Kito Cheng B-extension is default off, use cpu rv32 or rv64 with x-b=true to enable B-extension. Signed-off-by: Kito Cheng Signed-off-by: Frank Chang Reviewed-by: Alistair Francis Reviewed-by: Richard Henderson --- target/riscv/cpu.c | 4 target/riscv/cpu.h | 1 + 2 files

Re: [PATCH] target/riscv: Add a property to set vl to ceil(AVL/2)

Reviewed-by: Frank Chang Jason Chien 於 2024年7月23日 週二 上午1:51寫道： > > RVV spec allows implementations to set vl with values within > [ceil(AVL/2),VLMAX] when VLMAX < AVL < 2*VLMAX. This commit adds a > property "rvv_vl_half_avl" to enable setting vl = ceil(AVL/2). Th

Re: [RFC v3 26/71] target/riscv: rvv-1.0: update vext_max_elems() for load/store insns

the detailed point outs. I manage to change the codes to below as your suggestion. > static inline uint32_t vext_max_elems(uint32_t desc, uint32_t esz) > { > /* > * As simd_desc support at most 256 bytes, the max vlen is 256 bits. > * so vlen in bytes (vlenb) is encoded as maxsz. > */ > uint32_t vlenb = simd_maxsz(desc); > > /* Return VLMAX */ > int scale = vext_lmul(desc) - ctzl(esz); // may remove ctzl() if esz is already log2(esz) > return scale < 0 ? vlenb >> -scale : vlenb << scale; > } > > r~ > Thanks for the review. Frank Chang

Re: [RFC v3 12/71] target/riscv: rvv-1.0: add fractional LMUL

c), VDATA, LMUL); > > + uint32_t lmul = FIELD_EX32(simd_data(desc), VDATA, LMUL); > > +return (int8_t)(lmul << 5) >> 5; > > } > > ... this encoding? > > Oh, and sextract32(lmul, 0, 3) instead of those shifts. > OK~ > > > r~ > Thanks Frank Chang

Re: [RFC v3 26/71] target/riscv: rvv-1.0: update vext_max_elems() for load/store insns

On Sat, Aug 15, 2020 at 2:36 AM Richard Henderson < richard.hender...@linaro.org> wrote: > On 8/13/20 7:48 PM, Frank Chang wrote: > > esz is passed from e.g. GEN_VEXT_LD_STRIDE() macro: > > > >> #define GEN_VEXT_LD_STRIDE(NAME, ETYPE, LOAD_FN)\ > >>

Re: [RFC v3 26/71] target/riscv: rvv-1.0: update vext_max_elems() for load/store insns

On Sat, Aug 15, 2020 at 2:36 AM Richard Henderson < richard.hender...@linaro.org> wrote: > On 8/13/20 7:48 PM, Frank Chang wrote: > > esz is passed from e.g. GEN_VEXT_LD_STRIDE() macro: > > > >> #define GEN_VEXT_LD_STRIDE(NAME, ETYPE, LOAD_FN)\ > >>

Re: [RFC v3 26/71] target/riscv: rvv-1.0: update vext_max_elems() for load/store insns

On Sat, Aug 15, 2020 at 1:29 PM Richard Henderson < richard.hender...@linaro.org> wrote: > On 8/14/20 7:52 PM, Frank Chang wrote: > > probe_pages(env, base + stride * i, nf * esz, ra, access_type); > > and > > target_ulong addr = base + stride * i + k * esz; >

[RFC v4 00/70] support vector extension v1.0

From: Frank Chang This patchset implements the vector extension v1.0 for RISC-V on QEMU. This patchset is sent as RFC because RVV v1.0 is still in draft state. v2 patchset was sent for RVV v0.9 and bumped to RVV v1.0 since v3 patchset. The port is available here: https://github.com/sifive/qemu

[RFC v4 02/70] target/riscv: Use FIELD_EX32() to extract wd field

From: Frank Chang Signed-off-by: Frank Chang Reviewed-by: Richard Henderson --- target/riscv/vector_helper.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c index 793af990673..43ba272c09b 100644 --- a/target/riscv

[RFC v4 03/70] target/riscv: rvv-1.0: add mstatus VS field

From: LIU Zhiwei Signed-off-by: LIU Zhiwei Signed-off-by: Frank Chang Reviewed-by: Richard Henderson --- target/riscv/cpu.h| 6 ++ target/riscv/cpu_bits.h | 1 + target/riscv/cpu_helper.c | 16 +++- target/riscv/csr.c| 25 - 4 files

[RFC v4 11/70] target/riscv: rvv-1.0: remove MLEN calculations

From: Frank Chang As in RVV 1.0 design, MLEN is hardcoded with value 1 (Section 4.5). Thus, remove all MLEN related calculations. Signed-off-by: Frank Chang Reviewed-by: Richard Henderson --- target/riscv/insn_trans/trans_rvv.inc.c | 35 +--- target/riscv/internals.h| 9

[RFC v4 01/70] target/riscv: drop vector 0.7.1 and add 1.0 support

From: Frank Chang Signed-off-by: Frank Chang Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/cpu.c | 10 +- target/riscv/cpu.h | 2 +- 2 files changed, 6 insertions(+), 6 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index

[RFC v4 04/70] target/riscv: rvv-1.0: add sstatus VS field

From: LIU Zhiwei Signed-off-by: LIU Zhiwei Signed-off-by: Frank Chang Reviewed-by: Richard Henderson --- target/riscv/cpu_bits.h | 1 + target/riscv/csr.c | 2 +- 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index

[RFC v4 05/70] target/riscv: rvv-1.0: introduce writable misa.v field

From: Frank Chang Implementations may have a writable misa.v field. Analogous to the way in which the floating-point unit is handled, the mstatus.vs field may exist even if misa.v is clear. Signed-off-by: Frank Chang Reviewed-by: Richard Henderson --- target/riscv/csr.c | 2 +- 1 file

[RFC v4 08/70] target/riscv: rvv-1.0: add vcsr register

From: LIU Zhiwei Signed-off-by: LIU Zhiwei Signed-off-by: Frank Chang Reviewed-by: Richard Henderson --- target/riscv/cpu_bits.h | 7 +++ target/riscv/csr.c | 21 + 2 files changed, 28 insertions(+) diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h

[RFC v4 06/70] target/riscv: rvv-1.0: add translation-time vector context status

From: LIU Zhiwei Signed-off-by: LIU Zhiwei Signed-off-by: Frank Chang Reviewed-by: Richard Henderson --- target/riscv/insn_trans/trans_rvv.inc.c | 69 - target/riscv/translate.c| 33 2 files changed, 90 insertions(+), 12 deletions(-) diff

[RFC v4 07/70] target/riscv: rvv-1.0: remove rvv related codes from fcsr registers

From: Frank Chang * Remove VXRM and VXSAT fields from FCSR register as they are only presented in VCSR register. * Remove RVV loose check in fs() predicate function. Signed-off-by: Frank Chang --- target/riscv/csr.c | 13 - 1 file changed, 13 deletions(-) diff --git a/target

[RFC v4 24/70] target/riscv: rvv-1.0: update vext_max_elems() for load/store insns

From: Frank Chang Unlike other vector instructions, load/store vector instructions return the maximum vector size calculated with EMUL. For other vector instructions, return VLMAX as the maximum vector size. Signed-off-by: Frank Chang --- target/riscv/insn_trans/trans_rvv.inc.c | 57

[RFC v4 20/70] target/riscv: rvv-1.0: fix address index overflow bug of indexed load/store insns

From: Frank Chang Replace ETYPE from signed int to unsigned int to prevent index overflow issue, which would lead to wrong index address. Signed-off-by: Frank Chang --- target/riscv/vector_helper.c | 8 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/target/riscv

[RFC v4 10/70] target/riscv: rvv-1.0: check MSTATUS_VS when accessing vector csr registers

From: Frank Chang If VS field is off, accessing vector csr registers should raise an illegal-instruction exception. Signed-off-by: Frank Chang Reviewed-by: Richard Henderson --- target/riscv/csr.c | 5 + 1 file changed, 5 insertions(+) diff --git a/target/riscv/csr.c b/target/riscv

[RFC v4 09/70] target/riscv: rvv-1.0: add vlenb register

From: Greentime Hu Signed-off-by: Greentime Hu Signed-off-by: Frank Chang Reviewed-by: Richard Henderson --- target/riscv/cpu_bits.h | 1 + target/riscv/csr.c | 7 +++ 2 files changed, 8 insertions(+) diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index 7afdd4814bb

[RFC v4 27/70] target/riscv: rvv-1.0: floating-point classify instructions

From: Frank Chang Signed-off-by: Frank Chang Reviewed-by: Richard Henderson --- target/riscv/insn32.decode | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index f142aa5d073..a800c989050 100644 --- a/target/riscv

[RFC v4 21/70] target/riscv: rvv-1.0: fault-only-first unit stride load

From: Frank Chang Signed-off-by: Frank Chang --- target/riscv/helper.h | 27 +++- target/riscv/insn32.decode | 14 +++ target/riscv/insn_trans/trans_rvv.inc.c | 31 -- target/riscv/vector_helper.c| 56

[RFC v4 28/70] target/riscv: rvv-1.0: mask population count instruction

From: Frank Chang Signed-off-by: Frank Chang Reviewed-by: Richard Henderson --- target/riscv/helper.h | 2 +- target/riscv/insn32.decode | 2 +- target/riscv/insn_trans/trans_rvv.inc.c | 7 --- target/riscv/vector_helper.c| 6 +++--- 4 files

[RFC v4 12/70] target/riscv: rvv-1.0: add fractional LMUL

From: Frank Chang Introduce the concepts of fractional LMUL for RVV 1.0. In RVV 1.0, LMUL bits are contiguous in vtype register. Signed-off-by: Frank Chang --- target/riscv/cpu.h | 15 --- target/riscv/translate.c | 16 ++-- target/riscv/vector_helper.c

[RFC v4 22/70] target/riscv: rvv-1.0: amo operations

From: Frank Chang Signed-off-by: Frank Chang --- target/riscv/helper.h | 100 +++--- target/riscv/insn32-64.decode | 18 +- target/riscv/insn32.decode | 36 +++- target/riscv/insn_trans/trans_rvv.inc.c | 220 ++ target/riscv

[RFC v4 16/70] target/riscv: rvv:1.0: add translation-time nan-box helper function

From: Frank Chang * Add fp16 nan-box check generator function, if a 16-bit input is not properly nanboxed, then the input is replaced with the default qnan. * Add do_nanbox() helper function to utilize gen_check_nanbox_X() to generate the NaN-boxed floating-point values based on SEW setting

[RFC v4 35/70] target/riscv: rvv-1.0: integer scalar move instructions

From: Frank Chang * Remove "vmv.s.x: dothing if rs1 == 0" constraint. * Add vmv.x.s instruction. Signed-off-by: Frank Chang Reviewed-by: Richard Henderson --- target/riscv/insn32.decode | 3 +- target/riscv/insn_trans/trans_rvv.inc.c | 45

[RFC v4 39/70] target/riscv: rvv-1.0: integer extension instructions

From: Frank Chang Add the following instructions: * vzext.vf2 * vzext.vf4 * vzext.vf8 * vsext.vf2 * vsext.vf4 * vsext.vf8 Signed-off-by: Frank Chang Reviewed-by: Richard Henderson --- target/riscv/helper.h | 14 target/riscv/insn32.decode | 8 +++ target

[RFC v4 15/70] target/riscv: introduce more imm value modes in translator functions

From: Frank Chang Immediate value in translator function is extended not only zero-extended and sign-extended but with more modes to be applicable with multiple formats of vector instructions. * IMM_ZX: Zero-extended * IMM_SX: Sign-extended * IMM_TRUNC_SEW: Truncate to log(SEW

[RFC v4 23/70] target/riscv: rvv-1.0: load/store whole register instructions

From: Frank Chang Add the following instructions: * vlre.v * vsr.v Signed-off-by: Frank Chang --- target/riscv/helper.h | 21 target/riscv/insn32.decode | 22 target/riscv/insn_trans/trans_rvv.inc.c | 72 + target/riscv

[RFC v4 17/70] target/riscv: rvv-1.0: configure instructions

From: Frank Chang Signed-off-by: Frank Chang Reviewed-by: Richard Henderson --- target/riscv/insn_trans/trans_rvv.inc.c | 12 target/riscv/vector_helper.c| 14 +- 2 files changed, 21 insertions(+), 5 deletions(-) diff --git a/target/riscv/insn_trans

[RFC v4 40/70] target/riscv: rvv-1.0: single-width averaging add and subtract instructions

From: Frank Chang Add the following instructions: * vaaddu.vv * vaaddu.vx * vasubu.vv * vasubu.vx Remove the following instructions: * vadd.vi Signed-off-by: Frank Chang --- target/riscv/helper.h | 16 ++ target/riscv/insn32.decode | 13 +++-- target

[RFC v4 32/70] target/riscv: rvv-1.0: element index instruction

From: Frank Chang Signed-off-by: Frank Chang Reviewed-by: Richard Henderson --- target/riscv/insn32.decode | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index 7a10fc27c5f..15afc469cb0 100644 --- a/target/riscv

[RFC v4 14/70] target/riscv: rvv-1.0: update check functions

From: Frank Chang Update check functions with RVV 1.0 rules. Signed-off-by: Frank Chang --- target/riscv/insn_trans/trans_rvv.inc.c | 708 1 file changed, 476 insertions(+), 232 deletions(-) diff --git a/target/riscv/insn_trans/trans_rvv.inc.c b/target/riscv

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