From: Kito Cheng
Signed-off-by: Kito Cheng
Signed-off-by: Chih-Min Chao
Signed-off-by: Frank Chang
Reviewed-by: Richard Henderson
---
target/riscv/cpu.h| 1 +
target/riscv/insn32.decode| 4 ++
target/riscv/insn_trans/trans_rvzfh.c.inc | 65
From: Kito Cheng
Signed-off-by: Kito Cheng
Signed-off-by: Chih-Min Chao
Signed-off-by: Frank Chang
Reviewed-by: Richard Henderson
Reviewed-by: Alistair Francis
---
target/riscv/fpu_helper.c | 21 +
target/riscv/helper.h | 3 ++
target/riscv
From: Frank Chang
Zfhmin extension is a subset of Zfh extension, consisting only of data
transfer and conversion instructions.
If enabled, only the following instructions from Zfh extension are
included:
* flh, fsh, fmv.x.h, fmv.h.x, fcvt.s.h, fcvt.h.s
* If D extension is present: fcvt.d.h
From: Kito Cheng
Signed-off-by: Kito Cheng
Signed-off-by: Chih-Min Chao
Signed-off-by: Frank Chang
Reviewed-by: Richard Henderson
Reviewed-by: Alistair Francis
---
target/riscv/fpu_helper.c | 86 +++
target/riscv/helper.h | 13 +++
target
From: Kito Cheng
Signed-off-by: Kito Cheng
Signed-off-by: Chih-Min Chao
Signed-off-by: Frank Chang
Reviewed-by: Richard Henderson
Reviewed-by: Alistair Francis
---
target/riscv/fpu_helper.c | 6 ++
target/riscv/helper.h | 1 +
target/riscv/insn32
From: Kito Cheng
Signed-off-by: Kito Cheng
Signed-off-by: Chih-Min Chao
Signed-off-by: Frank Chang
Reviewed-by: Richard Henderson
Acked-by: Alistair Francis
---
target/riscv/fpu_helper.c | 67 +
target/riscv/helper.h | 12 +
target/riscv/insn32
From: Frank Chang
Signed-off-by: Frank Chang
---
target/riscv/cpu.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 8c579dc297b..4c0e6532164 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -602,6 +602,7 @@ static Property
From: Frank Chang
Signed-off-by: Frank Chang
---
target/riscv/cpu.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 1d69d1887e6..8c579dc297b 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -601,6 +601,7 @@ static Property
NaN && ft2 == NaN.
The IEEE 754 spec allows both implementation and some architecture such
as riscv choose different defintions in two spec versions.
(riscv-spec-v2.2 use original version, riscv-spec-20191213 changes to
alternative)
Signed-off-by: Chih-Min Chao
Signed-off-by: Frank Chang
Re
nough.
Signed-off-by: Chih-Min Chao
Signed-off-by: Frank Chang
Acked-by: Alistair Francis
---
target/riscv/fpu_helper.c | 16
1 file changed, 12 insertions(+), 4 deletions(-)
diff --git a/target/riscv/fpu_helper.c b/target/riscv/fpu_helper.c
index 8700516a14c..d62f4709002 1
From: Kito Cheng
Signed-off-by: Kito Cheng
Signed-off-by: Chih-Min Chao
Signed-off-by: Frank Chang
Reviewed-by: Richard Henderson
---
target/riscv/cpu.h| 1 +
target/riscv/insn32.decode| 4 ++
target/riscv/insn_trans/trans_rvzfh.c.inc | 65
From: Kito Cheng
Signed-off-by: Kito Cheng
Signed-off-by: Chih-Min Chao
Signed-off-by: Frank Chang
Reviewed-by: Richard Henderson
Reviewed-by: Alistair Francis
---
target/riscv/fpu_helper.c | 86 +++
target/riscv/helper.h | 13 +++
target
From: Kito Cheng
Signed-off-by: Kito Cheng
Signed-off-by: Chih-Min Chao
Signed-off-by: Frank Chang
Reviewed-by: Richard Henderson
Reviewed-by: Alistair Francis
---
target/riscv/fpu_helper.c | 21 +
target/riscv/helper.h | 3 ++
target/riscv
From: Kito Cheng
Signed-off-by: Kito Cheng
Signed-off-by: Chih-Min Chao
Signed-off-by: Frank Chang
Reviewed-by: Richard Henderson
Acked-by: Alistair Francis
---
target/riscv/fpu_helper.c | 67 +
target/riscv/helper.h | 12 +
target/riscv/insn32
From: Frank Chang
Signed-off-by: Frank Chang
Reviewed-by: Alistair Francis
---
target/riscv/cpu.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 788fa0b11c0..1b3a7784b06 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -617,6
From: Frank Chang
Signed-off-by: Frank Chang
Reviewed-by: Alistair Francis
---
target/riscv/cpu.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 1b3a7784b06..e6e3ef183ae 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -618,6
From: Frank Chang
Zfhmin extension is a subset of Zfh extension, consisting only of data
transfer and conversion instructions.
If enabled, only the following instructions from Zfh extension are
included:
* flh, fsh, fmv.x.h, fmv.h.x, fcvt.s.h, fcvt.h.s
* If D extension is present: fcvt.d.h
From: Kito Cheng
Signed-off-by: Kito Cheng
Signed-off-by: Chih-Min Chao
Signed-off-by: Frank Chang
Reviewed-by: Richard Henderson
Reviewed-by: Alistair Francis
---
target/riscv/fpu_helper.c | 6 ++
target/riscv/helper.h | 1 +
target/riscv/insn32
> >> Signed-off-by: Chih-Min Chao
> >> Signed-off-by: Frank Chang
> >> Reviewed-by: Richard Henderson
> >
> > It doesn't look like this made it through to the list. I only see v3
> > on patchew:
> https://patchew.org/QEMU/20211016090742.30346
On Thu, Oct 28, 2021 at 12:45 PM Alistair Francis <
alistair.fran...@opensource.wdc.com> wrote:
> From: Chih-Min Chao
>
> The sNaN propagation behavior has been changed since
> cd20cee7 in https://github.com/riscv/riscv-isa-manual.
>
> Signed-off-by: Chih-Min Chao
>
From: Frank Chang
Signed-off-by: Frank Chang
Reviewed-by: Richard Henderson
Reviewed-by: Alistair Francis
---
target/riscv/cpu.c | 16
target/riscv/cpu.h | 2 +-
2 files changed, 9 insertions(+), 9 deletions(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index
From: Frank Chang
This patchset implements the vector extension v1.0 for RISC-V on QEMU.
RVV v1.0 spec is now fronzen for public review:
https://github.com/riscv/riscv-v-spec/releases/tag/v1.0
The port is available here:
https://github.com/sifive/qemu/tree/rvv-1.0-upstream-v9
RVV v1.0 can be
From: Frank Chang
Signed-off-by: Frank Chang
Reviewed-by: Richard Henderson
Reviewed-by: Alistair Francis
---
target/riscv/vector_helper.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index 12c31aa4b4d
From: LIU Zhiwei
Signed-off-by: LIU Zhiwei
Signed-off-by: Frank Chang
Reviewed-by: Richard Henderson
Reviewed-by: Alistair Francis
---
target/riscv/cpu.h| 2 ++
target/riscv/cpu_bits.h | 1 +
target/riscv/cpu_helper.c | 20 +++-
target/riscv/csr.c| 12
From: Frank Chang
Implementations may have a writable misa.v field. Analogous to the way
in which the floating-point unit is handled, the mstatus.vs field may
exist even if misa.v is clear.
Signed-off-by: Frank Chang
Reviewed-by: Richard Henderson
Reviewed-by: Alistair Francis
---
target
From: Frank Chang
Update check functions with RVV 1.0 rules.
Signed-off-by: Frank Chang
Reviewed-by: Alistair Francis
---
target/riscv/insn_trans/trans_rvv.c.inc | 715 +---
1 file changed, 507 insertions(+), 208 deletions(-)
diff --git a/target/riscv/insn_trans
From: LIU Zhiwei
Signed-off-by: LIU Zhiwei
Signed-off-by: Frank Chang
Reviewed-by: Richard Henderson
Reviewed-by: Alistair Francis
---
target/riscv/cpu_bits.h | 1 +
target/riscv/csr.c | 2 +-
2 files changed, 2 insertions(+), 1 deletion(-)
diff --git a/target/riscv/cpu_bits.h b
From: Frank Chang
Signed-off-by: Frank Chang
---
target/riscv/csr.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index 9b5bd5d7b49..bb500afdeb5 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -502,6 +502,7 @@ static RISCVException
From: LIU Zhiwei
Signed-off-by: LIU Zhiwei
Signed-off-by: Frank Chang
Reviewed-by: Richard Henderson
Reviewed-by: Alistair Francis
---
target/riscv/cpu_bits.h | 7 +++
target/riscv/csr.c | 17 +
2 files changed, 24 insertions(+)
diff --git a/target/riscv
From: Greentime Hu
Signed-off-by: Greentime Hu
Signed-off-by: Frank Chang
Reviewed-by: Richard Henderson
Reviewed-by: Alistair Francis
---
target/riscv/cpu_bits.h | 1 +
target/riscv/csr.c | 7 +++
2 files changed, 8 insertions(+)
diff --git a/target/riscv/cpu_bits.h b/target
From: Frank Chang
Immediate value in translator function is extended not only
zero-extended and sign-extended but with more modes to be applicable
with multiple formats of vector instructions.
* IMM_ZX: Zero-extended
* IMM_SX: Sign-extended
* IMM_TRUNC_SEW: Truncate to log(SEW
From: Frank Chang
* Remove VXRM and VXSAT fields from FCSR register as they are only
presented in VCSR register.
* Remove RVV loose check in fs() predicate function.
Signed-off-by: Frank Chang
Reviewed-by: Richard Henderson
Reviewed-by: Alistair Francis
---
target/riscv/csr.c | 13
From: Frank Chang
Signed-off-by: LIU Zhiwei
Signed-off-by: Frank Chang
Reviewed-by: Richard Henderson
Reviewed-by: Alistair Francis
---
target/riscv/cpu.h | 5 +-
target/riscv/cpu_helper.c | 3 +
target/riscv/insn_trans/trans_rvv.c.inc | 75
From: Frank Chang
As in RVV 1.0 design, MLEN is hardcoded with value 1 (Section 4.5).
Thus, remove all MLEN related calculations.
Signed-off-by: Frank Chang
Reviewed-by: Richard Henderson
Reviewed-by: Alistair Francis
---
target/riscv/insn_trans/trans_rvv.c.inc | 35 +---
target/riscv
From: Frank Chang
Add the following instructions:
* vlre.v
* vsr.v
Signed-off-by: Frank Chang
Reviewed-by: Alistair Francis
---
target/riscv/helper.h | 21
target/riscv/insn32.decode | 22
target/riscv/insn_trans/trans_rvv.c.inc | 68
From: Frank Chang
If VS field is off, accessing vector csr registers should raise an
illegal-instruction exception.
Signed-off-by: Frank Chang
Reviewed-by: Richard Henderson
Reviewed-by: Alistair Francis
---
target/riscv/csr.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/target
From: Frank Chang
Signed-off-by: Frank Chang
Reviewed-by: Alistair Francis
---
target/riscv/insn_trans/trans_rvv.c.inc | 32 ++--
target/riscv/vector_helper.c| 99 ++---
2 files changed, 80 insertions(+), 51 deletions(-)
diff --git a/target/riscv
From: Frank Chang
* Add fp16 nan-box check generator function, if a 16-bit input is not
properly nanboxed, then the input is replaced with the default qnan.
* Add do_nanbox() helper function to utilize gen_check_nanbox_X() to
generate the NaN-boxed floating-point values based on SEW setting
From: Frank Chang
Signed-off-by: Frank Chang
Reviewed-by: Richard Henderson
Reviewed-by: Alistair Francis
---
target/riscv/helper.h | 2 +-
target/riscv/insn32.decode | 2 +-
target/riscv/insn_trans/trans_rvv.c.inc | 7 ---
target/riscv/vector_helper.c
From: Frank Chang
Introduce the concepts of fractional LMUL for RVV 1.0.
In RVV 1.0, LMUL bits are contiguous in vtype register.
Also rearrange rvv bits in TB_FLAGS to skip MSTATUS_VS (0x600)
and MSTATUS_FS (0x6000) bits.
Signed-off-by: Frank Chang
Reviewed-by: Richard Henderson
Reviewed-by
From: Frank Chang
Vector AMOs are removed from standard vector extensions. Will be added
later as separate Zvamo extension, but will need a different encoding
from earlier proposal.
Signed-off-by: Frank Chang
Reviewed-by: Alistair Francis
---
target/riscv/helper.h | 27
From: Frank Chang
Signed-off-by: Frank Chang
Reviewed-by: Richard Henderson
Reviewed-by: Alistair Francis
---
target/riscv/helper.h | 2 +-
target/riscv/insn32.decode | 2 +-
target/riscv/insn_trans/trans_rvv.c.inc | 4 ++--
target/riscv/vector_helper.c
From: Frank Chang
Update vext_get_vlmax() and MAXSZ() to take fractional LMUL into
calculation for RVV 1.0.
Signed-off-by: Frank Chang
Reviewed-by: Richard Henderson
Reviewed-by: Alistair Francis
---
target/riscv/cpu.h | 27 -
target/riscv
From: Frank Chang
Signed-off-by: Frank Chang
Reviewed-by: Richard Henderson
Reviewed-by: Alistair Francis
---
target/riscv/insn_trans/trans_rvv.c.inc | 62 +++--
target/riscv/vector_helper.c| 14 +-
2 files changed, 40 insertions(+), 36 deletions(-)
diff
From: Frank Chang
Signed-off-by: Frank Chang
Reviewed-by: Richard Henderson
Reviewed-by: Alistair Francis
---
target/riscv/insn32.decode | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index 7d8441d1f21..92a0e6fe51e
From: Frank Chang
Signed-off-by: Frank Chang
Reviewed-by: Alistair Francis
---
target/riscv/helper.h | 67 +++
target/riscv/insn32.decode | 21 +++--
target/riscv/insn_trans/trans_rvv.c.inc | 110 +---
target/riscv
From: Frank Chang
Signed-off-by: Frank Chang
Reviewed-by: Richard Henderson
Reviewed-by: Alistair Francis
---
target/riscv/insn32.decode | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index 3ac5162aeb7..ab274dcde12
From: Frank Chang
Signed-off-by: Frank Chang
Reviewed-by: Richard Henderson
Reviewed-by: Alistair Francis
---
target/riscv/insn32.decode | 2 +-
target/riscv/insn_trans/trans_rvv.c.inc | 10 --
2 files changed, 9 insertions(+), 3 deletions(-)
diff --git a/target/riscv
From: Frank Chang
Replace ETYPE from signed int to unsigned int to prevent index overflow
issue, which would lead to wrong index address.
Signed-off-by: Frank Chang
Reviewed-by: Richard Henderson
Reviewed-by: Alistair Francis
---
target/riscv/vector_helper.c | 8
1 file changed, 4
From: Frank Chang
Signed-off-by: Frank Chang
Reviewed-by: Alistair Francis
---
target/riscv/helper.h | 129 ++--
target/riscv/insn32.decode | 43 ++-
target/riscv/insn_trans/trans_rvv.c.inc | 376
target/riscv/vector_helper.c
From: Frank Chang
vfncvt.f.xu.w, vfncvt.f.x.w convert double-width integer to single-width
floating-point. Therefore, should use require_rvf() to check whether
RVF/RVD is enabled.
vfncvt.f.f.w, vfncvt.rod.f.f.w convert double-width floating-point to
single-width integer. Therefore, should use
From: Frank Chang
For vector widening and narrowing floating-point instructions, we should
use require_scale_rvf() instead of require_rvf() to check whether the
correspond RVF/RVD is enabled if either source or destination
floating-point operand is double-width of SEW. Otherwise, illegal
From: Frank Chang
vfwcvt.xu.f.v, vfwcvt.x.f.v, vfwcvt.rtz.xu.f.v and vfwcvt.rtz.x.f.v
convert single-width floating-point to double-width integer.
Therefore, should use require_rvf() to check whether RVF/RVD is enabled.
vfwcvt.f.xu.v, vfwcvt.f.x.v convert single-width integer to double-width
From: Frank Chang
Vector widening floating-point instructions should use
require_scale_rvf() instead of require_rvf() to check whether RVF/RVD is
enabled.
Signed-off-by: Frank Chang
---
target/riscv/insn_trans/trans_rvv.c.inc | 12
1 file changed, 8 insertions(+), 4 deletions
ret = -EINVAL;
> +bool set, pend, virt;
> +target_ulong priv, isel, vgein, xlen, nval, wmask;
> +
> +/* Translate CSR number for VS-mode */
> +csrno = aia_xlate_vs_csrno(env, csrno);
> +
> +/* Decode register details from CSR number */
> +virt = set =
> +} else {
> +aplic->state[irq] &= ~APLIC_ISTATE_PENDING;
> +}
> +}
> +
> +static void riscv_aplic_set_pending(RISCVAPLICState *aplic,
> + uint32_t irq, bool pending)
> +{
> +uint32_t sourcecfg, sm;
> +
>
+addr |= (uint64_t)(guest_idx & APLIC_xMSICFGADDR_PPN_HART(lhxs));
> +addr <<= APLIC_xMSICFGADDR_PPN_SHIFT;
> +
> +address_space_stl_le(&address_space_memory, addr,
> + eiid, MEMTXATTRS_UNSPECIFIED, &result);
> +if (result != M
with priority
number p.
For a major interrupt that defaults to a higher priority than machine
external interrupts,
setting its priority number to a nonzero value lowers its priority.
For a major interrupt that defaults to a lower priority than machine
external interrupts,
setting its p
io = IPRIO_DEFAULT_VS;
> +} else if (irq == IRQ_S_GEXT) {
> +iprio = IPRIO_DEFAULT_SGEXT;
> +} else if (irq == IRQ_S_EXT || irq == IRQ_S_TIMER ||
> + irq == IRQ_S_SOFT) {
> +iprio = IPRIO_DEFAULT_S;
> +} else if (irq == IRQ_M
nd VS-Level High-Half CSRs (H-extension with AIA) */
> [CSR_HIDELEGH]= { "hidelegh",aia_hmode32, NULL, NULL,
> rmw_hidelegh },
> +[CSR_HVIENH] = { "hvienh", aia_hmode32, read_zero,
> write_ignore },
> [CSR_HVIPH] = { "hviph", aia_hmode32, NULL, NULL,
> rmw_hviph },
> [CSR_HVIPRIO1H] = { "hviprio1h", aia_hmode32, read_hviprio1h,
> write_hviprio1h },
> [CSR_HVIPRIO2H] = { "hviprio2h", aia_hmode32, read_hviprio2h,
> write_hviprio2h },
> --
> 2.25.1
>
>
>
Reviewed-by: Frank Chang
On Wed, Jan 12, 2022 at 1:18 AM Anup Patel wrote:
>
>
> On Mon, Jan 10, 2022 at 6:38 PM Frank Chang
> wrote:
> >
> > Anup Patel 於 2021年12月30日 週四 下午8:38寫道：
> >>
> >> From: Anup Patel
> >>
> >> The AIA spec defines programmable 8-bit
* Supervisor Protection and Translation */
> [CSR_SATP] = { "satp", smode, read_satp,write_satp },
>
> +/* Supervisor-Level Interrupts (AIA) */
> +[CSR_STOPI] = { "stopi", aia_smode, read_stopi },
> +
> /* Supervisor-Level High-Half CSRs (AIA) */
> [CSR_SIEH] = { "sieh", aia_smode32, NULL, NULL, rmw_sieh },
> [CSR_SIPH] = { "siph", aia_smode32, NULL, NULL, rmw_siph },
> @@ -2454,6 +2607,9 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
> [CSR_HVIPRIO1]= { "hviprio1",aia_hmode, read_hviprio1,
> write_hviprio1 },
> [CSR_HVIPRIO2]= { "hviprio2",aia_hmode, read_hviprio2,
> write_hviprio2 },
>
> +/* VS-Level Interrupts (H-extension with AIA) */
> +[CSR_VSTOPI] = { "vstopi", aia_hmode, read_vstopi },
> +
> /* Hypervisor and VS-Level High-Half CSRs (H-extension with AIA) */
> [CSR_HIDELEGH]= { "hidelegh",aia_hmode32, NULL, NULL,
> rmw_hidelegh },
> [CSR_HVIENH] = { "hvienh", aia_hmode32, read_zero,
> write_ignore },
> --
> 2.25.1
>
>
>
Reviewed-by: Frank Chang
if (riscv_cpu_virt_enabled(env)) {
> +if (!riscv_cpu_virt_enabled(env)) {
> return RISCV_EXCP_ILLEGAL_INST;
> } else {
> return RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
> --
> 2.25.1
>
>
>
Reviewed-by: Frank Chang
> --- a/target/riscv/cpu.h
> +++ b/target/riscv/cpu.h
> @@ -75,7 +75,8 @@ enum {
> RISCV_FEATURE_MMU,
> RISCV_FEATURE_PMP,
> RISCV_FEATURE_EPMP,
> -RISCV_FEATURE_MISA
> +RISCV_FEATURE_MISA,
> +RISCV_FEATURE_AIA
> };
>
> #define PRIV_VERSION_1_10_0 0x00011000
> --
> 2.25.1
>
>
>
Reviewed-by: Frank Chang
> 2))
> +#define IPRIO_DEFAULT_48_63(_i)\
> +(IPRIO_DEFAULT_MMAXIPRIO - (8 + (IPRIO_DEFAULT_L(_i) >> 2)))
> +
> +/* HVICTL bits (AIA) */
> +#define HVICTL_VTI 0x4000
> +#define HVICTL_IID 0x0fff
> +#define HVICTL_IPRIOM 0x0100
> +#define HVICTL_IPRIO 0x00ff
> +#define HVICTL_VALID_MASK \
> +(HVICTL_VTI | HVICTL_IID | HVICTL_IPRIOM | HVICTL_IPRIO)
> +
> #endif
> --
> 2.25.1
>
>
>
Reviewed-by: Frank Chang
c..1bdd03731f 100644
> --- a/target/riscv/cpu.h
> +++ b/target/riscv/cpu.h
> @@ -344,6 +344,11 @@ static inline bool riscv_feature(CPURISCVState *env,
> int feature)
> return env->features & (1ULL << feature);
> }
>
> +static inline void riscv_set_feature(CPURISCVState *env, int feature)
> +{
> +env->features |= (1ULL << feature);
> +}
> +
> #include "cpu_user.h"
>
> extern const char * const riscv_int_regnames[];
> --
> 2.25.1
>
>
>
Reviewed-by: Frank Chang
k),
> + void *rmw_fn_arg)
> +{
> +if (priv <= PRV_M) {
> +env->aia_ireg_rmw_fn[priv] = rmw_fn;
> +env->aia_ireg_rmw_fn_arg[priv] = rmw_fn_arg;
> +}
> +}
> +
> void riscv_cpu_set_mode(CPURISCVState *env, target_ulong newpriv)
> {
> if (newpriv > PRV_M) {
> --
> 2.25.1
>
>
>
Reviewed-by: Frank Chang
define VIRT_CPUS_MAX_BITS 3
> +#define VIRT_CPUS_MAX_BITS 9
> #define VIRT_CPUS_MAX (1 << VIRT_CPUS_MAX_BITS)
> #define VIRT_SOCKETS_MAX_BITS 2
> #define VIRT_SOCKETS_MAX (1 << VIRT_SOCKETS_MAX_BITS)
> --
> 2.25.1
>
>
>
Reviewed-by: Frank Chang
egh },
> [CSR_HVIPH] = { "hviph", aia_hmode32, NULL, NULL,
> rmw_hviph },
> +[CSR_HVIPRIO1H] = { "hviprio1h", aia_hmode32, read_hviprio1h,
> write_hviprio1h },
> +[CSR_HVIPRIO2H] = { "hviprio2h", aia_hmode32, read_hviprio2h,
> write_hviprio2h },
> [CSR_VSIEH] = { "vsieh", aia_hmode32, NULL, NULL,
> rmw_vsieh },
> [CSR_VSIPH] = { "vsiph", aia_hmode32, NULL, NULL,
> rmw_vsiph },
>
> diff --git a/target/riscv/machine.c b/target/riscv/machine.c
> index 44dca84ded..f027d5e307 100644
> --- a/target/riscv/machine.c
> +++ b/target/riscv/machine.c
> @@ -92,6 +92,8 @@ static const VMStateDescription vmstate_hyper = {
> VMSTATE_UINTTL(env.hgeie, RISCVCPU),
> VMSTATE_UINTTL(env.hgeip, RISCVCPU),
> VMSTATE_UINT64(env.htimedelta, RISCVCPU),
> +
> +VMSTATE_UINTTL(env.hvictl, RISCVCPU),
> VMSTATE_UINT8_ARRAY(env.hviprio, RISCVCPU, 64),
>
> VMSTATE_UINT64(env.vsstatus, RISCVCPU),
> --
> 2.25.1
>
>
>
Otherwise,
Reviewed-by: Frank Chang
u.h b/target/riscv/cpu.h
> index 82272f99fd..0b24c4324b 100644
> --- a/target/riscv/cpu.h
> +++ b/target/riscv/cpu.h
> @@ -362,6 +362,7 @@ struct RISCVCPU {
> bool mmu;
> bool pmp;
> bool epmp;
> +bool aia;
> uint64_t resetvec;
> } cfg;
> };
> --
> 2.25.1
>
>
>
Reviewed-by: Frank Chang
ired interrupts.
> +
> +- aia-guests=nnn
> +
> + The number of per-HART VS-level AIA IMSIC pages to be emulated for a
> guest
> + having AIA IMSIC (i.e. "aia=aplic-imsic" selected). When not specified,
> + the default number of per-HART VS-level AIA IMSIC pages is 0.
> +
> Running Linux kernel
>
>
> --
> 2.25.1
>
>
>
Reviewed-by: Frank Chang
NULL,
> rmw_xireg },
> +
> /* VS-Level Interrupts (H-extension with AIA) */
> [CSR_VSTOPI] = { "vstopi", aia_hmode, read_vstopi },
>
> diff --git a/target/riscv/machine.c b/target/riscv/machine.c
> index f027d5e307..376a02a36f 100644
> --- a/target/riscv/machine.c
> +++ b/target/riscv/machine.c
> @@ -103,6 +103,7 @@ static const VMStateDescription vmstate_hyper = {
> VMSTATE_UINTTL(env.vscause, RISCVCPU),
> VMSTATE_UINTTL(env.vstval, RISCVCPU),
> VMSTATE_UINTTL(env.vsatp, RISCVCPU),
> +VMSTATE_UINTTL(env.vsiselect, RISCVCPU),
>
> VMSTATE_UINTTL(env.mtval2, RISCVCPU),
> VMSTATE_UINTTL(env.mtinst, RISCVCPU),
> @@ -210,6 +211,8 @@ const VMStateDescription vmstate_riscv_cpu = {
> VMSTATE_UINTTL(env.mepc, RISCVCPU),
> VMSTATE_UINTTL(env.mcause, RISCVCPU),
> VMSTATE_UINTTL(env.mtval, RISCVCPU),
> +VMSTATE_UINTTL(env.miselect, RISCVCPU),
> +VMSTATE_UINTTL(env.siselect, RISCVCPU),
> VMSTATE_UINTTL(env.scounteren, RISCVCPU),
> VMSTATE_UINTTL(env.mcounteren, RISCVCPU),
> VMSTATE_UINTTL(env.sscratch, RISCVCPU),
> --
> 2.25.1
>
>
>
Reviewed-by: Frank Chang
);
> +} else {
> +qemu_fdt_setprop_string(mc->fdt, intc_name, "compatible",
> +"riscv,cpu-intc");
> +}
> qemu_fdt_setprop(mc->fdt, intc_name, "interrupt-controller",
> NULL, 0);
> qemu_fdt_setprop_cell(mc->fdt, intc_name, "#interrupt-cells", 1);
>
> --
> 2.25.1
>
>
>
Reviewed-by: Frank Chang
Anup Patel 於 2021年12月30日 週四 下午9:00寫道：
> From: Anup Patel
>
> The RISC-V AIA (Advanced Interrupt Architecture) defines a new
> interrupt controller for MSIs (message signal interrupts) called
> IMSIC (Incoming Message Signal Interrupt Controller). The IMSIC
> is per-HART device and also suppport
uggish response to serial console input and other I/O
> events.
> +*
> +* To solve this, we check and inject interrupt after setting V=1.
> +*/
> +riscv_cpu_update_mip(env_archcpu(env), 0, 0);
> +}
> }
>
> bool riscv_cpu_two_stage_lookup(int mmu_idx)
> --
> 2.25.1
>
>
>
Reviewed-by: Frank Chang
On Thu, Jan 13, 2022 at 6:45 PM Anup Patel wrote:
> On Wed, Jan 12, 2022 at 8:30 AM Frank Chang
> wrote:
> >
> > On Wed, Jan 12, 2022 at 1:18 AM Anup Patel wrote:
> >>
> >>
> >>
> >> On Mon, Jan 10, 2022 at 6:38 PM Frank Chang
> w
tion rmw_hip(CPURISCVState *env,
> int csrno,
> static RISCVException read_hie(CPURISCVState *env, int csrno,
> target_ulong *val)
> {
> -*val = env->mie & VS_MODE_INTERRUPTS;
> +*val = env->mie & HS_MODE_INTERRUPTS;
> return RISCV_EXCP_NONE;
> }
>
> static RISCVException write_hie(CPURISCVState *env, int csrno,
> target_ulong val)
> {
> -target_ulong newval = (env->mie & ~VS_MODE_INTERRUPTS) | (val &
> VS_MODE_INTERRUPTS);
> +target_ulong newval = (env->mie & ~HS_MODE_INTERRUPTS) | (val &
> HS_MODE_INTERRUPTS);
> return write_mie(env, CSR_MIE, newval);
> }
>
> --
> 2.25.1
>
>
>
Reviewed-by: Frank Chang
[CSR_HTVAL] = { "htval", hmode, read_htval,
> write_htval },
> [CSR_HTINST] = { "htinst", hmode, read_htinst,
> write_htinst },
> -[CSR_HGEIP] = { "hgeip", hmode, read_zero,
> write_hgeip },
> +[CSR_HGEIP] = { "hgeip", hmode, read_hgeip, NULL
> },
> [CSR_HGATP] = { "hgatp", hmode, read_hgatp,
> write_hgatp },
> [CSR_HTIMEDELTA] = { "htimedelta", hmode, read_htimedelta,
> write_htimedelta },
> [CSR_HTIMEDELTAH] = { "htimedeltah", hmode32, read_htimedeltah,
> write_htimedeltah },
> diff --git a/target/riscv/machine.c b/target/riscv/machine.c
> index ad8248ebfd..76dd0d415c 100644
> --- a/target/riscv/machine.c
> +++ b/target/riscv/machine.c
> @@ -78,8 +78,8 @@ static bool hyper_needed(void *opaque)
>
> static const VMStateDescription vmstate_hyper = {
> .name = "cpu/hyper",
> -.version_id = 1,
> -.minimum_version_id = 1,
> +.version_id = 2,
> +.minimum_version_id = 2,
> .needed = hyper_needed,
> .fields = (VMStateField[]) {
> VMSTATE_UINTTL(env.hstatus, RISCVCPU),
> @@ -89,6 +89,8 @@ static const VMStateDescription vmstate_hyper = {
> VMSTATE_UINTTL(env.htval, RISCVCPU),
> VMSTATE_UINTTL(env.htinst, RISCVCPU),
> VMSTATE_UINTTL(env.hgatp, RISCVCPU),
> +VMSTATE_UINTTL(env.hgeie, RISCVCPU),
> +VMSTATE_UINTTL(env.hgeip, RISCVCPU),
> VMSTATE_UINT64(env.htimedelta, RISCVCPU),
>
> VMSTATE_UINT64(env.vsstatus, RISCVCPU),
> --
> 2.25.1
>
>
>
Reviewed-by: Frank Chang
leg", hmode, read_hedeleg,
> write_hedeleg },
> -[CSR_HIDELEG] = { "hideleg", hmode, read_hideleg,
> write_hideleg },
> +[CSR_HIDELEG] = { "hideleg", hmode, NULL, NULL,
> rmw_hideleg },
> [CSR_HVIP]= { "hvip",hmode, NULL, NULL,
> rmw_hvip },
> [CSR_HIP] = { "hip", hmode, NULL, NULL,
> rmw_hip },
> -[CSR_HIE] = { "hie", hmode, read_hie,
> write_hie },
> +[CSR_HIE] = { "hie", hmode, NULL, NULL,
> rmw_hie },
> [CSR_HCOUNTEREN] = { "hcounteren", hmode, read_hcounteren,
> write_hcounteren },
> [CSR_HGEIE] = { "hgeie", hmode, read_hgeie,
> write_hgeie },
> [CSR_HTVAL] = { "htval", hmode, read_htval,
> write_htval },
> @@ -1949,7 +2297,7 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
>
> [CSR_VSSTATUS]= { "vsstatus",hmode, read_vsstatus,
> write_vsstatus},
> [CSR_VSIP]= { "vsip",hmode, NULL,NULL,
> rmw_vsip },
> -[CSR_VSIE]= { "vsie",hmode, read_vsie,
> write_vsie},
> +[CSR_VSIE]= { "vsie",hmode, NULL,NULL,
> rmw_vsie },
> [CSR_VSTVEC] = { "vstvec", hmode, read_vstvec,
> write_vstvec },
> [CSR_VSSCRATCH] = { "vsscratch", hmode, read_vsscratch,
> write_vsscratch },
> [CSR_VSEPC] = { "vsepc", hmode, read_vsepc,
> write_vsepc },
> @@ -1960,6 +2308,12 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
> [CSR_MTVAL2] = { "mtval2", hmode, read_mtval2,
> write_mtval2 },
> [CSR_MTINST] = { "mtinst", hmode, read_mtinst,
> write_mtinst },
>
> +/* Hypervisor and VS-Level High-Half CSRs (H-extension with AIA) */
> +[CSR_HIDELEGH]= { "hidelegh",aia_hmode32, NULL, NULL,
> rmw_hidelegh },
> +[CSR_HVIPH] = { "hviph", aia_hmode32, NULL, NULL,
> rmw_hviph },
> +[CSR_VSIEH] = { "vsieh", aia_hmode32, NULL, NULL,
> rmw_vsieh },
> +[CSR_VSIPH] = { "vsiph", aia_hmode32, NULL, NULL,
> rmw_vsiph },
> +
> /* Physical Memory Protection */
> [CSR_MSECCFG]= { "mseccfg", epmp, read_mseccfg, write_mseccfg },
> [CSR_PMPCFG0]= { "pmpcfg0", pmp, read_pmpcfg, write_pmpcfg },
> diff --git a/target/riscv/machine.c b/target/riscv/machine.c
> index cffc444969..44dca84ded 100644
> --- a/target/riscv/machine.c
> +++ b/target/riscv/machine.c
> @@ -84,7 +84,7 @@ static const VMStateDescription vmstate_hyper = {
> .fields = (VMStateField[]) {
> VMSTATE_UINTTL(env.hstatus, RISCVCPU),
> VMSTATE_UINTTL(env.hedeleg, RISCVCPU),
> -VMSTATE_UINTTL(env.hideleg, RISCVCPU),
> +VMSTATE_UINT64(env.hideleg, RISCVCPU),
> VMSTATE_UINTTL(env.hcounteren, RISCVCPU),
> VMSTATE_UINTTL(env.htval, RISCVCPU),
> VMSTATE_UINTTL(env.htinst, RISCVCPU),
> @@ -194,10 +194,10 @@ const VMStateDescription vmstate_riscv_cpu = {
> VMSTATE_UINTTL(env.resetvec, RISCVCPU),
> VMSTATE_UINTTL(env.mhartid, RISCVCPU),
> VMSTATE_UINT64(env.mstatus, RISCVCPU),
> -VMSTATE_UINTTL(env.mip, RISCVCPU),
> -VMSTATE_UINT32(env.miclaim, RISCVCPU),
> -VMSTATE_UINTTL(env.mie, RISCVCPU),
> -VMSTATE_UINTTL(env.mideleg, RISCVCPU),
> +VMSTATE_UINT64(env.mip, RISCVCPU),
> +VMSTATE_UINT64(env.miclaim, RISCVCPU),
> +VMSTATE_UINT64(env.mie, RISCVCPU),
> +VMSTATE_UINT64(env.mideleg, RISCVCPU),
> VMSTATE_UINTTL(env.satp, RISCVCPU),
> VMSTATE_UINTTL(env.stval, RISCVCPU),
> VMSTATE_UINTTL(env.medeleg, RISCVCPU),
> --
> 2.25.1
>
>
>
Reviewed-by: Frank Chang
From: Frank Chang
Add Xilinx AXI CDMA model, which follows
AXI Central Direct Memory Access v4.1 spec:
https://docs.xilinx.com/v/u/en-US/pg034-axi-cdma
Supports both Simple DMA and Scatter Gather modes.
Signed-off-by: Frank Chang
Reviewed-by: Jim Shu
---
hw/dma/meson.build
Reviewed-by: Frank Chang
On Fri, Apr 29, 2022 at 11:41 PM Anup Patel wrote:
> The riscv_cpu_realize() sets priv spec verion to v1.12 when it is
> when "env->priv_ver == 0" (i.e. default v1.10) because the enum
> value of priv spec v1.10 is zero.
>
> Due to above
the one in which the
extension is supported.
(This is possible if user specifies the privileged spec version through the
command line.)
The ISA string therefore won't include the enabled extension.
Regards,
Frank Chang
On Fri, Apr 29, 2022 at 11:49 PM Anup Patel wrote:
> Most o
Reviewed-by: Frank Chang
On Fri, Apr 29, 2022 at 11:44 PM Anup Patel wrote:
> The mcountinhibit CSR is mandatory for priv spec v1.11 or higher. For
> implementation that don't want to implement can simply have a dummy
> mcountinhibit which always zero.
>
> Fixes: a4b2fa4
Reviewed-by: Frank Chang
On Fri, Apr 29, 2022 at 11:36 AM Anup Patel wrote:
> Currently, the [m|s]tval CSRs are set with trapping instruction encoding
> only for illegal instruction traps taken at the time of instruction
> decoding.
>
> In RISC-V world, a valid instructions mig
Reviewed-by: Frank Chang
On Fri, Apr 29, 2022 at 11:34 AM Anup Patel wrote:
> When hypervisor and VS CSRs are accessed from VS-mode or VU-mode,
> the riscv_csrrw_check() function should generate virtual instruction
> trap instead illegal instruction trap.
>
> Fixes: 533c91e8f22c
On Sat, Apr 30, 2022 at 12:30 PM Anup Patel wrote:
> On Sat, Apr 30, 2022 at 8:39 AM Frank Chang
> wrote:
> >
> > Hi Anup,
> >
> > If we want to limit the generated ISA string to/after a specific
> privilege spec version.
> > Shouldn't we also
On Mon, May 2, 2022 at 6:29 PM Edgar E. Iglesias
wrote:
> On Thu, Apr 28, 2022 at 5:43 PM wrote:
>
>> From: Frank Chang
>>
>> Add Xilinx AXI CDMA model, which follows
>> AXI Central Direct Memory Access v4.1 spec:
>> https://docs.xilinx.com/v/u/en-US/pg034
On Tue, May 3, 2022 at 5:35 PM Edgar E. Iglesias
wrote:
> On Tue, May 3, 2022 at 3:16 AM Frank Chang wrote:
>
>> On Mon, May 2, 2022 at 6:29 PM Edgar E. Iglesias <
>> edgar.igles...@gmail.com> wrote:
>>
>>> On Thu, Apr 28, 2022 at 5:43 PM wrote:
>>&
Hi Anup,
I found that Atish has already submitted a patch to implement the
mcountinhibit CSR:
https://www.mail-archive.com/qemu-devel@nongnu.org/msg879349.html
Regards,
Frank Chang
On Fri, Apr 29, 2022 at 11:44 PM Anup Patel wrote:
> The mcountinhibit CSR is mandatory for priv spec v1.11
On Thu, May 5, 2022 at 4:50 AM Edgar E. Iglesias
wrote:
>
> On Tue, May 3, 2022 at 7:12 PM Edgar E. Iglesias
> wrote:
>
>> On Tue, May 3, 2022 at 5:06 PM Frank Chang
>> wrote:
>>
>>> On Tue, May 3, 2022 at 5:35 PM Edgar E. Iglesias <
>>> edga
Reviewed-by: Frank Chang
On Wed, Aug 17, 2022 at 11:32 PM Yang Liu wrote:
> Remove duplicate code by wrapping vfwredsum_vs's OP function.
>
> Signed-off-by: Yang Liu
> ---
> target/riscv/vector_helper.c | 56 +++-
> 1 file change
Reviewed-by: Frank Chang
On Wed, Aug 17, 2022 at 11:45 PM Yang Liu wrote:
> Starting with RVV1.0, the original vf[w]redsum_vs instruction was renamed
> to vf[w]redusum_vs. The distinction between ordered and unordered is also
> more consistent with other instructions, although th
Reviewed-by: Frank Chang
On Thu, Sep 22, 2022 at 4:42 PM Tommy Wu wrote:
> Add some simple tests of the watchdog timer in the always-on domain device
> of HiFive 1 rev b.
>
> Signed-off-by: Tommy Wu
> ---
> tests/qtest/meson.build | 3 +
> tests/qtest/
Reviewed-by: Frank Chang
On Thu, Sep 22, 2022 at 4:41 PM Tommy Wu wrote:
> The watchdog timer is in the always-on domain device of HiFive 1 rev b,
> so this patch added the AON device to the sifive_e machine. This patch
> only implemented the functionality of the watchdog timer.
>
Reviewed-by: Frank Chang
On Thu, Sep 22, 2022 at 4:41 PM Tommy Wu wrote:
> Create the AON device when we realize the sifive_e machine.
> This patch only implemented the functionality of the watchdog timer,
> not all the functionality of the AON device.
>
> Signed-off-by: Tommy
Reviewed-by: Frank Chang
On Wed, Sep 14, 2022 at 6:12 PM Alistair Francis via
wrote:
> Instead of using our properties to set a config value which then might
> be used to set the resetvec (depending on your timing), let's instead
> just set the resetvec directly in the env st
From: Frank Chang
Replace type2_trigger_t with the real tdata1, tdata2, and tdata3 CSRs,
which allows us to support more types of triggers in the future.
Signed-off-by: Frank Chang
---
target/riscv/cpu.h | 6 ++-
target/riscv/debug.c | 101
From: Frank Chang
This patchset refactors RISC-V Debug support to allow more types of
triggers to be extended.
The initial support of type 6 trigger, which is similar to type 2
trigger with additional functionality, is also introduced in this
patchset.
Frank Chang (9):
target/riscv: debug
From: Frank Chang
The value of tselect CSR can be written should be limited within the
range of supported triggers number.
Signed-off-by: Frank Chang
---
target/riscv/debug.c | 9 +++--
1 file changed, 3 insertions(+), 6 deletions(-)
diff --git a/target/riscv/debug.c b/target/riscv
From: Frank Chang
Introduce build_tdata1() to build tdata1 register content, which can be
shared among all types of triggers.
Signed-off-by: Frank Chang
---
target/riscv/debug.c | 15 ++-
1 file changed, 10 insertions(+), 5 deletions(-)
diff --git a/target/riscv/debug.c b/target
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