Anup Patel <a...@brainfault.org> 於 2021年12月30日 週四 下午8:57寫道：
> From: Anup Patel <anup.pa...@wdc.com>
>
> We add "x-aia" command-line option for RISC-V HART using which
> allows users to force enable CPU AIA CSRs without changing the
> interrupt controller available in RISC-V machine.
>
> Signed-off-by: Anup Patel <anup.pa...@wdc.com>
> Signed-off-by: Anup Patel <a...@brainfault.org>
> Reviewed-by: Alistair Francis <alistair.fran...@wdc.com>
> ---
> target/riscv/cpu.c | 5 +++++
> target/riscv/cpu.h | 1 +
> 2 files changed, 6 insertions(+)
>
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index 9ad26035e1..1ae9e15b27 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -463,6 +463,10 @@ static void riscv_cpu_realize(DeviceState *dev, Error
> **errp)
> }
> }
>
> + if (cpu->cfg.aia) {
> + riscv_set_feature(env, RISCV_FEATURE_AIA);
> + }
> +
> set_resetvec(env, cpu->cfg.resetvec);
>
> /* Validate that MISA_MXL is set properly. */
> @@ -691,6 +695,7 @@ static Property riscv_cpu_properties[] = {
> DEFINE_PROP_BOOL("x-j", RISCVCPU, cfg.ext_j, false),
> /* ePMP 0.9.3 */
> DEFINE_PROP_BOOL("x-epmp", RISCVCPU, cfg.epmp, false),
> + DEFINE_PROP_BOOL("x-aia", RISCVCPU, cfg.aia, false),
>
> DEFINE_PROP_UINT64("resetvec", RISCVCPU, cfg.resetvec,
> DEFAULT_RSTVEC),
> DEFINE_PROP_END_OF_LIST(),
> diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
> index 82272f99fd..0b24c4324b 100644
> --- a/target/riscv/cpu.h
> +++ b/target/riscv/cpu.h
> @@ -362,6 +362,7 @@ struct RISCVCPU {
> bool mmu;
> bool pmp;
> bool epmp;
> + bool aia;
> uint64_t resetvec;
> } cfg;
> };
> --
> 2.25.1
>
>
>
Reviewed-by: Frank Chang <frank.ch...@sifive.com>
