trng_generate(true);
> +n = trng_collect(prng, cnt);
> +g_assert_cmpuint(n, ==, cnt);
> +
> +/* #2: zero string should match personalization disabled */
> +trng_load(R_TRNG_PER_STRNG_0, NULL);
> +trng_reseed(prng_seed);
> +
> +trng_generate(tr
On [2023 Oct 04] Wed 07:27:46, Tong Ho wrote:
> Signed-off-by: Tong Ho
Reviewed-by: Francisco Iglesias
> ---
> tests/qtest/meson.build | 2 +-
> tests/qtest/xlnx-versal-trng-test.c | 490
> 2 files changed, 491 insertions(+), 1 deleti
s not intended for use cases when
> cryptograpically strong TRNG is needed.
>
> Signed-off-by: Tong Ho
Reviewed-by: Francisco Iglesias
> ---
> hw/arm/Kconfig | 1 +
> hw/arm/xlnx-versal.c | 16
> include/hw/arm/xlnx-versal.h | 5
On [2023 Oct 03] Tue 22:57:13, Tong Ho wrote:
> This change implements the ResettableClass interface for the device.
>
> Signed-off-by: Tong Ho
Reviewed-by: Francisco Iglesias
> ---
> hw/nvram/xlnx-zynqmp-efuse.c | 8 +---
> 1 file changed, 5 insertions(+), 3 deletions(
On [2023 Oct 03] Tue 22:53:39, Tong Ho wrote:
> This change implements the ResettableClass interface for the device.
>
> Signed-off-by: Tong Ho
Reviewed-by: Francisco Iglesias
> ---
> hw/nvram/xlnx-versal-efuse-ctrl.c | 8 +---
> 1 file changed, 5 insertions(+), 3 dele
On [2023 Oct 02] Mon 22:21:39, Tong Ho wrote:
> This replaces the comma (,) to dot (.) in the device type name
> so the name can be used with the 'driver=' command line option.
>
> Signed-off-by: Tong Ho
Reviewed-by: Francisco Iglesias
> ---
> include/hw/nvram/x
with connecting the models to Xilinx Versal
machine.
Best regards,
Francisco Iglesias
References:
[1] https://docs.xilinx.com/r/en-US/am011-versal-acap-trm/PSM-Local-Registers
Changelog:
v1->v2:
[PATCH 2]
* Use KiB when defining KEYHOLE_STREAM_4K/KEYHOLE_STREAM_256K
* Updated to be able
emulating bitstream programming and readback).
Signed-off-by: Francisco Iglesias
Reviewed-by: Sai Pavan Boddu
Acked-by: Edgar E. Iglesias
---
MAINTAINERS | 6
hw/misc/meson.build | 1 +
hw/misc/xlnx-cfi-if.c | 34
include/hw/misc/xlnx
Introduce a model of the software programming interface (CFU_APB) of
Xilinx Versal's Configuration Frame Unit.
Signed-off-by: Francisco Iglesias
---
MAINTAINERS | 2 +
hw/misc/meson.build | 1 +
hw/misc/xlnx-versal-cfu.c
Introduce a model of Xilinx Versal's Configuration Frame Unit's Single
Frame Read port (CFU_SFR).
Signed-off-by: Francisco Iglesias
---
hw/misc/xlnx-versal-cfu.c | 87 +++
include/hw/misc/xlnx-versal-cfu.h | 15 ++
2 files changed, 102 insertion
Introduce a model of Xilinx Versal's Configuration Frame broadcast
controller (CFRAME_BCAST_REG).
Signed-off-by: Francisco Iglesias
---
hw/misc/xlnx-versal-cframe-reg.c | 161 +++
include/hw/misc/xlnx-versal-cframe-reg.h | 17 +++
2 files changed, 178 inser
Connect the Configuration Frame Unit (CFU_APB, CFU_FDRO and CFU_SFR) to
the Versal machine.
Signed-off-by: Francisco Iglesias
Acked-by: Edgar E. Iglesias
Reviewed-by: Peter Maydell
---
hw/arm/xlnx-versal.c | 42
include/hw/arm/xlnx-versal.h | 16
Connect the Configuration Frame controller (CFRAME_REG) and the
Configuration Frame broadcast controller (CFRAME_BCAST_REG) to the
Versal machine.
Signed-off-by: Francisco Iglesias
---
hw/arm/xlnx-versal.c | 113 ++-
include/hw/arm/xlnx-versal.h | 69
Introduce a model of Xilinx Versal's Configuration Frame Unit's data out
port (CFU_FDRO).
Signed-off-by: Francisco Iglesias
---
hw/misc/xlnx-versal-cfu.c | 96 +++
include/hw/misc/xlnx-versal-cfu.h | 12
2 files changed, 108 insertions(+)
di
Introduce a model of Xilinx Versal's Configuration Frame controller
(CFRAME_REG).
Signed-off-by: Francisco Iglesias
---
MAINTAINERS | 2 +
hw/misc/meson.build | 1 +
hw/misc/xlnx-versal-cframe-reg.c
Hi Peter,
On 2023-08-03 15:48, Peter Maydell wrote:
On Mon, 10 Jul 2023 at 15:03, Francisco Iglesias
wrote:
Introduce a model of Xilinx Versal's Configuration Frame Unit's data out
port (CFU_FDRO).
Signed-off-by: Francisco Iglesias
---
hw/misc/xlnx-versal-cfu.c
size-checked (e.g. CVE-2021-3527).
>
> Signed-off-by: Philippe Mathieu-Daudé
> [PMM: expanded commit message]
> Signed-off-by: Peter Maydell
Reviewed-by: Francisco Iglesias
> ---
> block/vpc.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> dif
27;t correctly size-checked (e.g. CVE-2021-3527).
>
> Signed-off-by: Peter Maydell
Reviewed-by: Francisco Iglesias
> ---
> audio/jackaudio.c | 5 +++--
> 1 file changed, 3 insertions(+), 2 deletions(-)
>
> diff --git a/audio/jackaudio.c b/audio/jackaudio.c
> index 5bd
w additions. This is a defensive
> measure against security bugs where an on-stack dynamic allocation
> isn't correctly size-checked (e.g. CVE-2021-3527).
>
> Signed-off-by: Philippe Mathieu-Daudé
> [PMM: expanded commit message]
> Signed-off-by: Peter Maydell
Reviewed-
s very few VLAs, and if we can get rid of them all we
> can make the compiler error on new additions. This is a defensive
> measure against security bugs where an on-stack dynamic allocation
> isn't correctly size-checked (e.g. CVE-2021-3527).
>
> Signed-off-by: Peter Maydel
Introduce a model of Xilinx Versal's Configuration Frame Unit's Single
Frame Read port (CFU_SFR).
Signed-off-by: Francisco Iglesias
---
hw/misc/xlnx-versal-cfu.c | 88 +++
include/hw/misc/xlnx-versal-cfu.h | 15 ++
2 files changed, 103 insertion
Introduce a model of Xilinx Versal's Configuration Frame broadcast
controller (CFRAME_BCAST_REG).
Signed-off-by: Francisco Iglesias
---
hw/misc/xlnx-versal-cframe-reg.c | 173 +++
include/hw/misc/xlnx-versal-cframe-reg.h | 17 +++
2 files changed, 190 inser
Introduce a model of the software programming interface (CFU_APB) of
Xilinx Versal's Configuration Frame Unit.
Signed-off-by: Francisco Iglesias
---
MAINTAINERS | 2 +
hw/misc/meson.build | 1 +
hw/misc/xlnx-versal-cfu.c
Connect the Configuration Frame controller (CFRAME_REG) and the
Configuration Frame broadcast controller (CFRAME_BCAST_REG) to the
Versal machine.
Signed-off-by: Francisco Iglesias
---
hw/arm/xlnx-versal.c | 116 ++-
include/hw/arm/xlnx-versal.h | 69
emulating bitstream programming and readback).
Signed-off-by: Francisco Iglesias
---
MAINTAINERS | 6
hw/misc/meson.build | 1 +
hw/misc/xlnx-cfi-if.c | 34
include/hw/misc/xlnx-cfi-if.h | 59 +++
4 files
Introduce a model of Xilinx Versal's Configuration Frame controller
(CFRAME_REG).
Signed-off-by: Francisco Iglesias
---
MAINTAINERS | 2 +
hw/misc/meson.build | 1 +
hw/misc/xlnx-versal-cframe-reg.c
Connect the Configuration Frame Unit (CFU_APB, CFU_FDRO and CFU_SFR) to
the Versal machine.
Signed-off-by: Francisco Iglesias
---
hw/arm/xlnx-versal.c | 42
include/hw/arm/xlnx-versal.h | 16 ++
2 files changed, 58 insertions(+)
diff
Introduce a model of Xilinx Versal's Configuration Frame Unit's data out
port (CFU_FDRO).
Signed-off-by: Francisco Iglesias
---
hw/misc/xlnx-versal-cfu.c | 105 ++
include/hw/misc/xlnx-versal-cfu.h | 11
2 files changed, 116 insertions(+)
di
with connecting the models to Xilinx Versal
machine.
Best regards,
Francisco Iglesias
References:
[1] https://docs.xilinx.com/r/en-US/am011-versal-acap-trm/PSM-Local-Registers
Francisco Iglesias (8):
hw/misc: Introduce the Xilinx CFI interface
hw/misc: Introduce a model of Xilinx Versal&#
+PMM (I think this one might have fallen throught the cracks)
Best regards,
Francisco Iglesias
On [2023 Jun 18] Sun 00:50:47, Philippe Mathieu-Daudé wrote:
> On 16/6/23 16:38, Kinsey Moore wrote:
> > The Cadence GEM peripherals as configured for Zynq MPSoC and Versal
> > pla
Hi Kinsey,
On [2023 Jun 15] Thu 08:48:47, Kinsey Moore wrote:
> The Cadence GEM peripherals as configured for Zynq MPSoC and Versal
> platforms have two priority queues with separate interrupt sources for
> each. If the interrupt source for the second priority queue is not
> connected, they work i
k in polling mode only. This change connects the
> second interrupt source for platforms where it is available. This patch
> has been tested using the lwIP stack with a Xilinx-supplied driver from
> their embeddedsw repository.
>
> Signed-off-by: Kinsey Moore
Reviewed-by: Francisco
On [2023 Sep 05] Tue 16:56:51, Philippe Mathieu-Daudé wrote:
> Simplify gicv3_class_name() logic. No functional change intended.
>
> Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Francisco Iglesias
> ---
> hw/intc/arm_gicv3_common.c | 9 -
> 1 file changed,
g Liu
> Fixes: 98e5d7a2b7 ("hw/net/can: Introduce Xilinx ZynqMP CAN controller")
> Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1425
> Signed-off-by: Philippe Mathieu-Daudé
> Francisco Iglesias
-above line
+below line
Reviewed-by: Francisco Iglesias
> ---
&
tps://gitlab.com/qemu-project/qemu/-/issues/1427
> Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Francisco Iglesias
> ---
> hw/net/can/xlnx-zynqmp-can.c | 17 +
> 1 file changed, 9 insertions(+), 8 deletions(-)
>
> diff --git a/hw/net/can/xlnx-zynqmp-can.c b
bytes for zynqmp-qspips) thus it is possible to write
out of s->regs[addr] in xilinx_spips_write for spips and qspips.
This fixes that wrong behavior.
Reviewed-by: Luc Michel
Signed-off-by: Frederic Konrad
Reviewed-by: Francisco Iglesias
---
hw/ssi/xilinx_spips.c
On 2023-11-24 15:35, Frederic Konrad wrote:
It seems that the url changed a bit, and it triggers an error. Fix the URLs so
the documentation can be reached again.
Signed-off-by: Frederic Konrad
Reviewed-by: Francisco Iglesias
---
hw/dma/xlnx_csu_dma.c | 2
SIZE register, so remove the LOG_GUEST_ERROR in that case.
While at it remove the comment marking the SIZE register as write-only.
See:
https://docs.xilinx.com/r/en-US/ug1087-zynq-ultrascale-registers/CSUDMA_SRC_SIZE-CSUDMA-Register
Signed-off-by: Frederic Konrad
Reviewed-by: Francisco Iglesias
> the memory region.
>
> Signed-off-by: Sai Pavan Boddu
Reviewed-by: Francisco Iglesias
Tested-by: Francisco Iglesias
> ---
> hw/ssi/xlnx-versal-ospi.c | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/hw/ssi/xlnx-versal-ospi.c b/hw/ssi/xlnx-versal-ospi.c
>
On [2023 Dec 05] Tue 15:22:26, Sai Pavan Boddu wrote:
> This property allows users to change flash model on command line as
> below.
>
>ex: "-M xlnx-versal-virt,ospi-flash=mt35xu02gbba"
>
> Signed-off-by: Sai Pavan Boddu
Reviewed-by: Francisco Iglesias
> -
On [2023 Dec 05] Tue 15:22:25, Sai Pavan Boddu wrote:
> Add Micro 2Gb OSPI flash part with sfdp data.
>
> Signed-off-by: Sai Pavan Boddu
Reviewed-by: Francisco Iglesias
> ---
> hw/block/m25p80_sfdp.h | 1 +
> hw/block/m25p80.c | 3 +++
> hw/blo
On 2023-11-13 14:43, Markus Armbruster wrote:
Fixes: b65b4b7ae3c8 (xlnx-bbram: hw/nvram: Use dot in device type name)
Signed-off-by: Markus Armbruster
Reviewed-by: Francisco Iglesias
---
docs/system/arm/xlnx-versal-virt.rst | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff
x-FOO", like commit e178113ff64 did.
Reported-by: Thomas Huth
Signed-off-by: Markus Armbruster
Reviewed-by: Francisco Iglesias
---
docs/system/arm/xlnx-versal-virt.rst | 2 +-
include/hw/misc/xlnx-versal-cframe-reg.h | 2 +-
include/hw/misc/xlnx-versal-cfu.h| 6 +++---
incl
bove minor modification:
Reviewed-by: Francisco Iglesias
Best regards,
Francisco
+bool is_txhpb = fifo == &s->txhpb_fifo;
+
+assert(used > 0);
+used %= CAN_FRAME_SIZE;
+
+/*
+ * Frame Message Format
+ *
+ * Each frame includes four words (16 bytes). Software mus
Hi Philippe,
On 2023-11-16 16:44, Philippe Mathieu-Daudé wrote:
Hi Francisco,
On 16/11/23 15:17, Francisco Iglesias wrote:
Hi Philippe, good catch!
Well this was fuzzed by Qiang Liu.
On 2023-11-15 16:17, Philippe Mathieu-Daudé wrote:
Per
https://docs.xilinx.com/r/en-US/ug1085-zynq
Connect the Configuration Frame controller (CFRAME_REG) and the
Configuration Frame broadcast controller (CFRAME_BCAST_REG) to the
Versal machine.
Signed-off-by: Francisco Iglesias
Reviewed-by: Peter Maydell
---
hw/arm/xlnx-versal.c | 113 ++-
include/hw
Introduce a model of Xilinx Versal's Configuration Frame Unit's data out
port (CFU_FDRO).
Signed-off-by: Francisco Iglesias
Reviewed-by: Peter Maydell
---
hw/misc/xlnx-versal-cfu.c | 96 +++
include/hw/misc/xlnx-versal-cfu.h | 12
2 files ch
with connecting the models to Xilinx Versal
machine.
Best regards,
Francisco Iglesias
References:
[1] https://docs.xilinx.com/r/en-US/am011-versal-acap-trm/PSM-Local-Registers
Changelog:
v2->v3:
[PATCH 5]
* Swap to store the CFrames in a GTree instead of GArray
* Rename new_f to new_f_d
Introduce a model of the software programming interface (CFU_APB) of
Xilinx Versal's Configuration Frame Unit.
Signed-off-by: Francisco Iglesias
Reviewed-by: Peter Maydell
---
MAINTAINERS | 2 +
hw/misc/meson.build | 1 +
hw/misc/xlnx-versal-
Introduce a model of Xilinx Versal's Configuration Frame broadcast
controller (CFRAME_BCAST_REG).
Signed-off-by: Francisco Iglesias
Reviewed-by: Peter Maydell
---
hw/misc/xlnx-versal-cframe-reg.c | 161 +++
include/hw/misc/xlnx-versal-cframe-reg.h | 17 +++
2
Introduce a model of Xilinx Versal's Configuration Frame controller
(CFRAME_REG).
Signed-off-by: Francisco Iglesias
---
MAINTAINERS | 2 +
hw/misc/meson.build | 1 +
hw/misc/xlnx-versal-cframe-reg.c
Hi Peter,
On 2023-08-21 15:34, Peter Maydell wrote:
On Thu, 10 Aug 2023 at 20:16, Francisco Iglesias
wrote:
Introduce a model of Xilinx Versal's Configuration Frame controller
(CFRAME_REG).
Signed-off-by: Francisco Iglesias
---
MAINTAINERS | 2 +
hw
emulating bitstream programming and readback).
Signed-off-by: Francisco Iglesias
Reviewed-by: Sai Pavan Boddu
Acked-by: Edgar E. Iglesias
---
MAINTAINERS | 6
hw/misc/meson.build | 1 +
hw/misc/xlnx-cfi-if.c | 34
include/hw/misc/xlnx
Connect the Configuration Frame Unit (CFU_APB, CFU_FDRO and CFU_SFR) to
the Versal machine.
Signed-off-by: Francisco Iglesias
Acked-by: Edgar E. Iglesias
Reviewed-by: Peter Maydell
---
hw/arm/xlnx-versal.c | 42
include/hw/arm/xlnx-versal.h | 16
Introduce a model of Xilinx Versal's Configuration Frame Unit's Single
Frame Read port (CFU_SFR).
Signed-off-by: Francisco Iglesias
Reviewed-by: Peter Maydell
---
hw/misc/xlnx-versal-cfu.c | 87 +++
include/hw/misc/xlnx-versal-cfu.h | 15 +
is a defensive
> measure against security bugs where an on-stack dynamic allocation
> isn't correctly size-checked (e.g. CVE-2021-3527).
>
> Signed-off-by: Peter Maydell
Reviewed-by: Francisco Iglesias
> ---
> hw/net/rocker/rocker_of_dpa.c | 2 +-
> 1 file changed, 1 inse
t; measure against security bugs where an on-stack dynamic allocation
> isn't correctly size-checked (e.g. CVE-2021-3527).
>
> Signed-off-by: Peter Maydell
Reviewed-by: Francisco Iglesias
> ---
> net/tap.c | 3 ++-
> 1 file changed, 2 insertions(+), 1 deletion(-)
>
is a defensive
> measure against security bugs where an on-stack dynamic allocation
> isn't correctly size-checked (e.g. CVE-2021-3527).
>
> Signed-off-by: Peter Maydell
Reviewed-by: Francisco Iglesias
> ---
> net/dump.c | 2 +-
> 1 file changed, 1 insertion(+), 1 delet
Hi Peter,
On 2023-08-29 18:44, Peter Maydell wrote:
On Thu, 24 Aug 2023 at 19:35, Francisco Iglesias
wrote:
Introduce a model of Xilinx Versal's Configuration Frame controller
(CFRAME_REG).
Signed-off-by: Francisco Iglesias
+static void cfrm_fdri_post_write(RegisterInfo *reg, uin
with connecting the models to Xilinx Versal
machine.
Best regards,
Francisco Iglesias
References:
[1] https://docs.xilinx.com/r/en-US/am011-versal-acap-trm/PSM-Local-Registers
Changelog:
v3->v4:
[PATCH 5]
* Swap to pop out the fifo32 data instead of using memcpy
* Use g_tree_nnodes inst
Introduce a model of Xilinx Versal's Configuration Frame Unit's Single
Frame Read port (CFU_SFR).
Signed-off-by: Francisco Iglesias
Reviewed-by: Peter Maydell
---
hw/misc/xlnx-versal-cfu.c | 87 +++
include/hw/misc/xlnx-versal-cfu.h | 15 +
Introduce a model of Xilinx Versal's Configuration Frame Unit's data out
port (CFU_FDRO).
Signed-off-by: Francisco Iglesias
Reviewed-by: Peter Maydell
---
hw/misc/xlnx-versal-cfu.c | 96 +++
include/hw/misc/xlnx-versal-cfu.h | 12
2 files ch
Introduce a model of the software programming interface (CFU_APB) of
Xilinx Versal's Configuration Frame Unit.
Signed-off-by: Francisco Iglesias
Reviewed-by: Peter Maydell
---
MAINTAINERS | 2 +
hw/misc/meson.build | 1 +
hw/misc/xlnx-versal-
emulating bitstream programming and readback).
Signed-off-by: Francisco Iglesias
Reviewed-by: Sai Pavan Boddu
Acked-by: Edgar E. Iglesias
---
MAINTAINERS | 6
hw/misc/meson.build | 1 +
hw/misc/xlnx-cfi-if.c | 34
include/hw/misc/xlnx
Connect the Configuration Frame Unit (CFU_APB, CFU_FDRO and CFU_SFR) to
the Versal machine.
Signed-off-by: Francisco Iglesias
Acked-by: Edgar E. Iglesias
Reviewed-by: Peter Maydell
---
hw/arm/xlnx-versal.c | 42
include/hw/arm/xlnx-versal.h | 16
Introduce a model of Xilinx Versal's Configuration Frame controller
(CFRAME_REG).
Signed-off-by: Francisco Iglesias
---
MAINTAINERS | 2 +
hw/misc/meson.build | 1 +
hw/misc/xlnx-versal-cframe-reg.c
Connect the Configuration Frame controller (CFRAME_REG) and the
Configuration Frame broadcast controller (CFRAME_BCAST_REG) to the
Versal machine.
Signed-off-by: Francisco Iglesias
Reviewed-by: Peter Maydell
---
hw/arm/xlnx-versal.c | 113 ++-
include/hw
Introduce a model of Xilinx Versal's Configuration Frame broadcast
controller (CFRAME_BCAST_REG).
Signed-off-by: Francisco Iglesias
Reviewed-by: Peter Maydell
---
hw/misc/xlnx-versal-cframe-reg.c | 161 +++
include/hw/misc/xlnx-versal-cframe-reg.h | 17 +++
2
with connecting the models to Xilinx Versal
machine.
Best regards,
Francisco Iglesias
References:
[1] https://docs.xilinx.com/r/en-US/am011-versal-acap-trm/PSM-Local-Registers
Changelog:
v4->v5:
* Identical to v4 (resend of v4 due to an smtp problem)
v3->v4:
[PATCH 5]
* Swap to pop o
emulating bitstream programming and readback).
Signed-off-by: Francisco Iglesias
Reviewed-by: Sai Pavan Boddu
Acked-by: Edgar E. Iglesias
---
MAINTAINERS | 6
hw/misc/meson.build | 1 +
hw/misc/xlnx-cfi-if.c | 34
include/hw/misc/xlnx
Introduce a model of Xilinx Versal's Configuration Frame Unit's data out
port (CFU_FDRO).
Signed-off-by: Francisco Iglesias
Reviewed-by: Peter Maydell
---
hw/misc/xlnx-versal-cfu.c | 96 +++
include/hw/misc/xlnx-versal-cfu.h | 12
2 files ch
Connect the Configuration Frame controller (CFRAME_REG) and the
Configuration Frame broadcast controller (CFRAME_BCAST_REG) to the
Versal machine.
Signed-off-by: Francisco Iglesias
Reviewed-by: Peter Maydell
---
hw/arm/xlnx-versal.c | 113 ++-
include/hw
Introduce a model of Xilinx Versal's Configuration Frame controller
(CFRAME_REG).
Signed-off-by: Francisco Iglesias
---
MAINTAINERS | 2 +
hw/misc/meson.build | 1 +
hw/misc/xlnx-versal-cframe-reg.c
Introduce a model of Xilinx Versal's Configuration Frame broadcast
controller (CFRAME_BCAST_REG).
Signed-off-by: Francisco Iglesias
Reviewed-by: Peter Maydell
---
hw/misc/xlnx-versal-cframe-reg.c | 161 +++
include/hw/misc/xlnx-versal-cframe-reg.h | 17 +++
2
Introduce a model of the software programming interface (CFU_APB) of
Xilinx Versal's Configuration Frame Unit.
Signed-off-by: Francisco Iglesias
Reviewed-by: Peter Maydell
---
MAINTAINERS | 2 +
hw/misc/meson.build | 1 +
hw/misc/xlnx-versal-
Introduce a model of Xilinx Versal's Configuration Frame Unit's Single
Frame Read port (CFU_SFR).
Signed-off-by: Francisco Iglesias
Reviewed-by: Peter Maydell
---
hw/misc/xlnx-versal-cfu.c | 87 +++
include/hw/misc/xlnx-versal-cfu.h | 15 +
Connect the Configuration Frame Unit (CFU_APB, CFU_FDRO and CFU_SFR) to
the Versal machine.
Signed-off-by: Francisco Iglesias
Acked-by: Edgar E. Iglesias
Reviewed-by: Peter Maydell
---
hw/arm/xlnx-versal.c | 42
include/hw/arm/xlnx-versal.h | 16
Coverity found that the variable tx_rx in the function
xilinx_spips_flush_txfifo was being used uninitialized (CID 1383841). This
patch corrects this by always initializing tx_rx to zeros.
Signed-off-by: Francisco Iglesias
---
v3. Change to report errors on the num_busses property via the Error
On Thursday, 25 January 2018, Peter Maydell
wrote:
> On 24 January 2018 at 21:57, Francisco Iglesias
> wrote:
> > Coverity found that the variable tx_rx in the function
> > xilinx_spips_flush_txfifo was being used uninitialized (CID 1383841).
> This
> > pa
On 28 November 2017 at 23:31, Alistair Francis
wrote:
> Update the reset value to match the latest ZynqMP register spec.
>
> Signed-off-by: Alistair Francis
>
Reviewed-by: Francisco Iglesias
> ---
>
> hw/ssi/xilinx_spips.c | 1 +
> 1 file changed, 1 insertion(+)
On 28 November 2017 at 23:31, Alistair Francis
wrote:
> Use memset() instead of a for loop to zero all of the registers.
>
> Signed-off-by: Alistair Francis
>
Reviewed-by: Francisco Iglesias
> ---
>
> hw/ssi/xilinx_spips.c | 11 +++
> 1 file changed, 3 in
s->regs[R_INTR_STATUS] = R_INTR_STATUS_RESET;
> +s->regs[R_GPIO] = 1;
>
+s->regs[R_LPBK_DLY_ADJ] = R_LPBK_DLY_ADJ_RESET;
> +s->regs[R_GQSPI_GFIFO_THRESH] = 0x10;
> s->regs[R_GQSPI_IMR] = GQSPI_IXR_MASK;
>
Also, above row will be overriden below so ma
(0x110 / 4)
> +#define R_GQSPI_IMR_RESET (0xfbe)
> #define R_GQSPI_TX_THRESH (0x128 / 4)
> #define R_GQSPI_RX_THRESH (0x12c / 4)
> +#define R_GQSPI_GPIO_THRESH (0x130 / 4)
>
According to doc (mentioned in patch 0/3) the address above, 0x130, is
"GQSPI GPIO for Writ
On 11 December 2017 at 18:27, Alistair Francis
wrote:
> On Wed, Dec 6, 2017 at 3:39 PM, francisco iglesias
> wrote:
> > Hi Alistair,
> >
> > On 6 December 2017 at 23:22, Alistair Francis <
> alistair.fran...@xilinx.com>
> > wrote:
> >>
> >
On 13 December 2017 at 06:17, Philippe Mathieu-Daudé
wrote:
> Signed-off-by: Philippe Mathieu-Daudé
> ---
> include/hw/registerfields.h | 11 +++
> 1 file changed, 11 insertions(+)
>
> diff --git a/include/hw/registerfields.h b/include/hw/registerfields.h
> index ad9d7a82a3..f59e7f47bd
Good day Alistair,
Thank you very much for reviewing agian! I will update the patch set
according to your comments and come back with a new version (v8)!
Best regards,
Francisco Iglesias
On 23 November 2017 at 01:39, Alistair Francis wrote:
> On Thu, Nov 2, 2017 at 5:01 PM, Franci
Add support for continuous read out of the RDSR and READ_FSR status
registers until the chip select is deasserted. This feature is supported
by amongst others 1 or more flashtypes manufactured by Numonyx (Micron),
Windbond, SST, Gigadevice, Eon and Macronix.
Signed-off-by: Francisco Iglesias
Make tx/rx_data_bytes more generic so they can be reused (when adding
support for the Zynqmp Generic QSPI).
Signed-off-by: Francisco Iglesias
---
hw/ssi/xilinx_spips.c | 64 +--
1 file changed, 37 insertions(+), 27 deletions(-)
diff --git a/hw
Add support for the bank address register access commands (BRRD/BRWR) and
the BULK_ERASE (0x60) command.
Signed-off-by: Francisco Iglesias
Acked-by: Marcin Krzemiński
---
hw/block/m25p80.c | 7 +++
1 file changed, 7 insertions(+)
diff --git a/hw/block/m25p80.c b/hw/block/m25p80.c
index
: Francisco Iglesias
Reviewed-by: Alistair Francis
---
hw/ssi/xilinx_spips.c | 35 ---
include/hw/ssi/xilinx_spips.h | 34 ++
2 files changed, 34 insertions(+), 35 deletions(-)
diff --git a/hw/ssi/xilinx_spips.c b/hw/ssi
pumping according transfer register and 4
byte LQSPI addresses. Finally it adds support for the ZynqMP Generic QSPI and
adds the ZynqMP QSPI to the xlnx-zcu102 board.
Best regards,
Francisco Iglesias
Changelog:
v7 -> v8
* Corrected commit messages in the patches 'xilinx_spips: Don'
Add support for 4 byte addresses in the LQSPI and correct LQSPI_CFG_SEP_BUS.
Signed-off-by: Francisco Iglesias
Reviewed-by: Alistair Francis
---
hw/ssi/xilinx_spips.c | 6 +-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/hw/ssi/xilinx_spips.c b/hw/ssi/xilinx_spips.c
index
Add support for Micron (Numonyx) n25q512a11 and n25q512a13 flashes.
Signed-off-by: Francisco Iglesias
Acked-by: Marcin Krzemiński
Reviewed-by: Alistair Francis
---
hw/block/m25p80.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/hw/block/m25p80.c b/hw/block/m25p80.c
index 1d0aa1d
: Francisco Iglesias
Acked-by: Alistair Francis
---
hw/ssi/xilinx_spips.c | 19 ++-
1 file changed, 10 insertions(+), 9 deletions(-)
diff --git a/hw/ssi/xilinx_spips.c b/hw/ssi/xilinx_spips.c
index 559fa79..231aa5b 100644
--- a/hw/ssi/xilinx_spips.c
+++ b/hw/ssi/xilinx_spips.c
@@ -208,14
Add support for SST READ ID 0x90/0xAB commands for reading out the flash
manufacuter ID and device ID.
Signed-off-by: Francisco Iglesias
Acked-by: Alistair Francis
Acked-by: Marcin Krzemiński
---
hw/block/m25p80.c | 23 +++
1 file changed, 23 insertions(+)
diff --git a/hw
Don't set TX FIFO UNDERFLOW interrupt after transmitting the commands.
Also update interrupts after reading out the interrupt status.
Signed-off-by: Francisco Iglesias
Acked-by: Alistair Francis
---
hw/ssi/xilinx_spips.c | 4 +---
1 file changed, 1 insertion(+), 3 deletions(-)
diff --git
Add support for the RX discard and RX drain functionality. Also transmit
one byte per dummy cycle (to the flash memories) with commands that require
these.
Signed-off-by: Francisco Iglesias
---
hw/ssi/xilinx_spips.c | 167 +-
include/hw/ssi
Add support for zero pumping according to the transfer size register.
Signed-off-by: Francisco Iglesias
---
hw/ssi/xilinx_spips.c | 47 ---
include/hw/ssi/xilinx_spips.h | 2 ++
2 files changed, 42 insertions(+), 7 deletions(-)
diff --git a/hw
Add support for the ZynqMP QSPI (consisting of the Generic QSPI and Legacy
QSPI) and connect Numonyx n25q512a11 flashes to it.
Signed-off-by: Francisco Iglesias
Reviewed-by: Alistair Francis
---
hw/arm/xlnx-zcu102.c | 23 +++
hw/arm/xlnx-zynqmp.c | 26
Add support for the Zynq Ultrascale MPSoc Generic QSPI.
Signed-off-by: Francisco Iglesias
---
default-configs/arm-softmmu.mak | 2 +-
hw/ssi/xilinx_spips.c | 579
include/hw/ssi/xilinx_spips.h | 32 ++-
3 files changed, 564 insertions
201 - 300 of 576 matches
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