s is confusing for the user.
>
> Use blk_check_size_and_read_all() instead of blk_pread() to improve
> the reported error.
>
> Signed-off-by: Cédric Le Goater
Reviewed-by: Francisco Iglesias
> ---
> hw/block/m25p80.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletio
RDSFDP command giving access to
> a private SFDP area under the flash. This area now needs to be
> populated with the flash device characteristics, using a new
> 'sfdp_read' handler under FlashPartInfo.
>
> Signed-off-by: Cédric Le Goater
Reviewed-by: Francisco Iglesia
On 2024-02-16 12:03, Philippe Mathieu-Daudé wrote:
When the QOM parent is available, prefer object_initialize_child()
over object_initialize(), since it create the parent relationship.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Francisco Iglesias
---
hw/net/can/xlnx-versal
rrects the issue for the zynqmp but not for the other two models
(below functions shouldn't be called when writing the mentioned config
regs for them either), would it be ok for you to expand to the switch
cases you had in v1 (into the switch in this function and return afte
J:
> +case R_IOU_TAPDLY_BYPASS:
> +case R_DUMMY_CYCLE_EN:
> +case R_ECO:
Would it be ok for you to move above cases into the switch case above in
this same function instead? (And add a reg write before returning) This
way all registers are handled at
ize but I forgot to mention that below are not dummy registers
(they are configuration registers). Would it be ok for you to remove the
last (second) sentence above?
The patch looks ok to me after that! (Also tested it!)
Best regards,
Francisco Iglesias
>
> Signed-off-by: Sai Pavan Boddu
From: Francisco Iglesias
Correct the number of dummy cycles required by the FAST_READ_4 command (to
be eight, one dummy byte).
Fixes: ef06ca3946 ("xilinx_spips: Add support for RX discard and RX drain")
Suggested-by: Cédric Le Goater
Signed-off-by: Francisco Iglesias
-
is needed in the xilinx_spips aswell, I just
provided a patch. Thank you for the notification!
Best regards,
Francisco Iglesias
>
> Thanks,
>
> C.
>
>
> > Signed-off-by: Guenter Roeck
> > ---
> > hw/ssi/aspeed_smc.c | 2 +-
> > 1 file changed, 1 insertion
Also consider the requested transaction size when generating the access
mask (so that only the requested bytes are returned when those are less
than the memory region's minimum access size).
Signed-off-by: Francisco Iglesias
---
memory.c | 2 +-
1 file changed, 1 insertion(+), 1 del
Connect Versal's PMC SLCR (system-level control registers) model.
Signed-off-by: Francisco Iglesias
---
hw/arm/xlnx-versal.c | 18 ++
include/hw/arm/xlnx-versal.h | 6 ++
2 files changed, 24 insertions(+)
diff --git a/hw/arm/xlnx-versal.c b/hw/arm/xlnx-ver
Add a model of Versal's PMC SLCR (system-level control registers).
Signed-off-by: Francisco Iglesias
Signed-off-by: Edgar E. Iglesias
---
hw/misc/meson.build|5 +-
hw/misc/xlnx-versal-pmc-iou-slcr.c | 1437
include/hw/misc
Include ptimer.h and stream.h in the header for being able to build and
reuse the DMA model (the first usage of StreamSink, StreamCanPushNotifyFn
and ptimer_state is in the header).
Signed-off-by: Francisco Iglesias
---
include/hw/dma/xlnx_csu_dma.h | 3 +++
1 file changed, 3 insertions
Connect Micron Xccela mt35xu01g flashes to the OSPI flash memory
controller.
Signed-off-by: Francisco Iglesias
---
hw/arm/xlnx-versal-virt.c | 23 +++
1 file changed, 23 insertions(+)
diff --git a/hw/arm/xlnx-versal-virt.c b/hw/arm/xlnx-versal-virt.c
index d2f55e29b6
Add an interface for controlling DMA models that are reused with other
models. This allows a controlling model to start transfers through the
DMA while reusing the DMA's handling of transfer state and completion
signaling.
Signed-off-by: Francisco Iglesias
---
hw/dma/dma-ctrl.c
Implement the DMA control interface for allowing control of DMA operations
from inside models that contain instances of (and reuse) the Xilinx CSU
DMA.
Signed-off-by: Francisco Iglesias
---
hw/dma/xlnx_csu_dma.c | 32
include/hw/dma/xlnx_csu_dma.h | 4
Add support for Micron Xccela flash mt35xu01g.
Signed-off-by: Francisco Iglesias
---
hw/block/m25p80.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/hw/block/m25p80.c b/hw/block/m25p80.c
index b77503dc84..c6bf3c6bfa 100644
--- a/hw/block/m25p80.c
+++ b/hw/block/m25p80.c
@@ -255,6 +255,8
Connect the OSPI flash memory controller model (including the source and
destination DMA).
Signed-off-by: Francisco Iglesias
---
hw/arm/xlnx-versal.c | 89
include/hw/arm/xlnx-versal.h | 18 +
2 files changed, 107 insertions(+)
diff
Add a model of Xilinx Versal's OSPI flash memory controller.
Signed-off-by: Francisco Iglesias
---
hw/ssi/meson.build|1 +
hw/ssi/xlnx-versal-ospi.c | 1892 +
include/hw/ssi/xlnx-versal-ospi.h | 86 ++
3 files changed,
a model of
Versal's OSPI controller is added and connected to the Versal virt
machine. The series then ends with adding initial support for the Micron
Xccelera mt35xu01g flash and flashes of this type are connected to the
OSPI in the Versal virt machine.
Best regards,
Francisco Iglesias
Franci
Hi Edgar,
Thank you for having a look at the series! I made the updates in v2!
Best regards,
Francisco Iglesias
On [2021 Nov 19] Fri 18:16:23, Edgar E. Iglesias wrote:
> On Wed, Nov 17, 2021 at 02:18:41PM +0000, Francisco Iglesias wrote:
> > Connect Micron Xccela mt35xu01g flashes to
Implement the DMA control interface for allowing control of DMA operations
from inside models that contain instances of (and reuse) the Xilinx CSU
DMA.
Signed-off-by: Francisco Iglesias
Reviewed-by: Edgar E. Iglesias
---
hw/dma/xlnx_csu_dma.c | 32
Add a model of Xilinx Versal's OSPI flash memory controller.
Signed-off-by: Francisco Iglesias
Reviewed-by: Edgar E. Iglesias
---
hw/ssi/meson.build|1 +
hw/ssi/xlnx-versal-ospi.c | 1892 +
include/hw/ssi/xlnx-versal-ospi.h |
Add an interface for controlling DMA models that are reused with other
models. This allows a controlling model to start transfers through the
DMA while reusing the DMA's handling of transfer state and completion
signaling.
Signed-off-by: Francisco Iglesias
Reviewed-by: Edgar E. Iglesias
--
Include ptimer.h and stream.h in the header for being able to build and
reuse the DMA model (the first usage of StreamSink, StreamCanPushNotifyFn
and ptimer_state is in the header).
Signed-off-by: Francisco Iglesias
---
include/hw/dma/xlnx_csu_dma.h | 3 +++
1 file changed, 3 insertions
Connect Micron Xccela mt35xu01g flashes to the OSPI flash memory
controller.
Signed-off-by: Francisco Iglesias
---
hw/arm/xlnx-versal-virt.c | 23 +++
1 file changed, 23 insertions(+)
diff --git a/hw/arm/xlnx-versal-virt.c b/hw/arm/xlnx-versal-virt.c
index d2f55e29b6
Add support for Micron Xccela flash mt35xu01g.
Signed-off-by: Francisco Iglesias
Reviewed-by: Edgar E. Iglesias
---
hw/block/m25p80.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/hw/block/m25p80.c b/hw/block/m25p80.c
index b77503dc84..c6bf3c6bfa 100644
--- a/hw/block/m25p80.c
+++ b/hw
List myself as maintainer for the Xilinx Versal OSPI controller.
Signed-off-by: Francisco Iglesias
---
MAINTAINERS | 6 ++
1 file changed, 6 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index d3879aa3c1..8c2b01a282 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -963,6 +963,12 @@ F
Connect the OSPI flash memory controller model (including the source and
destination DMA).
Signed-off-by: Francisco Iglesias
---
hw/arm/xlnx-versal.c | 87
include/hw/arm/xlnx-versal.h | 20 ++
2 files changed, 107 insertions(+)
diff
a model of
Versal's OSPI controller is added and connected to the Versal virt
machine. The series then ends with adding initial support for the Micron
Xccelera mt35xu01g flash and flashes of this type are connected to the
OSPI in the Versal virt machine.
Best regards,
Francisco Iglesias
Chan
Connect Versal's PMC SLCR (system-level control registers) model.
Signed-off-by: Francisco Iglesias
Reviewed-by: Edgar E. Iglesias
---
hw/arm/xlnx-versal.c | 18 ++
include/hw/arm/xlnx-versal.h | 6 ++
2 files changed, 24 insertions(+)
diff --git a/hw/arm
Add a model of Versal's PMC SLCR (system-level control registers).
Signed-off-by: Francisco Iglesias
Signed-off-by: Edgar E. Iglesias
---
hw/misc/meson.build|5 +-
hw/misc/xlnx-versal-pmc-iou-slcr.c | 1445
include/hw/misc
Add a model of Versal's PMC SLCR (system-level control registers).
Signed-off-by: Francisco Iglesias
Signed-off-by: Edgar E. Iglesias
Acked-by: Edgar E. Iglesias
---
hw/misc/meson.build|5 +-
hw/misc/xlnx-versal-pmc-iou-slcr.c |
Add an interface for controlling DMA models that are reused with other
models. This allows a controlling model to start transfers through the
DMA while reusing the DMA's handling of transfer state and completion
signaling.
Signed-off-by: Francisco Iglesias
Reviewed-by: Edgar E. Iglesias
--
Add support for Micron Xccela flash mt35xu01g.
Signed-off-by: Francisco Iglesias
Reviewed-by: Edgar E. Iglesias
---
hw/block/m25p80.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/hw/block/m25p80.c b/hw/block/m25p80.c
index b77503dc84..c6bf3c6bfa 100644
--- a/hw/block/m25p80.c
+++ b/hw
Implement the DMA control interface for allowing control of DMA operations
from inside models that contain instances of (and reuse) the Xilinx CSU
DMA.
Signed-off-by: Francisco Iglesias
Reviewed-by: Edgar E. Iglesias
---
hw/dma/xlnx_csu_dma.c | 32
Add in the missing includes in the header for being able to build the DMA
model when reusing it.
Signed-off-by: Francisco Iglesias
---
include/hw/dma/xlnx_csu_dma.h | 5 +
1 file changed, 5 insertions(+)
diff --git a/include/hw/dma/xlnx_csu_dma.h b/include/hw/dma/xlnx_csu_dma.h
index
Connect the OSPI flash memory controller model (including the source and
destination DMA).
Signed-off-by: Francisco Iglesias
Reviewed-by: Edgar E. Iglesias
---
hw/arm/xlnx-versal.c | 87
include/hw/arm/xlnx-versal.h | 20 ++
2 files
Hi Philippe,
On [2021 Nov 23] Tue 11:45:45, Philippe Mathieu-Daudé wrote:
> On 11/23/21 11:34, Francisco Iglesias wrote:
> > Include ptimer.h and stream.h in the header for being able to build and
> > reuse the DMA model (the first usage of StreamSink, StreamCanPushNotifyFn
>
a model of
Versal's OSPI controller is added and connected to the Versal virt
machine. The series then ends with adding initial support for the Micron
Xccelera mt35xu01g flash and flashes of this type are connected to the
OSPI in the Versal virt machine.
Best regards,
Francisco Iglesias
Chan
Connect Versal's PMC SLCR (system-level control registers) model.
Signed-off-by: Francisco Iglesias
Reviewed-by: Edgar E. Iglesias
---
hw/arm/xlnx-versal.c | 18 ++
include/hw/arm/xlnx-versal.h | 6 ++
2 files changed, 24 insertions(+)
diff --git a/hw/arm
Add a model of Xilinx Versal's OSPI flash memory controller.
Signed-off-by: Francisco Iglesias
Reviewed-by: Edgar E. Iglesias
---
hw/ssi/meson.build|1 +
hw/ssi/xlnx-versal-ospi.c | 1892 +
include/hw/ssi/xlnx-versal-ospi.h |
List myself as maintainer for the Xilinx Versal OSPI controller.
Signed-off-by: Francisco Iglesias
Reviewed-by: Edgar E. Iglesias
---
MAINTAINERS | 6 ++
1 file changed, 6 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index d3879aa3c1..8c2b01a282 100644
--- a/MAINTAINERS
+++ b
Connect Micron Xccela mt35xu01g flashes to the OSPI flash memory
controller.
Signed-off-by: Francisco Iglesias
Reviewed-by: Edgar E. Iglesias
---
hw/arm/xlnx-versal-virt.c | 23 +++
1 file changed, 23 insertions(+)
diff --git a/hw/arm/xlnx-versal-virt.c b/hw/arm/xlnx
On [2023 May 08] Mon 09:58:49, Cédric Le Goater wrote:
> This should also avoid Coverity to report a memory leak warning when
> the QEMU process exits. See CID 1508061.
>
> Signed-off-by: Cédric Le Goater
Reviewed-by: Francisco Iglesias
> ---
> hw/arm/aspeed.c | 12
essage-Id: <20230421131547.2177449-1-...@kaod.org>
> Signed-off-by: Cédric Le Goater
Reviewed-by: Francisco Iglesias
> ---
> hw/misc/aspeed_hace.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/hw/misc/aspeed_hace.c b/hw/misc/aspeed_hac
Huth
Reviewed-by: Francisco Iglesias
> ---
> hw/net/xilinx_ethlite.c | 2 +-
> hw/net/meson.build | 2 +-
> 2 files changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/hw/net/xilinx_ethlite.c b/hw/net/xilinx_ethlite.c
> index 99c22819ea..89f4f3b254 100644
> -
On [2022 Jun 21] Tue 13:24:27, Iris Chen wrote:
> From: Iris Chen
>
> Signed-off-by: Iris Chen
Reviewed-by: Francisco Iglesias
> ---
> Fixed .needed for subsection and suggestions from Francisco
>
> hw/block/m25p80.c | 82 ++--
On [2022 Jun 28] Tue 17:52:50, Cédric Le Goater wrote:
> Alistair, Francisco,
>
> On 6/22/22 11:45, Francisco Iglesias wrote:
> > On [2022 Jun 21] Tue 13:24:27, Iris Chen wrote:
> > > From: Iris Chen
> > >
> > > Signed-off-by: Iris Chen
> >
s->data[0] |= (!!s->top_bottom_bit) << 5;
> +}
> +if (s->pi->flags & SNOR_F_HAS_SR_BP3_BIT6) {
> +s->data[0] |= (!!s->block_protect3) << 6;
> +}
>
> if (get_man(s) == MAN_MACRONIX || get_man(s) == MAN_ISSI) {
> s->data[0] |= (!!s->quad_enable) << 6;
> @@ -1553,6 +1598,11 @@ static void m25p80_reset(DeviceState *d)
>
> s->wp_level = true;
> s->status_register_write_disabled = false;
> +s->block_protect0 = false;
> +s->block_protect1 = false;
> +s->block_protect2 = false;
> +s->block_protect3 = false;
> +s->top_bottom_bit = false;
We need to place above ones in a subsection in the vmstate (similar to the your
previous patch).
Looks good to me otherwise!
Thanks!
Best regards,
Francisco Iglesias
>
> reset_memory(s);
> }
> --
> 2.30.2
>
>
On [2022 Jul 01] Fri 14:23:17, Cédric Le Goater wrote:
> On 7/1/22 13:40, Francisco Iglesias wrote:
> > Hi Iris,
> >
> > Looks good, a couple of minor comments below!
> >
> > On [2022 Jun 27] Mon 11:52:33, Iris Chen wrote:
> > > Signed-off-by: Iris Chen
On [2023 Apr 24] Mon 23:34:30, Vikram Garhwal wrote:
> Signed-off-by: Vikram Garhwal
> Reviewed-by: Peter Maydell
Reviewed-by: Francisco Iglesias
> ---
> MAINTAINERS | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/MAINTAINERS b/MAINTAINE
qemu_fdt_setprop_string(s->fdt, name, "compatible",
> +"xlnx,versal-canfd");
And here we can swap above line with (kernel compatible):
"xlnx,canfd-2.0");
After changing above the linux
igned-off-by: Tong Ho
Reviewed-by: Francisco Iglesias
> ---
> hw/nvram/xlnx-efuse.c | 11 +--
> 1 file changed, 9 insertions(+), 2 deletions(-)
>
> diff --git a/hw/nvram/xlnx-efuse.c b/hw/nvram/xlnx-efuse.c
> index fdfffaab99..655c40b8d1 100644
> --- a/hw/nvram/
Hi Vikram,
A few comments below and some suggestions!
On [2023 Apr 24] Mon 23:34:31, Vikram Garhwal wrote:
> The Xilinx Versal CANFD controller is developed based on SocketCAN, QEMU CAN
> bus
> implementation. Bus connection and socketCAN connection for each CAN module
> can be set through comm
On [2023 May 22] Mon 17:31:33, Philippe Mathieu-Daudé wrote:
> Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Francisco Iglesias
> ---
> include/qemu/fifo8.h | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/include/qemu/fifo8.h b/include/qe
ieu-Daudé
Reviewed-by: Francisco Iglesias
> ---
> include/qemu/fifo8.h | 10 +-
> util/fifo8.c | 12
> 2 files changed, 13 insertions(+), 9 deletions(-)
>
> diff --git a/include/qemu/fifo8.h b/include/qemu/fifo8.h
> index 16be02f361..d0d02
* @numptr: pointer filled with number of bytes returned (can be NULL)
> + *
> + * Pop a number of elements from the FIFO up to a maximum of max. The buffer
s/Pop/Peek into/
> + * containing the popped data is returned. This buffer points directly into
s/popped data/data peeked into/
If
On [2023 May 19] Fri 13:36:57, Vikram Garhwal wrote:
> Connect CANFD0 and CANFD1 on the Versal-virt machine and update
> xlnx-versal-virt
> document with CANFD command line examples.
>
> Signed-off-by: Vikram Garhwal
> Reviewed-by: Peter Maydell
Reviewed-by: Francisco Iglesi
quot;, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
> + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES
he following error afterwards, as Qemu will try to
> instantiate some additional RPUs.
> | $ qemu-system-aarch64 --smp 1 -M xlnx-zcu102
> | **
> | ERROR:../src/tcg/tcg.c:777:tcg_register_thread:
> | assertion failed: (n < tcg_max_ctxs)
>
> Signed-off-by: Clément Chigot
On 2023-03-10 19:03, Alex Bennée wrote:
AMD recently acquired Xilinx and contributors have been transitioning
their emails across.
> Signed-off-by: Alex Bennée
Reviewed-by: Francisco Iglesias
Cc: Vikram Garhwal
Cc: Francisco Iglesias
Cc: Stefano Stabellini
Cc: Sai Pavan Boddu
On [2021 Oct 04] Mon 17:46:33, Cédric Le Goater wrote:
> The register index is currently printed and this is confusing.
>
> Signed-off-by: Cédric Le Goater
Reviewed-by: Francisco Iglesias
> ---
> hw/ssi/aspeed_smc.c | 6 +++---
> 1 file changed, 3 insertions(+), 3 dele
On [2021 Oct 04] Mon 17:46:32, Cédric Le Goater wrote:
> Signed-off-by: Cédric Le Goater
Reviewed-by: Francisco Iglesias
> ---
> hw/watchdog/wdt_aspeed.c | 5 +
> hw/watchdog/trace-events | 4
> 2 files changed, 9 insertions(+)
>
> diff --git a/hw/watchdog/wdt_a
> +.read = register_read_memory,
> +.write = register_write_memory,
> +.endianness = DEVICE_LITTLE_ENDIAN,
> +.valid = {
> +.min_access_size = 4,
> +.max_access_size = 4,
> +},
> +};
> +
> +static void crf_init(Object *o
On Mon, Jan 31, 2022 at 12:12:04AM +0100, Edgar E. Iglesias wrote:
> From: "Edgar E. Iglesias"
>
> Connect the ZynqMP CRF - Clock Reset FPD device.
>
> Signed-off-by: Edgar E. Iglesias
Reviewed-by: Francisco Iglesias
> ---
> include/hw/arm/xlnx-zynqmp.h
ut is used to connect to PMU GPIs. */
> +qdev_init_gpio_out_named(DEVICE(obj), s->wfi_out, "wfi_out", 4);
> +/* CPU_POWER_STATUS is used to connect to INTC redirect. */
> +qdev_init_gpio_out_named(DEVICE(obj), s->cpu_power_status,
> + "C
On Mon, Jan 31, 2022 at 12:12:01AM +0100, Edgar E. Iglesias wrote:
> From: "Edgar E. Iglesias"
>
> Add unimplemented SERDES area.
>
> Signed-off-by: Edgar E. Iglesias
Reviewed-by: Francisco Iglesias
> ---
> include/hw/arm/xlnx-zynqmp.h | 2 +-
> hw/arm/x
On Mon, Jan 31, 2022 at 12:12:06AM +0100, Edgar E. Iglesias wrote:
> From: "Edgar E. Iglesias"
>
> Connect the ZynqMP APU Control device.
>
> Signed-off-by: Edgar E. Iglesias
Reviewed-by: Francisco Iglesias
> ---
> include/hw/arm/xlnx-zynqmp.h | 4 +++-
>
'Or' the IRQs coming from the QSPI and QSPI DMA models. This is done for
avoiding the situation where one of the models incorrectly deasserts an
interrupt asserted from the other model (which will result in that the IRQ
is lost and will not reach guest SW).
Signed-off-by: Francisc
On [2022 Jan 07] Fri 16:07:17, Peter Maydell wrote:
> On Tue, 14 Dec 2021 at 11:04, Francisco Iglesias
> wrote:
> >
> > Also, since being the author, list myself as maintainer for the file.
> >
> > Signed-off-by: Francisco Iglesias
>
>
> > +DmaCtrl
Add a model of Versal's PMC SLCR (system-level control registers).
Signed-off-by: Francisco Iglesias
Signed-off-by: Edgar E. Iglesias
Reviewed-by: Peter Maydell
---
hw/misc/meson.build|5 +-
hw/misc/xlnx-versal-pmc-iou-slcr.c |
Connect Versal's PMC SLCR (system-level control registers) model.
Signed-off-by: Francisco Iglesias
---
hw/arm/xlnx-versal.c | 71 +++-
include/hw/arm/xlnx-versal.h | 5
2 files changed, 75 insertions(+), 1 deletion(-)
diff --git a/h
Add an orgate and 'or' the interrupts from the BBRAM and RTC models.
Signed-off-by: Francisco Iglesias
Reviewed-by: Peter Maydell
---
hw/arm/xlnx-versal-virt.c| 2 +-
hw/arm/xlnx-versal.c | 28 ++--
include/hw/arm/xlnx-versal.h | 5 +++--
3 fil
completion signaling will be read and caught through the DMA engine
model's register API and signaling.
Signed-off-by: Francisco Iglesias
---
hw/dma/dma-ctrl-if.c | 30 +++
hw/dma/meson.build | 1 +
include/hw/dma/dma
Add support for Micron Xccela flash mt35xu01g.
Signed-off-by: Francisco Iglesias
Reviewed-by: Edgar E. Iglesias
---
hw/block/m25p80.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/hw/block/m25p80.c b/hw/block/m25p80.c
index b77503dc84..c6bf3c6bfa 100644
--- a/hw/block/m25p80.c
+++ b/hw
Add in the missing includes in the header for being able to build the DMA
model when reusing it.
Signed-off-by: Francisco Iglesias
Reviewed-by: Peter Maydell
---
include/hw/dma/xlnx_csu_dma.h | 5 +
1 file changed, 5 insertions(+)
diff --git a/include/hw/dma/xlnx_csu_dma.h b/include/hw
List myself as maintainer for the Xilinx Versal OSPI controller.
Signed-off-by: Francisco Iglesias
Reviewed-by: Edgar E. Iglesias
Reviewed-by: Peter Maydell
---
MAINTAINERS | 6 ++
1 file changed, 6 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index 6ccdec7f02..0e31569d65 100644
Implement the DMA control interface for allowing direct control of DMA
operations from inside peripheral models embedding (and reusing) the
Xilinx CSU DMA.
Signed-off-by: Francisco Iglesias
---
hw/dma/xlnx_csu_dma.c | 20
1 file changed, 20 insertions(+)
diff --git a/hw
Add a model of Xilinx Versal's OSPI flash memory controller.
Signed-off-by: Francisco Iglesias
---
hw/ssi/meson.build|1 +
hw/ssi/xlnx-versal-ospi.c | 1856 +
include/hw/ssi/xlnx-versal-ospi.h | 111 +++
3 files changed,
Connect the OSPI flash memory controller model (including the source and
destination DMA).
Signed-off-by: Francisco Iglesias
Reviewed-by: Peter Maydell
---
hw/arm/xlnx-versal.c | 93
include/hw/arm/xlnx-versal.h | 20 ++
2 files
Connect Micron Xccela mt35xu01g flashes to the OSPI flash memory
controller.
Signed-off-by: Francisco Iglesias
Reviewed-by: Edgar E. Iglesias
Reviewed-by: Peter Maydell
---
hw/arm/xlnx-versal-virt.c | 23 +++
1 file changed, 23 insertions(+)
diff --git a/hw/arm/xlnx
Also, since being the author, list myself as maintainer for the file.
Signed-off-by: Francisco Iglesias
---
MAINTAINERS| 1 +
docs/devel/dma-ctrl-if.rst | 243 +
docs/devel/index.rst | 1 +
3 files changed, 245 insertions
a model of
Versal's OSPI controller is added and connected to the Versal virt
machine. The series then ends with adding initial support for the Micron
Xccelera mt35xu01g flash and flashes of this type are connected to the
OSPI in the Versal virt machine.
Best regards,
Francisco Iglesias
Chan
Hi Luc,
All the suggestions and corrections look good to me so brought them in in
v7!
Thank you very much reviewing!
Best regards,
Francisco Iglesias
On [2022 Jan 18] Tue 22:46:32, Luc Michel wrote:
> Hi Francisco,
>
> Impressive beast :-) Nicely done. Maybe I would have spli
On [2022 Jan 18] Tue 23:01:42, Luc Michel wrote:
> Hi Francisco!
>
> On 15:28 Fri 14 Jan , Francisco Iglesias wrote:
> > An option on real hardware when embedding a DMA engine into a peripheral
> > is to make the peripheral control the engine through a custom DMA
Connect Versal's PMC SLCR (system-level control registers) model.
Signed-off-by: Francisco Iglesias
Reviewed-by: Luc Michel
---
include/hw/arm/xlnx-versal.h | 5
hw/arm/xlnx-versal.c | 71 +++-
2 files changed, 75 insertions(+), 1 del
List myself as maintainer for the Xilinx Versal OSPI controller.
Signed-off-by: Francisco Iglesias
Reviewed-by: Edgar E. Iglesias
Reviewed-by: Peter Maydell
---
MAINTAINERS | 6 ++
1 file changed, 6 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index e4b3a4bcdf..6797a270e4 100644
Add a model of Versal's PMC SLCR (system-level control registers).
Signed-off-by: Francisco Iglesias
Signed-off-by: Edgar E. Iglesias
Reviewed-by: Peter Maydell
Reviewed-by: Luc Michel
---
include/hw/misc/xlnx-versal-pmc-iou-slcr.h | 78 ++
hw/misc/xlnx-versal-pmc-iou-slcr.c |
Add in the missing includes in the header for being able to build the DMA
model when reusing it.
Signed-off-by: Francisco Iglesias
Reviewed-by: Peter Maydell
Reviewed-by: Luc Michel
---
include/hw/dma/xlnx_csu_dma.h | 5 +
1 file changed, 5 insertions(+)
diff --git a/include/hw/dma
Add a model of Xilinx Versal's OSPI flash memory controller.
Signed-off-by: Francisco Iglesias
---
include/hw/ssi/xlnx-versal-ospi.h | 111 +++
hw/ssi/xlnx-versal-ospi.c | 1853 +
hw/ssi/meson.build|1 +
3 files changed,
Add support for Micron Xccela flash mt35xu01g.
Signed-off-by: Francisco Iglesias
Reviewed-by: Edgar E. Iglesias
---
hw/block/m25p80.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/hw/block/m25p80.c b/hw/block/m25p80.c
index b77503dc84..c6bf3c6bfa 100644
--- a/hw/block/m25p80.c
+++ b/hw
r
API (and signals).
This patch adds a class 'read' method for allowing to start read transfers
from peripherals embedding and controlling the Xilinx CSU DMA engine as in
above scenario.
Signed-off-by: Francisco Iglesias
---
include/hw/dma/xlnx_csu_dma.h | 19 +--
h
Connect the OSPI flash memory controller model (including the source and
destination DMA).
Signed-off-by: Francisco Iglesias
Reviewed-by: Peter Maydell
---
include/hw/arm/xlnx-versal.h | 20 ++
hw/arm/xlnx-versal.c | 93
2 files
Connect Micron Xccela mt35xu01g flashes to the OSPI flash memory
controller.
Signed-off-by: Francisco Iglesias
Reviewed-by: Edgar E. Iglesias
Reviewed-by: Peter Maydell
---
hw/arm/xlnx-versal-virt.c | 23 +++
1 file changed, 23 insertions(+)
diff --git a/hw/arm/xlnx
a model of
Versal's OSPI controller is added and connected to the Versal virt
machine. The series then ends with adding initial support for the Micron
Xccelera mt35xu01g flash and flashes of this type are connected to the
OSPI in the Versal virt machine.
Best regards,
Francisco Iglesias
Chan
Add an orgate and 'or' the interrupts from the BBRAM and RTC models.
Signed-off-by: Francisco Iglesias
Reviewed-by: Peter Maydell
Reviewed-by: Luc Michel
---
include/hw/arm/xlnx-versal.h | 5 +++--
hw/arm/xlnx-versal-virt.c| 2 +-
hw/arm/xlnx-versal.c
On Thu, Jan 27, 2022 at 05:27:55PM +, Peter Maydell wrote:
> On Fri, 21 Jan 2022 at 16:11, Francisco Iglesias
> wrote:
> >
> > Hi,
> >
> > This series attempts to add support for Xilinx Versal's PMC SLCR
> > (system-level control registers) and O
; +++ b/hw/block/m25p80.c
> @@ -1558,6 +1558,7 @@ static int m25p80_pre_save(void *opaque)
>
> static Property m25p80_properties[] = {
> /* This is default value for Micron flash */
> +DEFINE_PROP_BOOL("write-enable", Flash, write_enable, false),
te(s, OFFSET_TCNT >> 2, s->tcnt);
> diff --git a/hw/timer/slavio_timer.c b/hw/timer/slavio_timer.c
> index 90fdce4c442..8c4f6eb06b6 100644
> --- a/hw/timer/slavio_timer.c
> +++ b/hw/timer/slavio_timer.c
> @@ -405,7 +405,7 @@ static void slavio_timer_init(Object *obj)
> tc->
Hi Cedric,
On the subject s/speed/aspeed/. Otherwise:
Reviewed-by: Francisco Iglesias
/BR
On [2021 Oct 18] Mon 15:26:09, Cédric Le Goater wrote:
> Signed-off-by: Cédric Le Goater
> ---
> hw/sd/aspeed_sdhci.c | 5 +
> hw/sd/trace-events | 4
> 2 files change
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