[PATCH intel_iommu 1/7] intel_iommu: fix FRCD construction macro.

The constant must be unsigned, otherwise the two's complement overrides the other fields when a PASID is present Signed-off-by: Clément Mathieu--Drif --- hw/i386/intel_iommu_internal.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/i386/intel_iommu_internal.h b/hw/i386/in

[PATCH intel_iommu 3/7] intel_iommu: make types match

The 'level' field in vtd_iotlb_key is an uint8_t. We don't need to store level as an int in vtd_lookup_iotlb Signed-off-by: Clément Mathieu--Drif --- hw/i386/intel_iommu.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c index 6f13

[PATCH intel_iommu 5/7] intel_iommu: extract device IOTLB invalidation logic

This piece of code can be shared by both IOTLB invalidation and PASID-based IOTLB invalidation Signed-off-by: Clément Mathieu--Drif --- hw/i386/intel_iommu.c | 57 +-- 1 file changed, 33 insertions(+), 24 deletions(-) diff --git a/hw/i386/intel_iommu.c b/

[PATCH intel_iommu 6/7] intel_iommu: add PASID-based IOTLB invalidation

Signed-off-by: Clément Mathieu--Drif --- hw/i386/intel_iommu.c | 130 ++--- hw/i386/intel_iommu_internal.h | 51 +++-- 2 files changed, 150 insertions(+), 31 deletions(-) diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c index aaac61bf6a..4b

[PATCH intel_iommu 0/7] FLTS for VT-d

This series is the first of a list that add support for SVM in the Intel IOMMU. Here, we implement support for first-stage translation in VT-d. The PASID-based IOTLB invalidation is also added in this series as it is a requirement of FLTS. The last patch introduces the 'flts' option to enable the

[PATCH intel_iommu 2/7] intel_iommu: rename slpte to pte before adding FLTS

Some variables struct fields and functions can be used for both slpte and flpte. We can modify certain identifiers to make them more generic. - slpte in IOMMUTLBEntry becomes pte and will be used for both FL and SL - VTD_SL_PT_LEVEL, VTD_SL_PT_PAGE_SIZE_MASK and VTD_SL_LEVEL_BITS can be renamed

[PATCH intel_iommu 7/7] intel_iommu: add a CLI option to enable FLTS

Signed-off-by: Clément Mathieu--Drif --- hw/i386/intel_iommu.c | 6 ++ include/hw/i386/intel_iommu.h | 1 + 2 files changed, 7 insertions(+) diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c index 4b54a45107..c35ccc3a98 100644 --- a/hw/i386/intel_iommu.c +++ b/hw/i386/intel_

[PATCH intel_iommu 4/7] intel_iommu: add support for first-stage translation

This translation mode will only be made available in scalable mode Signed-off-by: Clément Mathieu--Drif --- hw/i386/intel_iommu.c | 364 - hw/i386/intel_iommu_internal.h | 51 - 2 files changed, 362 insertions(+), 53 deletions(-) diff --git a/hw/i38

Re: [PATCH intel_iommu 3/7] intel_iommu: make types match

On 22/04/2024 19:03, Philippe Mathieu-Daudé wrote: > On 22/4/24 17:52, CLEMENT MATHIEU--DRIF wrote: >> The 'level' field in vtd_iotlb_key is an uint8_t. >> We don't need to store level as an int in vtd_lookup_iotlb >> >> Signed-off-by: Clément Mathieu--D

Re: [PATCH intel_iommu 5/7] intel_iommu: extract device IOTLB invalidation logic

On 22/04/2024 18:59, Philippe Mathieu-Daudé wrote: > On 22/4/24 17:52, CLEMENT MATHIEU--DRIF wrote: >> This piece of code can be shared by both IOTLB invalidation and >> PASID-based IOTLB invalidation >> >> Signed-off-by: Clément Mathieu--Drif >> --

Re: [PATCH intel_iommu 3/7] intel_iommu: make types match

On 23/04/2024 10:19, Philippe Mathieu-Daudé wrote: > > On 23/4/24 07:05, CLEMENT MATHIEU--DRIF wrote: >> >> On 22/04/2024 19:03, Philippe Mathieu-Daudé wrote: >>> On 22/4/24 17:52, CLEMENT MATHIEU--DRIF wrote: >>>> The 'level' field in vtd_iot

Re: [PATCH intel_iommu 0/7] FLTS for VT-d

ing your remaining part, i.e., ATS, PRI emulation, etc on > to our rfcv2? > > Thanks > Zhenzhong > >> -Original Message- >> From: Cédric Le Goater >> Subject: Re: [PATCH intel_iommu 0/7] FLTS for VT-d >> >> Hello, >> >> Adding a few

[PATCH ats_vtd v1 15/24] pci: add a pci-level initialization function for iommu notifiers

We add a convenient way to initialize an device-iotlb notifier. This is meant to be used by ATS-capable devices. pci_device_iommu_memory_region_pasid is introduces in this commit and will be used in several other SVM-related functions exposed in the PCI API. Signed-off-by: Clément Mathieu--Drif

[PATCH ats_vtd v1 17/24] intel_iommu: implement the get_memory_region_pasid iommu operation

Signed-off-by: Clément Mathieu--Drif --- hw/i386/intel_iommu.c | 15 +++ 1 file changed, 15 insertions(+) diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c index e9fa48b378..a62cbf303d 100644 --- a/hw/i386/intel_iommu.c +++ b/hw/i386/intel_iommu.c @@ -6000,9 +6000,24 @@ stat

[PATCH ats_vtd v1 12/24] intel_iommu: add support for PASID-based device IOTLB invalidation

Signed-off-by: Clément Mathieu--Drif --- hw/i386/intel_iommu.c | 42 ++ hw/i386/intel_iommu_internal.h | 10 2 files changed, 47 insertions(+), 5 deletions(-) diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c index fe97930774..e7c1a5582a

[PATCH ats_vtd v1 20/24] atc: generic ATC that can be used by PCIe devices that support SVM

As the SVM-capable devices will need to cache translations, we provide an first implementation. This cache uses a two-level design based on hash tables. The first level is indexed by a PASID and the second by a virtual addresse. Signed-off-by: Clément Mathieu--Drif --- tests/unit/meson.build |

[PATCH ats_vtd v1 21/24] memory: add an API for ATS support

IOMMU have to implement iommu_ats_request_translation to support ATS. Devices can use IOMMU_TLB_ENTRY_TRANSLATION_ERROR to check the tlb entries returned by a translation request. Signed-off-by: Clément Mathieu--Drif --- include/exec/memory.h | 26 ++ system/memory.c

[PATCH ats_vtd v1 23/24] intel_iommu: set the address mask even when a translation fails

Implements the behavior defined in section 10.2.3.5 of PCIe spec rev 5. This is needed by devices that support ATS. Signed-off-by: Clément Mathieu--Drif --- hw/i386/intel_iommu.c | 10 -- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_

[PATCH ats_vtd v1 13/24] pci: cache the bus mastering status in the device

Signed-off-by: Clément Mathieu--Drif --- hw/pci/pci.c| 24 ++-- include/hw/pci/pci_device.h | 1 + 2 files changed, 15 insertions(+), 10 deletions(-) diff --git a/hw/pci/pci.c b/hw/pci/pci.c index 045d69f4c1..e5f72f9f1d 100644 --- a/hw/pci/pci.c +++ b/hw/pci/

[PATCH ats_vtd v1 16/24] intel_iommu: implement the get_address_space_pasid iommu operation

Signed-off-by: Clément Mathieu--Drif --- hw/i386/intel_iommu.c | 13 ++--- include/hw/i386/intel_iommu.h | 2 +- 2 files changed, 11 insertions(+), 4 deletions(-) diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c index e7c1a5582a..e9fa48b378 100644 --- a/hw/i386/intel_i

[PATCH ats_vtd v1 03/24] intel_iommu: check if the input address is canonical

First stage translation must fail if the address to translate is not canonical. Signed-off-by: Clément Mathieu--Drif --- hw/i386/intel_iommu.c | 22 ++ hw/i386/intel_iommu_internal.h | 2 ++ 2 files changed, 24 insertions(+) diff --git a/hw/i386/intel_iommu.c b/hw/

[PATCH ats_vtd v1 00/24] ATS support for VT-d

This series belongs to a list of series that add SVM support for VT-d. As a starting point, we use the series called 'intel_iommu: Enable stage-1 translation' (rfc2) by Zhenzhong Duan and Yi Liu. Here we focus on the implementation of ATS support in the IOMMU and on a PCI-level API for ATS to b

[PATCH ats_vtd v1 24/24] intel_iommu: add support for ATS

Signed-off-by: Clément Mathieu--Drif --- hw/i386/intel_iommu.c | 75 -- hw/i386/intel_iommu_internal.h | 1 + 2 files changed, 73 insertions(+), 3 deletions(-) diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c index aac7677063..400b27fc95 100644

[PATCH ats_vtd v1 05/24] intel_iommu: extract device IOTLB invalidation logic

This piece of code can be shared by both IOTLB invalidation and PASID-based IOTLB invalidation Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Clément Mathieu--Drif --- hw/i386/intel_iommu.c | 57 +-- 1 file changed, 33 insertions(+), 24 deletions(-)

[PATCH ats_vtd v1 09/24] pcie: helper functions to check if PASID and ATS are enabled

ats_enabled and pasid_enabled check whether the capabilities are present or not. If so, we read the configuration space to get the status of the feature (enabled or not). Signed-off-by: Clément Mathieu--Drif --- hw/pci/pcie.c | 18 ++ include/hw/pci/pcie.h | 3 +++ 2 fil

[PATCH ats_vtd v1 01/24] intel_iommu: fix FRCD construction macro.

The constant must be unsigned, otherwise the two's complement overrides the other fields when a PASID is present Signed-off-by: Clément Mathieu--Drif --- hw/i386/intel_iommu_internal.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/i386/intel_iommu_internal.h b/hw/i386/in

[PATCH ats_vtd v1 11/24] intel_iommu: add an internal API to find an address space with PASID

This will be used to implement the device IOTLB invalidation Signed-off-by: Clément Mathieu--Drif --- hw/i386/intel_iommu.c | 39 --- 1 file changed, 24 insertions(+), 15 deletions(-) diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c index 98c4a70fe0

[PATCH ats_vtd v1 14/24] pci: add IOMMU operations to get address spaces and memory regions with PASID

Signed-off-by: Clément Mathieu--Drif --- hw/pci/pci.c | 20 include/hw/pci/pci.h | 34 ++ 2 files changed, 54 insertions(+) diff --git a/hw/pci/pci.c b/hw/pci/pci.c index e5f72f9f1d..9ed788c95d 100644 --- a/hw/pci/pci.c +++ b/hw/pci/pc

[PATCH ats_vtd v1 08/24] pcie: add helper to declare PASID capability for a pcie device

Signed-off-by: Clément Mathieu--Drif --- hw/pci/pcie.c | 24 include/hw/pci/pcie.h | 6 +- include/hw/pci/pcie_regs.h | 3 +++ 3 files changed, 32 insertions(+), 1 deletion(-) diff --git a/hw/pci/pcie.c b/hw/pci/pcie.c index 4b2f0805c6..c8e9d4c0f7

[PATCH ats_vtd v1 06/24] intel_iommu: do not consider wait_desc as an invalid descriptor

Signed-off-by: Clément Mathieu--Drif --- hw/i386/intel_iommu.c | 5 + 1 file changed, 5 insertions(+) diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c index 85a7ebac67..c475a354a0 100644 --- a/hw/i386/intel_iommu.c +++ b/hw/i386/intel_iommu.c @@ -3365,6 +3365,11 @@ static bool vtd_

[PATCH ats_vtd v1 19/24] intel_iommu: fill the PASID field when creating an instance of IOMMUTLBEntry

Signed-off-by: Clément Mathieu--Drif --- hw/i386/intel_iommu.c | 5 + 1 file changed, 5 insertions(+) diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c index a62cbf303d..02c5f0fa4f 100644 --- a/hw/i386/intel_iommu.c +++ b/hw/i386/intel_iommu.c @@ -2302,6 +2302,7 @@ out: entry->

[PATCH ats_vtd v1 10/24] intel_iommu: declare supported PASID size

Signed-off-by: Clément Mathieu--Drif --- hw/i386/intel_iommu.c | 2 +- hw/i386/intel_iommu_internal.h | 1 + 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c index c475a354a0..98c4a70fe0 100644 --- a/hw/i386/intel_iommu.c +++ b/h

[PATCH ats_vtd v1 04/24] intel_iommu: set accessed and dirty bits during first stage translation

Signed-off-by: Clément Mathieu--Drif --- hw/i386/intel_iommu.c | 26 ++ hw/i386/intel_iommu_internal.h | 3 +++ 2 files changed, 29 insertions(+) diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c index 240ecb8f72..cad70e0d05 100644 --- a/hw/i386/intel_i

[PATCH ats_vtd v1 07/24] memory: add permissions in IOMMUAccessFlags

This will be necessary for devices implementing ATS. We also define a new macro IOMMU_ACCESS_FLAG_FULL in addition to IOMMU_ACCESS_FLAG to support more access flags. IOMMU_ACCESS_FLAG is kept for convenience and backward compatibility. Here are the flags added (defined by the PCIe 5 specification)

[PATCH ats_vtd v1 02/24] intel_iommu: make types match

The 'level' field in vtd_iotlb_key is an uint8_t. We don't need to store level as an int in vtd_lookup_iotlb (avoids a 'loosing precision' warning). VTDIOTLBPageInvInfo.mask is used in binary operations with addresses. Signed-off-by: Clément Mathieu--Drif --- hw/i386/intel_iommu.c | 2

[PATCH ats_vtd v1 22/24] pci: add a pci-level API for ATS

Devices implementing ATS can send translation requests using pci_ats_request_translation_pasid. The invalidation events are sent back to the device using the iommu notifier managed with pci_register_iommu_tlb_event_notifier and pci_unregister_iommu_tlb_event_notifier Signed-off-by: Clément Mathie

[PATCH ats_vtd v1 18/24] memory: Allow to store the PASID in IOMMUTLBEntry

This will be useful for devices that support ATS Signed-off-by: Clément Mathieu--Drif --- include/exec/memory.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/exec/memory.h b/include/exec/memory.h index 304504de02..f4b33415d7 100644 --- a/include/exec/memory.h +++ b/include/exec/mem

Re: [PATCH v4 19/19] intel_iommu: Check compatibility with host IOMMU capabilities

Hi Zhenzhong, On 07/05/2024 11:20, Zhenzhong Duan wrote: Caution: External email. Do not open attachments or click links, unless this email comes from a known sender and you know the content is safe. If check fails, host device (either VFIO or VDPA device) is not compatible with current vIOMMU

[PATCH ats_vtd v5 00/22] ATS support for VT-d

From: Clement Mathieu--Drif This series belongs to a list of series that add SVM support for VT-d. As a starting point, we use the series called 'intel_iommu: Enable stage-1 translation' (rfc2) by Zhenzhong Duan and Yi Liu. Here we focus on the implementation of ATS support in the

[PATCH ats_vtd v5 03/22] intel_iommu: return page walk level even when the translation fails

From: Clément Mathieu--Drif We use this information in vtd_do_iommu_translate to populate the IOMMUTLBEntry and indicate the correct page mask. This prevents ATS devices from sending many useless translation requests when a megapage or gigapage iova is not mapped to a physical address. Signed-of

[PATCH ats_vtd v5 16/22] intel_iommu: fill the PASID field when creating an instance of IOMMUTLBEntry

From: Clément Mathieu--Drif Signed-off-by: Clément Mathieu--Drif --- hw/i386/intel_iommu.c | 9 + 1 file changed, 9 insertions(+) diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c index 2e4f535dd1..f77972130f 100644 --- a/hw/i386/intel_iommu.c +++ b/hw/i386/intel_iommu.c @@ -2

[PATCH ats_vtd v5 22/22] intel_iommu: add support for ATS

From: Clément Mathieu--Drif Signed-off-by: Clément Mathieu--Drif --- hw/i386/intel_iommu.c | 75 -- hw/i386/intel_iommu_internal.h | 1 + 2 files changed, 73 insertions(+), 3 deletions(-) diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c index

[PATCH ats_vtd v5 01/22] intel_iommu: fix FRCD construction macro.

From: Clément Mathieu--Drif The constant must be unsigned, otherwise the two's complement overrides the other fields when a PASID is present Signed-off-by: Clément Mathieu--Drif --- hw/i386/intel_iommu_internal.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/i386/intel

[PATCH ats_vtd v5 02/22] intel_iommu: make types match

From: Clément Mathieu--Drif The 'level' field in vtd_iotlb_key is an unsigned integer. We don't need to store level as an int in vtd_lookup_iotlb. VTDIOTLBPageInvInfo.mask is used in binary operations with addresses. Signed-off-by: Clément Mathieu--Drif --- hw/i386/intel_iommu.c | 2

[PATCH ats_vtd v5 10/22] pci: add IOMMU operations to get address spaces and memory regions with PASID

From: Clément Mathieu--Drif Signed-off-by: Clément Mathieu--Drif --- hw/pci/pci.c | 19 +++ include/hw/pci/pci.h | 34 ++ 2 files changed, 53 insertions(+) diff --git a/hw/pci/pci.c b/hw/pci/pci.c index 51feede3cf..3fe47d4002 100644 --- a

[PATCH ats_vtd v5 05/22] memory: add permissions in IOMMUAccessFlags

From: Clément Mathieu--Drif This will be necessary for devices implementing ATS. We also define a new macro IOMMU_ACCESS_FLAG_FULL in addition to IOMMU_ACCESS_FLAG to support more access flags. IOMMU_ACCESS_FLAG is kept for convenience and backward compatibility. Here are the flags added (define

[PATCH ats_vtd v5 15/22] memory: Allow to store the PASID in IOMMUTLBEntry

From: Clément Mathieu--Drif This will be useful for devices that support ATS Signed-off-by: Clément Mathieu--Drif --- include/exec/memory.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/exec/memory.h b/include/exec/memory.h index bf91c4bed7..003ee06610 100644 --- a/include/exec/m

[PATCH ats_vtd v5 20/22] pci: add a pci-level API for ATS

From: Clément Mathieu--Drif Devices implementing ATS can send translation requests using pci_ats_request_translation_pasid. The invalidation events are sent back to the device using the iommu notifier managed with pci_register_iommu_tlb_event_notifier and pci_unregister_iommu_tlb_event_notifier

[PATCH ats_vtd v5 04/22] intel_iommu: do not consider wait_desc as an invalid descriptor

From: Clément Mathieu--Drif Signed-off-by: Clément Mathieu--Drif Reviewed-by: Zhenzhong Duan --- hw/i386/intel_iommu.c | 5 + 1 file changed, 5 insertions(+) diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c index 98996ededc..71cebe2fd3 100644 --- a/hw/i386/intel_iommu.c +++ b/hw

[PATCH ats_vtd v5 21/22] intel_iommu: set the address mask even when a translation fails

From: Clément Mathieu--Drif Implements the behavior defined in section 10.2.3.5 of PCIe spec rev 5. This is needed by devices that support ATS. Signed-off-by: Clément Mathieu--Drif --- hw/i386/intel_iommu.c | 10 -- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/hw/i386/

[PATCH ats_vtd v5 12/22] pci: add a pci-level initialization function for iommu notifiers

From: Clément Mathieu--Drif We add a convenient way to initialize an device-iotlb notifier. This is meant to be used by ATS-capable devices. pci_device_iommu_memory_region_pasid is introduces in this commit and will be used in several other SVM-related functions exposed in the PCI API. Signed-o

[PATCH ats_vtd v5 17/22] atc: generic ATC that can be used by PCIe devices that support SVM

From: Clément Mathieu--Drif As the SVM-capable devices will need to cache translations, we provide an first implementation. This cache uses a two-level design based on hash tables. The first level is indexed by a PASID and the second by a virtual addresse. Signed-off-by: Clément Mathieu--Drif

[PATCH ats_vtd v5 18/22] atc: add unit tests

From: Clément Mathieu--Drif Signed-off-by: Clément Mathieu--Drif --- tests/unit/meson.build | 1 + tests/unit/test-atc.c | 527 + 2 files changed, 528 insertions(+) create mode 100644 tests/unit/test-atc.c diff --git a/tests/unit/meson.build b/tests/

[PATCH ats_vtd v5 11/22] memory: store user data pointer in the IOMMU notifiers

From: Clément Mathieu--Drif This will help developers of svm devices to track a state Signed-off-by: Clément Mathieu--Drif --- include/exec/memory.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/exec/memory.h b/include/exec/memory.h index aa8e114e77..bf91c4bed7 100644 --- a/inclu

[PATCH ats_vtd v5 07/22] pcie: helper functions to check if PASID and ATS are enabled

From: Clément Mathieu--Drif ats_enabled and pasid_enabled check whether the capabilities are present or not. If so, we read the configuration space to get the status of the feature (enabled or not). Signed-off-by: Clément Mathieu--Drif --- hw/pci/pcie.c | 18 ++ include

[PATCH ats_vtd v5 13/22] intel_iommu: implement the get_address_space_pasid iommu operation

From: Clément Mathieu--Drif Signed-off-by: Clément Mathieu--Drif --- hw/i386/intel_iommu.c | 13 ++--- include/hw/i386/intel_iommu.h | 2 +- 2 files changed, 11 insertions(+), 4 deletions(-) diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c index 2a78fc823f..e047d2ca8

[PATCH ats_vtd v5 19/22] memory: add an API for ATS support

From: Clément Mathieu--Drif IOMMU have to implement iommu_ats_request_translation to support ATS. Devices can use IOMMU_TLB_ENTRY_TRANSLATION_ERROR to check the tlb entries returned by a translation request. Signed-off-by: Clément Mathieu--Drif --- include/exec/memory.h | 26 +

[PATCH ats_vtd v5 08/22] intel_iommu: declare supported PASID size

From: Clément Mathieu--Drif Signed-off-by: Clément Mathieu--Drif --- hw/i386/intel_iommu.c | 2 +- hw/i386/intel_iommu_internal.h | 1 + 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c index 71cebe2fd3..2a78fc823f 100644 --- a

[PATCH ats_vtd v5 14/22] intel_iommu: implement the get_memory_region_pasid iommu operation

From: Clément Mathieu--Drif Signed-off-by: Clément Mathieu--Drif --- hw/i386/intel_iommu.c | 15 +++ 1 file changed, 15 insertions(+) diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c index e047d2ca83..2e4f535dd1 100644 --- a/hw/i386/intel_iommu.c +++ b/hw/i386/intel_iommu

[PATCH ats_vtd v5 09/22] pci: cache the bus mastering status in the device

From: Clément Mathieu--Drif Signed-off-by: Clément Mathieu--Drif --- hw/pci/pci.c| 24 ++-- include/hw/pci/pci_device.h | 1 + 2 files changed, 15 insertions(+), 10 deletions(-) diff --git a/hw/pci/pci.c b/hw/pci/pci.c index c8a8aab306..51feede3cf 100644 --

[PATCH ats_vtd v5 06/22] pcie: add helper to declare PASID capability for a pcie device

From: Clément Mathieu--Drif Signed-off-by: Clément Mathieu--Drif --- hw/pci/pcie.c | 24 +++ include/hw/pci/pcie.h | 6 +- include/hw/pci/pcie_regs.h| 3 +++ include/standard-headers/linux/pci_regs.h | 1

Re: [PATCH ats_vtd v5 00/22] ATS support for VT-d

From: Michael S. Tsirkin Sent: 01 July 2024 22:02 To: CLEMENT MATHIEU--DRIF Cc: qemu-devel@nongnu.org ; jasow...@redhat.com ; zhenzhong.d...@intel.com ; kevin.t...@intel.com ; yi.l@intel.com ; joao.m.mart...@oracle.com ; pet...@redhat.com Subject: Re

Re: [PATCH ats_vtd v5 00/22] ATS support for VT-d

On 02/07/2024 14:16, Michael S. Tsirkin wrote: > Caution: External email. Do not open attachments or click links, unless this > email comes from a known sender and you know the content is safe. > > > On Tue, Jul 02, 2024 at 05:52:29AM +, CLEMENT MATHIEU--DRIF wrote: >>

Re: [PATCH ats_vtd v5 01/22] intel_iommu: fix FRCD construction macro.

On 02/07/2024 15:01, Yi Liu wrote: > Caution: External email. Do not open attachments or click links, > unless this email comes from a known sender and you know the content > is safe. > > > On 2024/7/2 13:52, CLEMENT MATHIEU--DRIF wrote: >> From: Clément Mathieu--Drif

Re: [PATCH ats_vtd v5 00/22] ATS support for VT-d

On 02/07/2024 15:44, Yi Liu wrote: > Caution: External email. Do not open attachments or click links, > unless this email comes from a known sender and you know the content > is safe. > > > On 2024/7/2 13:52, CLEMENT MATHIEU--DRIF wrote: >> From: Clement Mathieu--Drif &

Re: [PATCH ats_vtd v5 00/22] ATS support for VT-d

M +0000, CLEMENT MATHIEU--DRIF wrote: >>> >>> >>> ━━━ >>> >>> From: Michael S. Tsirkin >>> Sent: 01 July 2024 22:02 >>> To: CLEMENT MATHIEU--DRIF >>>

Re: [PATCH ats_vtd v5 04/22] intel_iommu: do not consider wait_desc as an invalid descriptor

On 02/07/2024 15:33, Yi Liu wrote: > Caution: External email. Do not open attachments or click links, > unless this email comes from a known sender and you know the content > is safe. > > > On 2024/7/2 13:52, CLEMENT MATHIEU--DRIF wrote: >> From: Clément Mathieu--D

Re: [PATCH ats_vtd v5 03/22] intel_iommu: return page walk level even when the translation fails

On 03/07/2024 13:59, Yi Liu wrote: > Caution: External email. Do not open attachments or click links, > unless this email comes from a known sender and you know the content > is safe. > > > On 2024/7/2 13:52, CLEMENT MATHIEU--DRIF wrote: >> From: Clément Mathieu-

Re: [PATCH ats_vtd v5 04/22] intel_iommu: do not consider wait_desc as an invalid descriptor

On 03/07/2024 09:29, Yi Liu wrote: > Caution: External email. Do not open attachments or click links, > unless this email comes from a known sender and you know the content > is safe. > > > On 2024/7/2 23:29, CLEMENT MATHIEU--DRIF wrote: >> >> On 02/07/2024 15

Re: [PATCH ats_vtd v5 06/22] pcie: add helper to declare PASID capability for a pcie device

On 03/07/2024 14:04, Yi Liu wrote: > Caution: External email. Do not open attachments or click links, > unless this email comes from a known sender and you know the content > is safe. > > > On 2024/7/2 13:52, CLEMENT MATHIEU--DRIF wrote: >> From: Clément Mathieu--D

Re: [PATCH ats_vtd v5 19/22] memory: add an API for ATS support

On 03/07/2024 14:14, Yi Liu wrote: > Caution: External email. Do not open attachments or click links, > unless this email comes from a known sender and you know the content > is safe. > > > On 2024/7/2 13:52, CLEMENT MATHIEU--DRIF wrote: >> From: Clément Mathieu--D

Re: [PATCH ats_vtd v5 00/22] ATS support for VT-d

design description in the cover-letter would be helpful. Ok, I will elaborate > > On 2024/7/2 13:52, CLEMENT MATHIEU--DRIF wrote: >> From: Clement Mathieu--Drif >> >> This series belongs to a list of series that add SVM support for VT-d. >> >> As a starting

Re: [PATCH v2 16/17] intel_iommu: Introduce a property to control FS1GP cap bit setting

Reviewed-by: Clément Mathieu--Drif On 05/08/2024 08:27, Zhenzhong Duan wrote: > Caution: External email. Do not open attachments or click links, unless this > email comes from a known sender and you know the content is safe. > > > When host IOMMU doesn't support FS1GP but vIOMMU does, host IOMM

Re: [PATCH v2 15/17] intel_iommu: Modify x-scalable-mode to be string option to expose scalable modern mode

On 05/08/2024 08:27, Zhenzhong Duan wrote: Caution: External email. Do not open attachments or click links, unless this email comes from a known sender and you know the content is safe. From: Yi Liu Intel VT-d 3.0 introduces scalable mode, and it has a bunch of ca

Re: [PATCH v2 14/17] intel_iommu: Set default aw_bits to 48 in scalable modren mode

Typo in the title : s/modren/modern Reviewed-by: Clément Mathieu--Drif On 05/08/2024 08:27, Zhenzhong Duan wrote: > Caution: External email. Do not open attachments or click links, unless this > email comes from a known sender and you know the content is safe. > > > According to VTD spec, stage

Re: [PATCH v2 03/17] intel_iommu: Add a placeholder variable for scalable modern mode

On 05/08/2024 08:27, Zhenzhong Duan wrote: > Caution: External email. Do not open attachments or click links, unless this > email comes from a known sender and you know the content is safe. > > > Add an new element scalable_mode in IntelIOMMUState to mark scalable > modern mode, this element wil

Re: [PATCH v2 04/17] intel_iommu: Flush stage-2 cache in PASID-selective PASID-based iotlb invalidation

On 05/08/2024 08:27, Zhenzhong Duan wrote: > Caution: External email. Do not open attachments or click links, unless this > email comes from a known sender and you know the content is safe. > > > Per spec 6.5.2.4, PADID-selective PASID-based iotlb invalidation will > flush stage-2 iotlb entries

Re: [PATCH v2 04/17] intel_iommu: Flush stage-2 cache in PASID-selective PASID-based iotlb invalidation

On 08/08/2024 14:40, Duan, Zhenzhong wrote: > Caution: External email. Do not open attachments or click links, > unless this email comes from a known sender and you know the content > is safe. > > > On 8/6/2024 2:35 PM, CLEMENT MATHIEU--DRIF wrote: >> >> On 05

Re: [PATCH v2 03/17] intel_iommu: Add a placeholder variable for scalable modern mode

On 08/08/2024 14:31, Duan, Zhenzhong wrote: > Caution: External email. Do not open attachments or click links, > unless this email comes from a known sender and you know the content > is safe. > > > On 8/6/2024 2:35 PM, CLEMENT MATHIEU--DRIF wrote: >> >> On 05

Re: [PATCH v2 03/17] intel_iommu: Add a placeholder variable for scalable modern mode

On 13/08/2024 04:20, Duan, Zhenzhong wrote: > Caution: External email. Do not open attachments or click links, unless this > email comes from a known sender and you know the content is safe. > > >> -Original Message- >> From: CLEMENT MATHIEU--DRIF >>

Re: [PATCH v2 03/17] intel_iommu: Add a placeholder variable for scalable modern mode

On 13/08/2024 08:26, Duan, Zhenzhong wrote: > Caution: External email. Do not open attachments or click links, unless this > email comes from a known sender and you know the content is safe. > > >> -Original Message- >> From: CLEMENT MATHIEU--DRIF >>

Re: [PATCH v2 04/17] intel_iommu: Flush stage-2 cache in PASID-selective PASID-based iotlb invalidation

On 13/08/2024 04:12, Duan, Zhenzhong wrote: > Caution: External email. Do not open attachments or click links, unless this > email comes from a known sender and you know the content is safe. > > >> -Original Message- >> From: CLEMENT MATHIEU--DRIF >>

Re: [PATCH v2 04/17] intel_iommu: Flush stage-2 cache in PASID-selective PASID-based iotlb invalidation

On 13/08/2024 09:13, CLEMENT MATHIEU--DRIF wrote: > > On 13/08/2024 04:12, Duan, Zhenzhong wrote: >> Caution: External email. Do not open attachments or click links, unless this >> email comes from a known sender and you know the content is safe. >> >> >>&

Re: [PATCH] intel_iommu: Fix invalidation descriptor type field

On 13/08/2024 09:06, Yi Liu wrote: > Caution: External email. Do not open attachments or click links, > unless this email comes from a known sender and you know the content > is safe. > > > On 2024/8/13 13:53, Zhenzhong Duan wrote: >> According to spec, invalidation descriptor type is 7bits whi

Re: [PATCH v2 2/2] intel_iommu: Make PASID-cache and PIOTLB type invalid in legacy mode

Reviewed-by: Clément Mathieu--Drif Super reactive! Maybe we can continue along this path after the handlers are implemented. It would be great to make sure we don't process PASID related descriptors when not in scalable mode. What are your thoughts? Thanks >cmd On 13/08/2024 09:44, Zhenzhong

Re: [PATCH v2 08/17] intel_iommu: Set accessed and dirty bits during first stage translation

On 14/08/2024 13:45, Yi Liu wrote: > Caution: External email. Do not open attachments or click links, > unless this email comes from a known sender and you know the content > is safe. > > > On 2024/8/5 14:27, Zhenzhong Duan wrote: >> From: Clément Mathieu--Drif >> >> Signed-off-by: Clément Mat

Re: [PATCH v2 08/17] intel_iommu: Set accessed and dirty bits during first stage translation

On 16/08/2024 04:37, Duan, Zhenzhong wrote: > Caution: External email. Do not open attachments or click links, unless this > email comes from a known sender and you know the content is safe. > > >> -Original Message- >> From: Liu, Yi L >> Subject: Re: [PATCH v2 08/17] intel_iommu: Set a

[PATCH] MAINTAINERS: Add myself as a reviewer of VT-d

Signed-off-by: Clément Mathieu--Drif --- MAINTAINERS | 1 + 1 file changed, 1 insertion(+) diff --git a/MAINTAINERS b/MAINTAINERS index 3584d6a6c6..b12973f595 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -3672,6 +3672,7 @@ VT-d Emulation M: Michael S. Tsirkin R: Jason Wang R: Yi Liu +R: C

[PATCH v1 3/8] pcie: add a way to get the outstanding page request allocation (pri) from the config space.

Signed-off-by: Clément Mathieu--Drif --- hw/pci/pcie.c | 8 include/hw/pci/pcie.h | 1 + 2 files changed, 9 insertions(+) diff --git a/hw/pci/pcie.c b/hw/pci/pcie.c index 3fb6588c31..d11b11fc34 100644 --- a/hw/pci/pcie.c +++ b/hw/pci/pcie.c @@ -1227,6 +1227,14 @@ void pcie_pri_i

[PATCH v1 2/8] pcie: helper functions to check to check if PRI is enabled

pri_enabled can be used to check whether the capability is present and enabled on a PCIe device Signed-off-by: Clément Mathieu--Drif --- hw/pci/pcie.c | 9 + include/hw/pci/pcie.h | 1 + 2 files changed, 10 insertions(+) diff --git a/hw/pci/pcie.c b/hw/pci/pcie.c index 053bca694

[PATCH v1 1/8] pcie: add a helper to declare the PRI capability for a pcie device

the pri configuration offset is also stored into the PCIExpressDevice to make it easier to get the PRI status register Signed-off-by: Clément Mathieu--Drif --- hw/pci/pcie.c | 25 + include/hw/pci/pcie.h | 5 - include/hw/pci/pcie_regs.h | 4

[PATCH v1 5/8] pci: add a PCI-level API for PRI

A device can send a PRI request to the IOMMU using pci_pri_request_page_pasid. The PRI response is sent back using the notifier managed with pci_pri_register_notifier and pci_pri_unregister_notifier. Signed-off-by: Clément Mathieu--Drif --- hw/pci/pci.c | 37

[PATCH v1 8/8] intel_iommu: add PRI operations support

Implement the iommu_pri_request_page IOMMU operation and the behavior when receiving a page group response descriptor Signed-off-by: Clément Mathieu--Drif --- hw/i386/intel_iommu.c | 235 + hw/i386/intel_iommu_internal.h | 2 + 2 files changed, 237 inse

[PATCH v1 7/8] intel_iommu: declare registers for PRI

Signed-off-by: Clément Mathieu--Drif --- hw/i386/intel_iommu.c | 67 +++ 1 file changed, 67 insertions(+) diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c index 2e78ebe6d2..899655928d 100644 --- a/hw/i386/intel_iommu.c +++ b/hw/i386/intel_iommu.c

[PATCH v1 6/8] intel_iommu: declare PRI constants and structures

Signed-off-by: Clément Mathieu--Drif --- hw/i386/intel_iommu_internal.h | 52 +- 1 file changed, 51 insertions(+), 1 deletion(-) diff --git a/hw/i386/intel_iommu_internal.h b/hw/i386/intel_iommu_internal.h index 461158f588..9e01251335 100644 --- a/hw/i386/intel_io

[PATCH v1 0/8] PRI support for VT-d

This series belongs to a list of series that add SVM support for VT-d. Here we focus on the implementation of PRI support in the IOMMU and on a PCI-level API for PRI to be used by virtual devices. This work is based on the VT-d specification version 4.1 (March 2023). Here is a link to a GitHub r

[PATCH v1 4/8] pci: declare structures and IOMMU operation for PRI

The API deliberately designed to be similar to the ATS one. We define a struct that stores a function pointer to the device's callback. Registering and unregistering a notifier is done using a pair of functions that will be added in a future commit of this series. An IOMMU can support PRI by imple

Re: [PATCH intel_iommu 0/7] FLTS for VT-d

On 02/06/2024 16:10, Michael S. Tsirkin wrote: > Caution: External email. Do not open attachments or click links, unless this > email comes from a known sender and you know the content is safe. > > > On Mon, Apr 22, 2024 at 03:52:52PM +, CLEMENT MATHIEU--DRIF wrote: >&g

[PATCH ats_vtd v5 01/22] intel_iommu: fix FRCD construction macro.

From: Clément Mathieu--Drif The constant must be unsigned, otherwise the two's complement overrides the other fields when a PASID is present Signed-off-by: Clément Mathieu--Drif --- hw/i386/intel_iommu_internal.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/i386/intel

[PATCH ats_vtd v5 19/22] memory: add an API for ATS support

From: Clément Mathieu--Drif IOMMU have to implement iommu_ats_request_translation to support ATS. Devices can use IOMMU_TLB_ENTRY_TRANSLATION_ERROR to check the tlb entries returned by a translation request. Signed-off-by: Clément Mathieu--Drif --- include/exec/memory.h | 26 +

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