The following changes since commit 3e246da2c3f85298b52f8a1154b832acf36aa656:
Merge tag 'for-upstream' of https://gitlab.com/bonzini/qemu into staging
(2024-06-08 07:40:08 -0700)
are available in the Git repository at:
https://github.com/quic/qemu tags/pull-hex-20240608
for you to fetch cha
eviewed-by: Taylor Simpson
Reviewed-by: Brian Cain
Message-Id:
<277b7aeda2c717a96d4dde936b3ac77707cb6517.1714755107.git.quic_mathb...@quicinc.com>
Signed-off-by: Brian Cain
---
linux-user/hexagon/cpu_loop.c | 4 ++
target/hexagon/cpu.h | 7 ++
target/hexagon/cpu_bits
habetical order on the register
type: 'd', 'e', 'x', and 'y'. No longer following that makes us select
the wrong register index and the HVX store new instruction does not
update the memory like expected.
Signed-off-by: Matheus Tavares Bernardino
Review
From: Anton Johansson
Signed-off-by: Anton Johansson
Reviewed-by: Taylor Simpson
Reviewed-by: Brian Cain
Message-Id: <20240523125901.27797-3-a...@rev.ng>
Signed-off-by: Brian Cain
---
target/hexagon/idef-parser/parser-helpers.h | 13 -
1 file changed, 13 deletions(-)
diff
From: Anton Johansson
Only predicate instruction arguments need to be initialized by
idef-parser. This commit removes registers from the init_list and
simplifies gen_inst_init_args() slightly.
Signed-off-by: Anton Johansson
Reviewed-by: Taylor Simpson
Reviewed-by: Brian Cain
Message-Id
Reviewed-by: Brian Cain
Message-Id: <20240523125901.27797-2-a...@rev.ng>
Signed-off-by: Brian Cain
---
target/hexagon/idef-parser/idef-parser.h | 10 --
1 file changed, 10 deletions(-)
diff --git a/target/hexagon/idef-parser/idef-parser.h
b/target/hexagon/idef-parser/idef-parser.h
,
gen_inst_init_args() isn't called and init_list will never be freed.
Free init_list from free_instruction() if it hasn't already been freed.
A comment in free_instruction is also updated.
Signed-off-by: Anton Johansson
Reviewed-by: Taylor Simpson
Reviewed-by: Brian Cain
Message-Id: <20240523125
ff00
(lldb) reg read -s 1
Predicate Registers:
p0 = 0x00
p1 = 0xff
p2 = 0x00
p3 = 0xff
Signed-off-by: Taylor Simpson
Reviewed-by: Brian Cain
---
target/hexagon/gdbstub.c | 19 ++-
gdb-xml/hexagon-core.xml | 6 +-
2 files changed,
Changes in v2:
* Fixed the HEX_EVENT_{INVALID*,PRIV*,etc} - several of these were actually
cause codes, just like TRAP0.
* I combined "Rename HEX_EXCP_ => HEX_EVENT_" and "rename
HEX_EVENT_TRAP0=>HEX_CAUSE_TRAP0"
into a single commit.
Brian Cain (2):
target
Signed-off-by: Brian Cain
---
target/hexagon/cpu_bits.h | 22 ++
1 file changed, 14 insertions(+), 8 deletions(-)
diff --git a/target/hexagon/cpu_bits.h b/target/hexagon/cpu_bits.h
index 2e60c0fafe..ff596e2a94 100644
--- a/target/hexagon/cpu_bits.h
+++ b/target/hexagon
The values previously used for "HEX_EXCP_*" were the cause code
definitions and not the event numbers. So in this commit, we update
the names to reflect the cause codes. In HEX_EVENT_TRAP0's case, we add
a new "HEX_EVENT_*" with the correct event number.
Signed-off-b
).
Signed-off-by: Matheus Tavares Bernardino
---
Reviewed-by: Brian Cain
target/hexagon/cpu_bits.h| 15 ++-
target/hexagon/helper.h | 15 ++-
target/hexagon/mmvec/mmvec.h | 15 ++-
tests/tcg/hexagon
de = readdir64(dir);
| ^
Signed-off-by: Brian Cain
---
tests/tcg/multiarch/linux/linux-test.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/tests/tcg/multiarch/linux/linux-test.c
b/tests/tcg/multiarch/linux/linux-test.c
index 64f57cb287..4e0e862ad9 100644
--- a/tests/tcg/multiarch
"macros.inc" as "macros.h.inc".
Signed-off-by: Philippe Mathieu-Daudé
---
Reviewed-by: Brian Cain
target/hexagon/idef-parser/README.rst | 4 ++--
target/hexagon/idef-parser/{macros.inc => macros.h.inc} | 0
target/hexagon/gen_idef_parser_funcs.p
7;re named sha256 and sha512.
Rather than port the test to each OS's particular program names, we
should use the portable solution that's included w/Python.
Reported-by: Peter Maydell
Signed-off-by: Thomas Huth
---
Reviewed-by: Brian Cain
tests/functional/qem
On 9/12/2024 7:47 AM, Matheus Tavares Bernardino wrote:
This options has been removed at cb771ac1f5 (meson: Split
--enable-sanitizers to --enable-{asan, ubsan}, 2024-08-13), so let's
update its last standing mention in the docs.
Signed-off-by: Matheus Tavares Bernardino
---
docs/devel/testi
fixed grammar typo and s/use-after-frees/uses-after-free/
v1:
https://lore.kernel.org/qemu-devel/a788215960b94d863baeffb736f06e3fb94275e7.1726145226.git.quic_mathb...@quicinc.com/
Reviewed-by: Brian Cain
docs/devel/testing/fuzzing.rst | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
On 9/13/2024 9:30 PM, Brad Smith wrote:
On 2024-09-10 10:06 p.m., Brian Cain wrote:
On 9/10/2024 5:26 PM, Brad Smith wrote:
On 2024-09-10 4:17 p.m., Thomas Huth wrote:
Some systems (like OpenBSD) do not have the sha256sum or sha512sum
programs
installed by default. Use the Python hashlib
On 9/6/2024 9:39 PM, Brian Cain wrote:
With newer clang builds (19.x), there's a warning for implicit function
declarations and it rejects linux-test.c.
glibc/musl's readdir64() declaration in dirent is guarded by
_LARGEFILE64_SOURCE, so we'll define it to fix the warning
On 9/16/2024 8:12 AM, Alex Bennée wrote:
Brian Cain writes:
On 9/6/2024 9:39 PM, Brian Cain wrote:
With newer clang builds (19.x), there's a warning for implicit function
declarations and it rejects linux-test.c.
glibc/musl's readdir64() declaration in dirent is
On 9/16/2024 10:47 AM, Alex Bennée wrote:
Brian Cain writes:
On 9/16/2024 8:12 AM, Alex Bennée wrote:
Brian Cain writes:
On 9/6/2024 9:39 PM, Brian Cain wrote:
With newer clang builds (19.x), there's a warning for implicit function
declarations and it rejects linux-test.c.
On 9/16/2024 11:05 AM, Brian Cain wrote:
On 9/16/2024 10:47 AM, Alex Bennée wrote:
Brian Cain writes:
On 9/16/2024 8:12 AM, Alex Bennée wrote:
Brian Cain writes:
On 9/6/2024 9:39 PM, Brian Cain wrote:
With newer clang builds (19.x), there's a warning for implicit
fun
> -Original Message-
> From: Richard Henderson
...
> It might be clearer, and easier to initialize, if you invert the sense of the
> mask:
Ok -- thanks for the suggestions! I'll give 'em all a try.
-Brian
p now.
> > Some registers are defined to have immutable bits, this commit
> > will implement that behavior.
> >
> > Signed-off-by: Brian Cain
> > ---
> > target/hexagon/gen_masked.c | 44
> > target/hexagon/gen_masked.
> -Original Message-
> From: Qemu-devel
> On Behalf Of Matheus Tavares Bernardino
...
> On Wed, 24 Aug 2022 at 14:51, Matheus Tavares Bernardino
> wrote:
> >
> > Instead, let's change gdb_set_stop_cpu() to send stop messages only as a
> > response to a previous GDB command, also making su
> -Original Message-
> From: Qemu-devel
> On Behalf Of Peter Maydell
...
> On Tue, 7 Dec 2021 at 09:44, Damien Hedde
> wrote:
> >
> > According to the "Arm Generic Interrupt Controller Architecture
> > Specification GIC architecture version 3 and 4" (version G: page 345
> > for aarch64 or
> -Original Message-
> From: Peter Maydell
...
> On Tue, 7 Dec 2021 at 15:18, Brian Cain wrote:
> > Peter Maydell wrote:
> > > I won't try to put this into 6.2 unless you have a common guest
> > > that runs into this bug.
>
> > I kn
Brian Cain (1):
target/hexagon: fix some occurrences of -Wshadow=local
Matheus Tavares Bernardino (1):
target/hexagon: move GETPC() calls to top level helpers
target/hexagon/imported/alu.idef | 6 +--
target/hexagon/macros.h | 19 +
target/hexagon/mmvec/macros.h| 2
ino
Signed-off-by: Brian Cain
---
target/hexagon/imported/alu.idef | 6 +++---
target/hexagon/mmvec/macros.h| 2 +-
target/hexagon/op_helper.c | 9 +++--
target/hexagon/translate.c | 10 +-
4 files changed, 12 insertions(+), 15 deletions(-)
diff --git a/target/hexa
Simpson
Message-Id:
<2c74c3696946edba7cc5b2942cf296a5af532052.1689070412.git.quic_mathb...@quicinc.com>-ne
Reviewed-by: Brian Cain
Signed-off-by: Brian Cain
---
target/hexagon/macros.h| 19 +-
target/hexagon/op_helper.c | 75 +++---
target/hexagon/op_he
Simpson
Message-Id:
<2c74c3696946edba7cc5b2942cf296a5af532052.1689070412.git.quic_mathb...@quicinc.com>-ne
Reviewed-by: Brian Cain
---
target/hexagon/macros.h| 19 +-
target/hexagon/op_helper.c | 75 +++---
target/hexagon/op_helper.h | 9 -
3 files cha
Matheus' patch has previously been reviewed, but I based my -Wshadow
patch on his. So I'm submitting the series for review.
Brian Cain (1):
target/hexagon: fix some occurrences of -Wshadow=local
Matheus Tavares Bernardino (1):
target/hexagon: move GETPC() calls to top level helper
ino
Signed-off-by: Brian Cain
---
target/hexagon/imported/alu.idef | 6 +++---
target/hexagon/mmvec/macros.h| 2 +-
target/hexagon/op_helper.c | 9 +++--
target/hexagon/translate.c | 10 +-
4 files changed, 12 insertions(+), 15 deletions(-)
diff --git a/target/hexa
> -Original Message-
> From: Markus Armbruster
> Sent: Wednesday, October 4, 2023 2:38 AM
> To: Brian Cain
> Cc: qemu-devel@nongnu.org; richard.hender...@linaro.org;
> phi...@linaro.org; peter.mayd...@linaro.org; Matheus Bernardino (QUIC)
> ; stefa...@redhat.
Replicates scalar across bytes in vector", VdV.ub[i] = RtV)
>
>
> diff --git a/tests/tcg/hexagon/fpstuff.c b/tests/tcg/hexagon/fpstuff.c
> index 344b9f7772..6aadaccabd 100644
> --- a/tests/tcg/hexagon/fpstuff.c
> +++ b/tests/tcg/hexagon/fpstuff.c
> @@ -53,5 +53,5 @@ static void check_compare_exception(void)
> uint32_t usr;
>
> -/* Check that FP compares are quiet (don't raise any execptions) */
> +/* Check that FP compares are quiet (don't raise any exceptions) */
> asm (CLEAR_FPSTATUS
> "p0 = sfcmp.eq(%2, %3)\n\t"
> diff --git a/tests/tcg/hexagon/test_clobber.S
> b/tests/tcg/hexagon/test_clobber.S
> index a7aeb2b60c..10046c30d2 100644
> --- a/tests/tcg/hexagon/test_clobber.S
> +++ b/tests/tcg/hexagon/test_clobber.S
> @@ -1,4 +1,4 @@
> /*
> - * Purpose: demonstrate the succesful operation of the register save
> mechanism,
> + * Purpose: demonstrate the successful operation of the register save
> mechanism,
> * in which the caller saves the registers that will be clobbered, and
> restores
> * them after the call.
> --
> 2.39.2
>
Reviewed-by: Brian Cain
In v2: reworked with suggestions from Philippe and added a new patch
to cover -Wshadow=global.
Brian Cain (2):
target/hexagon: fix some occurrences of -Wshadow=local
target/hexagon: avoid shadowing globals
Matheus Tavares Bernardino (1):
target/hexagon: move GETPC() calls to top level
The typedef `vaddr` is shadowed by `vaddr` identifiers, so we rename the
identifiers to avoid shadowing the type name.
The global `cpu_env` is shadowed by local `cpu_env` arguments, so we
rename the function arguments to avoid shadowing the global.
Signed-off-by: Brian Cain
---
target/hexagon
Simpson
Message-Id:
<2c74c3696946edba7cc5b2942cf296a5af532052.1689070412.git.quic_mathb...@quicinc.com>-ne
Reviewed-by: Brian Cain
Signed-off-by: Brian Cain
---
target/hexagon/macros.h| 19 +-
target/hexagon/op_helper.c | 75 +++---
target/hexagon/op_he
ino
Signed-off-by: Brian Cain
---
target/hexagon/imported/alu.idef | 6 +++---
target/hexagon/mmvec/macros.h| 6 +++---
target/hexagon/op_helper.c | 9 +++--
target/hexagon/translate.c | 9 -
4 files changed, 13 insertions(+), 17 deletions(-)
diff --git a/target/hexa
> -Original Message-
> From: ltaylorsimp...@gmail.com
> Sent: Friday, October 6, 2023 11:01 AM
> To: Brian Cain ; qemu-devel@nongnu.org
> Cc: arm...@redhat.com; richard.hender...@linaro.org; phi...@linaro.org;
> peter.mayd...@linaro.org; Matheus Bernardino (QUIC)
>
Simpson
Message-Id:
<2c74c3696946edba7cc5b2942cf296a5af532052.1689070412.git.quic_mathb...@quicinc.com>-ne
Reviewed-by: Brian Cain
Signed-off-by: Brian Cain
---
target/hexagon/macros.h| 19 +-
target/hexagon/op_helper.c | 75 +++---
target/hexagon/op_he
Changes since v2:
- rebased, suggested by Markus
- s/cpu_env/tcg_env/
- For local shadows: s/tcg_env/tcg_env_/
Brian Cain (2):
target/hexagon: fix some occurrences of -Wshadow=local
target/hexagon: avoid shadowing globals
Matheus Tavares Bernardino (1):
target/hexagon
ino
Signed-off-by: Brian Cain
---
target/hexagon/imported/alu.idef | 6 +++---
target/hexagon/mmvec/macros.h| 2 +-
target/hexagon/op_helper.c | 9 +++--
target/hexagon/translate.c | 10 +-
4 files changed, 12 insertions(+), 15 deletions(-)
diff --git a/target/hexa
The typedef `vaddr` is shadowed by `vaddr` identifiers, so we rename the
identifiers to avoid shadowing the type name.
The global `tcg_env` is shadowed by local `tcg_env` arguments, so we
rename the function arguments to avoid shadowing the global.
Signed-off-by: Brian Cain
---
target/hexagon
> -Original Message-
> From: Philippe Mathieu-Daudé
> Sent: Monday, October 9, 2023 1:43 AM
> To: Brian Cain ; qemu-devel@nongnu.org
> Cc: arm...@redhat.com; richard.hender...@linaro.org;
> peter.mayd...@linaro.org; Matheus Bernardino (QUIC)
> ; stefa...@redhat.
> -Original Message-
> From: Anton Johansson
> Sent: Thursday, July 13, 2023 7:09 AM
> To: qemu-devel@nongnu.org
> Cc: Brian Cain ; peter.mayd...@linaro.org
> Subject: [PATCH] target/hexagon/idef-parser: Remove self-assignment
>
> WARNING: This email or
> -Original Message-
> From: Matheus Tavares Bernardino
> Sent: Monday, July 3, 2023 4:50 PM
> To: qemu-devel@nongnu.org
> Cc: Brian Cain ; Marco Liebel (QUIC)
> ; ltaylorsimp...@gmail.com
> Subject: [PATCH] Hexagon: move GETPC() calls to top level helpers
>
> -Original Message-
> From: Alex Bennée
> Sent: Wednesday, May 31, 2023 6:24 AM
> To: Daniel P.Berrangé
> Cc: qemu-devel ; Michael Tokarev
> ; Erik Skultety ; Brian Cain
> ; Palmer Dabbelt ; Alistair Francis
> ; Bin Meng
> Subject: How do you represent a
> -Original Message-
> From: qemu-devel-bounces+bcain=quicinc@nongnu.org bounces+bcain=quicinc@nongnu.org> On Behalf Of Peter Maydell
> Sent: Tuesday, November 21, 2023 8:33 AM
> To: Taylor Simpson
> Cc: qemu-devel@nongnu.org; richard.hender...@linaro.org; f4...@amsat.org
> Subj
> -Original Message-
> From: Brian Cain
> Sent: Tuesday, November 21, 2023 9:52 AM
> To: Peter Maydell
> Cc: qemu-devel@nongnu.org; richard.hender...@linaro.org; f4...@amsat.org
> Subject: RE: [PULL v2 25/30] Hexagon HVX (target/hexagon) instruction
> decoding
>
> -Original Message-
> From: Taylor Simpson
> Sent: Thursday, November 30, 2023 12:40 PM
> To: qemu-devel@nongnu.org
> Cc: Brian Cain ; Matheus Bernardino (QUIC)
> ; Sid Manning ; Marco
> Liebel (QUIC) ; richard.hender...@linaro.org;
> phi...@linaro.org;
> -Original Message-
> From: Philippe Mathieu-Daudé
> Sent: Thursday, November 30, 2023 2:17 PM
> To: Taylor Simpson ; qemu-devel@nongnu.org
> Cc: Brian Cain ; Matheus Bernardino (QUIC)
> ; Sid Manning ; Marco
> Liebel (QUIC) ; richard.hender...@linaro.org;
>
> -Original Message-
> From: Taylor Simpson
> Sent: Monday, December 4, 2023 7:53 PM
> To: qemu-devel@nongnu.org
> Cc: Brian Cain ; Matheus Bernardino (QUIC)
> ; Sid Manning ; Marco
> Liebel (QUIC) ; richard.hender...@linaro.org;
> phi...@linaro.org;
> -Original Message-
> From: Taylor Simpson
> Sent: Monday, December 4, 2023 7:53 PM
> To: qemu-devel@nongnu.org
> Cc: Brian Cain ; Matheus Bernardino (QUIC)
> ; Sid Manning ; Marco
> Liebel (QUIC) ; richard.hender...@linaro.org;
> phi...@linaro.org;
> -Original Message-
> From: Taylor Simpson
> Sent: Monday, December 4, 2023 7:53 PM
> To: qemu-devel@nongnu.org
> Cc: Brian Cain ; Matheus Bernardino (QUIC)
> ; Sid Manning ; Marco
> Liebel (QUIC) ; richard.hender...@linaro.org;
> phi...@linaro.org;
> -Original Message-
> From: Taylor Simpson
> Sent: Monday, December 4, 2023 7:53 PM
> To: qemu-devel@nongnu.org
> Cc: Brian Cain ; Matheus Bernardino (QUIC)
> ; Sid Manning ; Marco
> Liebel (QUIC) ; richard.hender...@linaro.org;
> phi...@linaro.org;
Alex,
A very long time ago QEMU supported disabling the translation cache via
"-translation no-cache". That option was deliberately removed. We are looking
into a hexagon-specific failure when there's a TB lookup miss from a
cpu_loop_exit_restore().I'd like to test our fix for this failur
> -Original Message-
> From: Taylor Simpson
> Sent: Sunday, December 10, 2023 4:07 PM
> To: qemu-devel@nongnu.org
> Cc: Brian Cain ; Matheus Bernardino (QUIC)
> ; Sid Manning ; Marco
> Liebel (QUIC) ; richard.hender...@linaro.org;
> phi...@linaro.org;
> -Original Message-
> From: Taylor Simpson
> Sent: Sunday, December 10, 2023 4:07 PM
> To: qemu-devel@nongnu.org
> Cc: Brian Cain ; Matheus Bernardino (QUIC)
> ; Sid Manning ; Marco
> Liebel (QUIC) ; richard.hender...@linaro.org;
> phi...@linaro.org;
> -Original Message-
> From: Taylor Simpson
> Sent: Sunday, December 10, 2023 4:07 PM
> To: qemu-devel@nongnu.org
> Cc: Brian Cain ; Matheus Bernardino (QUIC)
> ; Sid Manning ; Marco
> Liebel (QUIC) ; richard.hender...@linaro.org;
> phi...@linaro.org;
> -Original Message-
> From: Taylor Simpson
> Sent: Sunday, December 10, 2023 4:07 PM
> To: qemu-devel@nongnu.org
> Cc: Brian Cain ; Matheus Bernardino (QUIC)
> ; Sid Manning ; Marco
> Liebel (QUIC) ; richard.hender...@linaro.org;
> phi...@linaro.org;
> -Original Message-
> From: Taylor Simpson
> Sent: Sunday, December 10, 2023 4:07 PM
> To: qemu-devel@nongnu.org
> Cc: Brian Cain ; Matheus Bernardino (QUIC)
> ; Sid Manning ; Marco
> Liebel (QUIC) ; richard.hender...@linaro.org;
> phi...@linaro.org;
> -Original Message-
> From: Taylor Simpson
> Sent: Sunday, December 10, 2023 4:07 PM
> To: qemu-devel@nongnu.org
> Cc: Brian Cain ; Matheus Bernardino (QUIC)
> ; Sid Manning ; Marco
> Liebel (QUIC) ; richard.hender...@linaro.org;
> phi...@linaro.org;
> -Original Message-
> From: Taylor Simpson
> Sent: Sunday, December 10, 2023 4:07 PM
> To: qemu-devel@nongnu.org
> Cc: Brian Cain ; Matheus Bernardino (QUIC)
> ; Sid Manning ; Marco
> Liebel (QUIC) ; richard.hender...@linaro.org;
> phi...@linaro.org;
> -Original Message-
> From: Taylor Simpson
> Sent: Sunday, December 10, 2023 4:07 PM
> To: qemu-devel@nongnu.org
> Cc: Brian Cain ; Matheus Bernardino (QUIC)
> ; Sid Manning ; Marco
> Liebel (QUIC) ; richard.hender...@linaro.org;
> phi...@linaro.org;
This update includes support for privileged instructions.
Signed-off-by: Brian Cain
---
tests/docker/dockerfiles/debian-hexagon-cross.docker | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/tests/docker/dockerfiles/debian-hexagon-cross.docker
b/tests/docker/dockerfiles
This is intended to address a coverity finding: CID 1527408.
Signed-off-by: Brian Cain
---
target/hexagon/mmvec/decode_ext_mmvec.c | 4 +---
1 file changed, 1 insertion(+), 3 deletions(-)
diff --git a/target/hexagon/mmvec/decode_ext_mmvec.c
b/target/hexagon/mmvec/decode_ext_mmvec.c
index
> -Original Message-
> From: Taylor Simpson
> Sent: Monday, January 8, 2024 4:49 PM
> To: qemu-devel@nongnu.org
> Cc: Brian Cain ; Matheus Bernardino (QUIC)
> ; Sid Manning ; Marco
> Liebel (QUIC) ; richard.hender...@linaro.org;
> phi...@linaro.org; a...@rev.ng;
> -Original Message-
> From: Taylor Simpson
> Sent: Monday, January 8, 2024 4:49 PM
> To: qemu-devel@nongnu.org
> Cc: Brian Cain ; Matheus Bernardino (QUIC)
> ; Sid Manning ; Marco
> Liebel (QUIC) ; richard.hender...@linaro.org;
> phi...@linaro.org; a...@rev.ng;
> -Original Message-
> From: Taylor Simpson
> Sent: Monday, January 8, 2024 4:49 PM
> To: qemu-devel@nongnu.org
> Cc: Brian Cain ; Matheus Bernardino (QUIC)
> ; Sid Manning ; Marco
> Liebel (QUIC) ; richard.hender...@linaro.org;
> phi...@linaro.org; a...@rev.ng;
> -Original Message-
> From: Philippe Mathieu-Daudé
> Sent: Tuesday, October 10, 2023 12:23 AM
> To: Brian Cain ; richard.hender...@linaro.org;
> a...@rev.ng
> Cc: arm...@redhat.com; peter.mayd...@linaro.org; Matheus Bernardino
> (QUIC) ; stefa...@redhat.com; a...@r
ino
Signed-off-by: Brian Cain
Reviewed-by: Philippe Mathieu-Daudé
Message-Id: <20231008220945.983643-3-bc...@quicinc.com>
---
target/hexagon/imported/alu.idef | 6 +++---
target/hexagon/mmvec/macros.h| 2 +-
target/hexagon/op_helper.c | 9 +++--
target/hexagon/translate.c
wing fixes
--------
Brian Cain (1):
target/hexagon: fix some occurrences of -Wshadow=local
Matheus Tavares Bernardino (1):
target/hexagon: move GETPC() calls to top level helpers
target/hexagon/imported/alu.idef | 6 +--
target/hexagon/macros.h | 19 +
targ
Simpson
Message-Id:
<2c74c3696946edba7cc5b2942cf296a5af532052.1689070412.git.quic_mathb...@quicinc.com>-ne
Reviewed-by: Brian Cain
Signed-off-by: Brian Cain
Message-Id: <20231008220945.983643-2-bc...@quicinc.com>
---
target/hexagon/macros.h| 19 +-
Alexander, Bandan, Paolo, Stefan, Manuel,
Hi, I'm Brian and I maintain the Hexagon arch for QEMU. Elia, a security
researcher at Qualcomm is exploring ways to fuzz some hexagon OS kernel with
QEMU and in particular leveraging snapshotting, inspired by your research and
more. I'm not an expert
> -Original Message-
> From: Taylor Simpson
> Sent: Thursday, November 9, 2023 3:26 PM
> To: qemu-devel@nongnu.org
> Cc: Brian Cain ; Matheus Bernardino (QUIC)
> ; Sid Manning ;
> richard.hender...@linaro.org; phi...@linaro.org; a...@rev.ng; a...@rev.ng;
>
> -Original Message-
> From: qemu-devel-bounces+bcain=quicinc@nongnu.org AFAICT the keys for registers and new_registers can be derived from the values
> themselves. Rather than worry about copy/paste errors causing these not to
> correspond, you can create a dictionary from an iterab
> -Original Message-
> From: ltaylorsimp...@gmail.com
> Sent: Wednesday, November 15, 2023 4:03 PM
> To: Brian Cain ; qemu-devel@nongnu.org
> Cc: Matheus Bernardino (QUIC) ; Sid Manning
> ; richard.hender...@linaro.org; phi...@linaro.org;
> a...@rev.ng; a...@rev.n
> -Original Message-
> From: ltaylorsimp...@gmail.com
> Sent: Thursday, November 16, 2023 1:19 PM
> To: Brian Cain ; qemu-devel@nongnu.org
> Cc: Matheus Bernardino (QUIC) ; Sid Manning
> ; richard.hender...@linaro.org; phi...@linaro.org;
> a...@rev.ng; a...@rev.n
-
> ri...@nongnu.org; Palmer Dabbelt ; Yoshinori Sato
> ; Bastian Koppelmann paderborn.de>; Bin Meng ; Daniel Henrique
> Barboza ; Mark Cave-Ayland ayl...@ilande.co.uk>; Weiwei Li ; Daniel Henrique
> Barboza ; Nicholas Piggin
> ; qemu-...@nongnu.org; Liu Zhiwei
> ; Marek Vasut
> -Original Message-
> From: Stefan Hajnoczi
> Sent: Thursday, October 26, 2023 7:52 PM
> To: Markus Armbruster
> Cc: qemu-devel@nongnu.org; pbonz...@redhat.com;
> marcandre.lur...@redhat.com; berra...@redhat.com; th...@redhat.com;
> phi...@linaro.org; Brian C
> -Original Message-
> From: Alex Bennée
...
> Which leads to the compiler complaining:
>
> hexagon-unknown-linux-musl-clang -Wno-incompatible-pointer-types -
> Wno-undefined-internal -fno-unroll-loops -Wall -Werror -O0 -g -fno-strict-
> aliasing -mv67 -O2 -static /home
> /alex.benne
> -Original Message-
> From: Brian Cain
...
> > I suspect the easiest thing to do is to drop the patches again so I
> > don't hold up the rest of testing/next. I can include the initial
> > docker image patch but I won't enable it in configure.sh/gitlab.
On 7/4/2024 3:47 AM, Zhao Liu wrote:
Fix the superfluous trailing semicolon in target/hexagon/imported/mmvec/
ext.idef.
Cc: Brian Cain
Signed-off-by: Zhao Liu
Reviewed-by: Brian Cain
---
target/hexagon/imported/mmvec/ext.idef | 2 +-
1 file changed, 1 insertion(+), 1 deletion
On 7/15/2024 4:59 AM, Michael Tokarev wrote:
06.07.2024 00:50, Brian Cain wrote:
On 7/4/2024 3:47 AM, Zhao Liu wrote:
Fix the superfluous trailing semicolon in
target/hexagon/imported/mmvec/
ext.idef.
Cc: Brian Cain
Signed-off-by: Zhao Liu
Reviewed-by: Brian Cain
Brian, is it okay
vares Bernardino
---
Reviewed-by: Brian Cain
target/hexagon/op_helper.c | 16
tests/tcg/hexagon/usr.c| 10 ++
2 files changed, 18 insertions(+), 8 deletions(-)
diff --git a/target/hexagon/op_helper.c b/target/hexagon/op_helper.c
index ae5a605513..e1fc88aa0d 1
vares Bernardino
Reviewed-by: Brian Cain
Reviewed-by: Taylor Simpson
---
v2: updated the copyright year
Queued. thanks!
target/hexagon/op_helper.c | 18 +-
tests/tcg/hexagon/usr.c| 12 +++-
2 files changed, 20 insertions(+), 10 deletions(-)
diff --git a/t
On 6/12/2024 11:42 AM, Taylor Simpson wrote:
hexagon-core.xml only exposes register p3_0 which is an alias that
aggregates the predicate registers. It is more convenient for users
to interact directly with the predicate registers.
Tested with lldb downloaded from this location
https://github.
For now, v66 behavior is the same as other CPUs.
Signed-off-by: Brian Cain
---
target/hexagon/cpu-qom.h | 1 +
target/hexagon/cpu.c | 2 ++
2 files changed, 3 insertions(+)
diff --git a/target/hexagon/cpu-qom.h b/target/hexagon/cpu-qom.h
index da92fe7468..0b149bd5fe 100644
--- a/target
Define a hexagon_cpu_properties list to match the idiom used
by other targets.
Signed-off-by: Brian Cain
---
target/hexagon/cpu.c | 18 --
1 file changed, 8 insertions(+), 10 deletions(-)
diff --git a/target/hexagon/cpu.c b/target/hexagon/cpu.c
index 64cc05cca7..93579fbb15
On 7/31/2024 12:07 PM, Peter Maydell wrote:
On Thu, 13 Jul 2023 at 17:21, Brian Cain wrote:
-Original Message-
From: Anton Johansson
Sent: Thursday, July 13, 2023 7:09 AM
To: qemu-devel@nongnu.org
Cc: Brian Cain ; peter.mayd...@linaro.org
Subject: [PATCH] target/hexagon/idef
Add my git tree for hexagon. Note that the branch is "hex-next" and not
"hex.next" as had been used previously. But I'll keep the "hex.next" branch
in sync with "hex-next" until this commit lands to avoid confusion.
Signed-off-by: Brian Cain
---
M
rom 68547357c895934796e9b4687338bb9e39ac86c5 Mon Sep 17 00:00:00 2001
From: Brian Cain mailto:bc...@quicinc.com
Date: Thu, 1 Apr 2021 10:32:24 -0500
Subject: [PATCH] Update llvm-project commit
clang was updated with new inline asm registers for hexagon, this is
necessary for QEMU test cases currently under rev
https://gitlab.com/qemu-project/ asks for sign in and if I do sign in, I get a
404. Is this expected?
https://status.gitlab.com/ describes "shared runner degradation" but that
doesn't sound like this problem.
-Brian
For some hexagon use cases, we would prefer to have finer grained scheduling
among multiple guest cores/threads. We haven't been able to determine exactly
what kind of scheduling algorithm is operating in the baseline case. If the
current hw thread is ready-to-run and is spinning over a tight
> -Original Message-
> From: Brian Cain
> Sent: Wednesday, April 28, 2021 10:06 PM
> To: qemu-devel@nongnu.org
> Cc: Richard Henderson ; Taylor Simpson
> ; Michael Lambert ;
> Manning, Sid
> Subject: sysemu SMP scheduling
>
> For some hexagon use cases,
> -Original Message-
> From: Philippe Mathieu-Daudé On
> Behalf Of Philippe Mathieu-Daudé
> Sent: Saturday, February 27, 2021 8:10 AM
> To: Taylor Simpson ; qemu-devel@nongnu.org
> Cc: richard.hender...@linaro.org; alex.ben...@linaro.org;
> laur...@vivier.eu; a...@rev
Reviewed-by: Brian Cain
> -Original Message-
> From: Philippe Mathieu-Daudé On
> Behalf Of Philippe Mathieu-Daudé
> Sent: Sunday, February 28, 2021 4:23 PM
> To: qemu-devel@nongnu.org
> Cc: Fam Zheng ; Taylor Simpson
> ; Philippe Mathieu-Daudé ;
> Alex Bennée
> -Original Message-
> From: Taylor Simpson
> Sent: Monday, January 25, 2021 5:09 PM
> To: Philippe Mathieu-Daudé ; qemu-devel@nongnu.org
> Cc: richard.hender...@linaro.org; alex.ben...@linaro.org;
> laur...@vivier.eu; a...@rev.ng; Brian Cain
> Subject: RE: [PATCH v7
> -Original Message-
> From: Alex Bennée
> Sent: Tuesday, February 16, 2021 5:18 AM
> To: Philippe Mathieu-Daudé
> Cc: Brian Cain ; qemu-devel@nongnu.org; Michael
> Lambert ; Sid Manning ;
> Laurent Vivier
> Subject: [EXT] Re: hexagon sysemu - library loading pat
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