Hi Richard,
+# Field examples:
+#
+# %disp 0:s16 -- sextract(i, 0, 16)
+# %imm9 16:6 10:3 -- extract(i, 16, 6) << 3 | extract(i, 10, 3)
startindex:endindex for unnamed_field is more intuitive. As any ISA
manual would specify those.
+#
+# It is recommended, but not required,
nstead of cpu_model.
>
> Signed-off-by: Igor Mammedov
> ---
> CC: Bastian Koppelmann
> ---
> target/tricore/cpu.h | 1 +
> 1 file changed, 1 insertion(+)
Reviewed-by: Bastian Koppelmann
Cheers,
Bastian
Hi Berg,
thanks for the tip, a fix has also been commited already :)
Cheers,
Bastian
** Changed in: qemu
Status: New => Fix Committed
--
You received this bug notification because you are a member of qemu-
devel-ml, which is subscribed to QEMU.
https://bugs.launchpad.net/bugs/1794939
T
Signed-off-by: Bastian Koppelmann
---
target/riscv/translate.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 18d7b6d147..5359088e24 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -1237,13
Hi,
while going through the reviews of the riscv-decodetree patches, two bugs came
up that I fix here. There is one more problem [1] mentioned by Richard but
I don't have the time to investigate it further.
[1] https://patchwork.kernel.org/patch/10650293/
Bastian Koppelmann (2):
target/
sfence.vm has been replaced in priv v1.10 spec by sfence.vma.
Reported-by: Richard Henderson
Signed-off-by: Bastian Koppelmann
---
target/riscv/translate.c | 18 +-
1 file changed, 13 insertions(+), 5 deletions(-)
diff --git a/target/riscv/translate.c b/target/riscv
On 11/8/18 4:53 PM, Richard Henderson wrote:
On 11/8/18 1:06 PM, Bastian Koppelmann wrote:
while going through the reviews of the riscv-decodetree patches, two bugs came
up that I fix here. There is one more problem [1] mentioned by Richard but
I don't have the time to investigate it fu
Signed-off-by: Bastian Koppelmann
Signed-off-by: Peer Adelt
---
target/riscv/insn32.decode | 15 ++
target/riscv/insn_trans/trans_rvi.inc.c | 71 +
target/riscv/translate.c| 7 ---
3 files changed, 86 insertions(+), 7 deletions(-)
diff
Signed-off-by: Bastian Koppelmann
Signed-off-by: Peer Adelt
---
target/riscv/insn32.decode | 8 +++
target/riscv/insn_trans/trans_rvi.inc.c | 79 +
target/riscv/translate.c| 43 +-
3 files changed, 88 insertions(+), 42 deletions
Signed-off-by: Bastian Koppelmann
Signed-off-by: Peer Adelt
---
target/riscv/insn32.decode | 17 +++
target/riscv/insn_trans/trans_rva.inc.c | 175
target/riscv/translate.c| 1 +
3 files changed, 193 insertions(+)
create mode 100644
l tree can be found here:
https://github.com/bkoppelmann/qemu/tree/riscv-dt
Cheers,
Bastian
Bastian Koppelmann (28):
targer/riscv: Activate decodetree and implemnt LUI & AUIPC
target/riscv: Convert RVXI branch insns to decodetree
target/riscv: Convert RVXI load/store insns to decodetree
Signed-off-by: Bastian Koppelmann
Signed-off-by: Peer Adelt
---
target/riscv/insn32.decode | 8
target/riscv/insn_trans/trans_rvi.inc.c | 20
target/riscv/translate.c| 14 --
3 files changed, 28 insertions(+), 14 deletions
trans_jalr() is the only caller, so move the code into
trans_jalr().
Signed-off-by: Bastian Koppelmann
Signed-off-by: Peer Adelt
---
target/riscv/insn_trans/trans_rvi.inc.c | 27 +-
target/riscv/translate.c| 38 -
2 files changed, 26
we cannot remove the call to gen_arith() in decode_RV32_64G() since it
is used to translate multiply instructions.
Signed-off-by: Bastian Koppelmann
Signed-off-by: Peer Adelt
---
target/riscv/insn32.decode | 36
target/riscv/insn_trans/trans_rvi.inc.c | 221
Signed-off-by: Bastian Koppelmann
Signed-off-by: Peer Adelt
---
target/riscv/insn32.decode | 19 +
target/riscv/insn_trans/trans_rvi.inc.c | 52 +
target/riscv/translate.c| 19 +
3 files changed, 72 insertions(+), 18 deletions
Signed-off-by: Bastian Koppelmann
Signed-off-by: Peer Adelt
---
target/riscv/insn32.decode| 13 ++
.../riscv/insn_trans/trans_privileged.inc.c | 111 ++
target/riscv/translate.c | 49 +---
3 files changed, 125 insertions(+), 48
The latter utilizes argument-sets of decodetree such that no manual
decoding is necessary as in gen_branch().
Signed-off-by: Bastian Koppelmann
Signed-off-by: Peer Adelt
---
target/riscv/insn_trans/trans_rvi.inc.c | 56 +
target/riscv/translate.c| 47
for now only LUI & AUIPC are decoded and translated. If decodetree fails, we
falls back to the old decoder.
Signed-off-by: Bastian Koppelmann
Signed-off-by: Peer Adelt
---
target/riscv/Makefile.objs | 10 +++
target/riscv/insn32.decode
Signed-off-by: Bastian Koppelmann
Signed-off-by: Peer Adelt
---
target/riscv/insn32.decode | 17 +
target/riscv/insn_trans/trans_rvm.inc.c | 87 +
target/riscv/translate.c| 10 +--
3 files changed, 105 insertions(+), 9 deletions
Signed-off-by: Bastian Koppelmann
Signed-off-by: Peer Adelt
---
target/riscv/insn32.decode | 8 +
target/riscv/insn_trans/trans_rvd.inc.c | 94 +
target/riscv/translate.c| 484 +---
3 files changed, 103 insertions(+), 483 deletions
Signed-off-by: Bastian Koppelmann
Signed-off-by: Peer Adelt
---
target/riscv/insn_trans/trans_rvi.inc.c | 79 +
target/riscv/translate.c| 59 ++
2 files changed, 86 insertions(+), 52 deletions(-)
diff --git a/target/riscv/insn_trans
Signed-off-by: Bastian Koppelmann
Signed-off-by: Peer Adelt
---
target/riscv/insn32.decode | 6 +++
target/riscv/insn_trans/trans_rvf.inc.c | 70 +
2 files changed, 76 insertions(+)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index
Signed-off-by: Bastian Koppelmann
Signed-off-by: Peer Adelt
---
target/riscv/insn32.decode | 28 +++
target/riscv/insn_trans/trans_rvd.inc.c | 313
target/riscv/translate.c| 1 +
3 files changed, 342 insertions(+)
create mode 100644
Signed-off-by: Bastian Koppelmann
Signed-off-by: Peer Adelt
---
target/riscv/insn32.decode | 35 +++
target/riscv/insn_trans/trans_rvf.inc.c | 326
target/riscv/translate.c| 1 +
3 files changed, 362 insertions(+)
create mode 100644
This also removes all functions that now became obsolete.
Signed-off-by: Bastian Koppelmann
Signed-off-by: Peer Adelt
---
target/riscv/insn16.decode | 34 +-
target/riscv/insn_trans/trans_rvc.inc.c | 107 +
target/riscv/translate.c| 151
With decodetree we don't need to convert RISC-V opcodes into to MemOps
as gen_load() did.
Signed-off-by: Bastian Koppelmann
Signed-off-by: Peer Adelt
---
target/riscv/insn_trans/trans_rvi.inc.c | 44 +
target/riscv/translate.c| 20 ---
2
Signed-off-by: Bastian Koppelmann
Signed-off-by: Peer Adelt
---
target/riscv/insn32.decode | 13 +++
target/riscv/insn_trans/trans_rva.inc.c | 99 +
target/riscv/translate.c| 140
3 files changed, 112 insertions(+), 140
gen_arith_imm() does a lot of decoding manually, which was hard to read in
case of the shift instructions and is not necessary anymore with decodetree.
Signed-off-by: Bastian Koppelmann
Signed-off-by: Peer Adelt
---
target/riscv/insn32.decode | 3 +-
target/riscv/insn_trans
Signed-off-by: Bastian Koppelmann
Signed-off-by: Peer Adelt
---
target/riscv/Makefile.objs | 9 ++-
target/riscv/insn16.decode | 55 +++
target/riscv/insn_trans/trans_rvc.inc.c | 89 +
target/riscv/translate.c| 88
with all 16 bit insns moved to decodetree no path is falling back to
gen_system(), so we can remove it.
Signed-off-by: Bastian Koppelmann
Signed-off-by: Peer Adelt
---
target/riscv/translate.c | 32
1 file changed, 32 deletions(-)
diff --git a/target/riscv
With decodetree we don't need to convert RISC-V opcodes into to MemOps
as gen_store() did.
Signed-off-by: Bastian Koppelmann
Signed-off-by: Peer Adelt
---
target/riscv/insn_trans/trans_rvi.inc.c | 31 --
target/riscv/translate.c
decodetree handles all instructions now so the fallback is not necessary
anymore.
Signed-off-by: Bastian Koppelmann
Signed-off-by: Peer Adelt
---
target/riscv/translate.c | 23 ---
1 file changed, 23 deletions(-)
diff --git a/target/riscv/translate.c b/target/riscv
manual decoding in gen_arith() is not necessary with decodetree.
Signed-off-by: Bastian Koppelmann
Signed-off-by: Peer Adelt
---
target/riscv/insn32.decode | 3 ++-
target/riscv/insn_trans/trans_rvi.inc.c | 21 ++--
target/riscv/translate.c| 33
Signed-off-by: Bastian Koppelmann
Signed-off-by: Peer Adelt
---
target/riscv/insn_trans/trans_rvm.inc.c | 55 ++---
target/riscv/translate.c| 266 +++-
2 files changed, 151 insertions(+), 170 deletions(-)
diff --git a/target/riscv/insn_trans/trans_rvm.inc.c
return false in trans_* instructions is no longer used as a fallback to
the old decoder. We can therefore now use 'return false' to indicate an illegal
instruction.
Signed-off-by: Bastian Koppelmann
Signed-off-by: Peer Adelt
---
.../riscv/insn_trans/trans_privileged.inc.c | 6 ++--
Hi Richard,
On 10/12/18 8:46 PM, Richard Henderson wrote:
On 10/12/18 10:30 AM, Bastian Koppelmann wrote:
+static bool trans_andi(DisasContext *ctx, arg_andi *a, uint32_t insn)
+{
+gen_arith_imm(ctx, OPC_RISC_ANDI, a->rd, a->rs1, a->imm);
+return true;
+}
+static bool t
On 10/13/18 8:18 PM, Richard Henderson wrote:
On 10/12/18 10:30 AM, Bastian Koppelmann wrote:
+# Argument sets:
+&cl rs1 rd
+&cl_dw uimm rs1 rd
+&ciw nzuimm rd
+&cs rs1 rs2
+&cs_dw uimm rs1 rs2
I guess this is good enou
On 10/13/18 8:53 PM, Richard Henderson wrote:
Choose return false or raise exception. Except...
I wonder if we might write this as
int shamt = a->shamt;
if (shamt == 0) {
shamt = 64;
}
Good catch. I'll add a comment, that a shamt of 0 is intended for RV128.
Cheers,
On 10/13/18 9:34 PM, Richard Henderson wrote:
On 10/12/18 10:30 AM, Bastian Koppelmann wrote:
+@c_flwsp_ldsp ... . . . .. &c_flwsp_ldsp uimm_flwsp=%uimm_6bit_lw \
+uimm_ldsp=%uimm_6bit_ld %rd
+@c_fswsp_sdsp ... . . . .. &c_fswsp_sdsp uimm_fswsp=%uimm
On 10/13/18 8:53 PM, Richard Henderson wrote:
On 10/12/18 10:30 AM, Bastian Koppelmann wrote:
+static bool trans_c_addi(DisasContext *ctx, arg_c_addi *a, uint16_t insn)
+{
+if (a->imm == 0) {
+return true;
+}
return false, I think.
Those are HINTS, which means
Reviewed-by: Richard Henderson
Signed-off-by: Bastian Koppelmann
Signed-off-by: Peer Adelt
---
v1 -> v2:
- use simplfied gen_amo() with function pointers
target/riscv/insn32.decode | 13 +++
target/riscv/insn_trans/trans_rva.inc.c | 99 +
target/ri
Signed-off-by: Bastian Koppelmann
Signed-off-by: Peer Adelt
---
v1 -> v2:
- use ctx->env instead of current_cpu->env_ptr
target/riscv/insn32.decode | 19 ++
target/riscv/insn_trans/trans_rvi.inc.c | 49 +
target/riscv/tr
for now only LUI & AUIPC are decoded and translated. If decodetree fails, we
fall back to the old decoder.
Reviewed-by: Richard Henderson
Signed-off-by: Bastian Koppelmann
Signed-off-by: Peer Adelt
---
v1 -> v2:
- ex_shift_amount returns uint32_t
target/riscv/Makefi
Reviewed-by: Richard Henderson
Signed-off-by: Bastian Koppelmann
Signed-off-by: Peer Adelt
---
v1 -> v2:
- RISCV32 now returns false instead of raising an exception
target/riscv/insn32.decode | 6 +++
target/riscv/insn_trans/trans_rvf.inc.c | 68 +
- trans_shift -> gen_shift
- Add missing TARGET_RISCV64 conditions
- trans_arith_w -> gen_arith_w
- Add missing gen_exception_illegal
- dropped 0028
Bastian Koppelmann (29):
target/riscv: Move CPURISCVState pointer to DisasContext
targer/riscv: Activate dec
Reviewed-by: Richard Henderson
Signed-off-by: Bastian Koppelmann
Signed-off-by: Peer Adelt
---
v1 -> v2:
- fixed spacing
target/riscv/insn32.decode | 17 +
target/riscv/insn_trans/trans_rvm.inc.c | 98 +
target/riscv/translate.c|
Reviewed-by: Richard Henderson
Signed-off-by: Bastian Koppelmann
Signed-off-by: Peer Adelt
---
target/riscv/insn32.decode| 15 +++
.../riscv/insn_trans/trans_privileged.inc.c | 111 ++
target/riscv/translate.c | 49 +---
3 files
Reviewed-by: Richard Henderson
Signed-off-by: Bastian Koppelmann
Signed-off-by: Peer Adelt
---
v1 -> v2:
- fixed spacing
target/riscv/insn32.decode | 15 +
target/riscv/insn_trans/trans_rvi.inc.c | 78 +
target/riscv/translate.c|
CPURISCVState is rarely used, so there is no need to pass it to every
translate function. This paves the way for decodetree which only passes
DisasContext to translate functions.
Signed-off-by: Bastian Koppelmann
---
target/riscv/translate.c | 15 ---
1 file changed, 8 insertions
Signed-off-by: Bastian Koppelmann
Signed-off-by: Peer Adelt
---
v1 -> v2:
- simplified gen_amo() with function pointers
- rs2 @atom_ld is now decimal
target/riscv/insn32.decode | 17 +++
target/riscv/insn_trans/trans_rva.inc.c | 145
target/ri
Reviewed-by: Richard Henderson
Signed-off-by: Bastian Koppelmann
Signed-off-by: Peer Adelt
---
target/riscv/insn32.decode | 9 +++
target/riscv/insn_trans/trans_rvi.inc.c | 79 +
target/riscv/translate.c| 43 +-
3 files changed
Signed-off-by: Bastian Koppelmann
Signed-off-by: Peer Adelt
---
v1 -> v2:
- Add REQUIRE_FPU to arithm helpers
target/riscv/insn32.decode | 28 +++
target/riscv/insn_trans/trans_rvd.inc.c | 319
target/riscv/translate.c| 1 +
3 fi
we cannot remove the call to gen_arith() in decode_RV32_64G() since it
is used to translate multiply instructions.
Signed-off-by: Bastian Koppelmann
Signed-off-by: Peer Adelt
---
v1 -> v2:
- RISCV32 now returns false instead of raising an exception
- shift translators now also
Signed-off-by: Bastian Koppelmann
Signed-off-by: Peer Adelt
---
v1 -> v2:
- simplified fence/fence_i as suggested by Richard
target/riscv/insn32.decode | 6 ++
target/riscv/insn_trans/trans_rvi.inc.c | 20
target/riscv/translate.c|
decodetree handles all instructions now so the fallback is not necessary
anymore.
Signed-off-by: Bastian Koppelmann
Signed-off-by: Peer Adelt
---
v1 -> v2:
- Add missing gen_exception_illegal
target/riscv/translate.c | 24 +---
1 file changed, 1 insertion(+),
We now utilizes argument-sets of decodetree such that no manual
decoding is necessary.
Reviewed-by: Richard Henderson
Signed-off-by: Bastian Koppelmann
Signed-off-by: Peer Adelt
---
v1 -> v2:
- trans_branch -> gen_branch
target/riscv/insn_trans/trans_rvi.inc.
Reviewed-by: Richard Henderson
Signed-off-by: Bastian Koppelmann
Signed-off-by: Peer Adelt
---
target/riscv/insn32.decode | 8 +
target/riscv/insn_trans/trans_rvd.inc.c | 94 +
target/riscv/translate.c| 484 +---
3 files changed, 103
Reviewed-by: Richard Henderson
Signed-off-by: Bastian Koppelmann
Signed-off-by: Peer Adelt
---
v1 -> v2:
- REQUIRE_FPU uses do {} while (0)
- Add REQUIRE_FPU to arithm helpers
target/riscv/insn32.decode | 35 +++
target/riscv/insn_trans/trans_rvf.inc.c |
Signed-off-by: Bastian Koppelmann
Signed-off-by: Peer Adelt
---
v1 -> v2:
- Add missing TARGET_RISCV64 conditions
- trans_arith_w -> gen_arith_w
target/riscv/insn_trans/trans_rvm.inc.c | 75 ---
target/riscv/translate.c| 268 +++-
2
With decodetree we don't need to convert RISC-V opcodes into to MemOps
as the old gen_load() did.
Reviewed-by: Richard Henderson
Signed-off-by: Bastian Koppelmann
Signed-off-by: Peer Adelt
---
v1 -> v2:
- trans_load -> gen_load
- removed negative memop check
target/riscv
With decodetree we don't need to convert RISC-V opcodes into to MemOps
as the old gen_store() did.
Reviewed-by: Richard Henderson
Signed-off-by: Bastian Koppelmann
Signed-off-by: Peer Adelt
---
v1 -> v2:
- trans_store -> gen_store
- removed negative memop check
target/riscv
Signed-off-by: Bastian Koppelmann
Signed-off-by: Peer Adelt
---
v1 -> v2:
- Stack allocate arg_c_* structs
- ex_rvc_register returns int
- special case of trans_c_addi4spn() returns false
target/riscv/Makefile.objs | 9 ++-
target/riscv/insn16.decode |
manual decoding in gen_arith() is not necessary with decodetree. For now
the function is called trans_arith as the original gen_arith still
exisits. The former will be renamed to gen_arith as soon as the old
gen_arith can be removed.
Signed-off-by: Bastian Koppelmann
Signed-off-by: Peer Adelt
trans_jalr() is the only caller, so move the code into trans_jalr().
Reviewed-by: Richard Henderson
Signed-off-by: Bastian Koppelmann
Signed-off-by: Peer Adelt
---
target/riscv/insn_trans/trans_rvi.inc.c | 28 +-
target/riscv/translate.c| 38
This also removes all functions that now became obsolete.
Signed-off-by: Bastian Koppelmann
---
target/riscv/insn16.decode | 34 +-
target/riscv/insn_trans/trans_rvc.inc.c | 103
target/riscv/translate.c| 151 +---
3 files
Reviewed-by: Richard Henderson
Signed-off-by: Bastian Koppelmann
Signed-off-by: Peer Adelt
---
v1 -> v2:
- trans_shift -> gen_shift
target/riscv/insn_trans/trans_rvi.inc.c | 79 +
target/riscv/translate.c| 59 ++
2
with all 16 bit insns moved to decodetree no path is falling back to
gen_system(), so we can remove it.
Reviewed-by: Richard Henderson
Signed-off-by: Bastian Koppelmann
Signed-off-by: Peer Adelt
---
target/riscv/translate.c | 32
1 file changed, 32 deletions
Signed-off-by: Bastian Koppelmann
---
target/riscv/insn_trans/trans_rvi.inc.c | 14 +++---
target/riscv/insn_trans/trans_rvm.inc.c | 14 +++---
target/riscv/translate.c| 4 ++--
3 files changed, 16 insertions(+), 16 deletions(-)
diff --git a/target/riscv
gen_arith_imm() does a lot of decoding manually, which was hard to read in
case of the shift instructions and is not necessary anymore with decodetree.
Signed-off-by: Bastian Koppelmann
Signed-off-by: Peer Adelt
---
v1 -> v2:
- trans_arith_imm -> gen_arith_imm
- Add m
+++---
1 file changed, 23 insertions(+), 11 deletions(-)
Reviewed-by: Bastian Koppelmann
Cheers,
Bastian
On 10/23/18 2:04 PM, Richard Henderson wrote:
??? Needs simultaneous corresponding changes to all
translators using decodetree.
---
scripts/decodetree.py | 5 ++---
1 file changed, 2 insertions(+), 3 deletions(-)
Was the only intend of the insn argument to be used for manual decoding
in a
On 10/23/18 3:08 PM, Richard Henderson wrote:
On 10/23/18 2:04 PM, Bastian Koppelmann wrote:
On 10/23/18 2:04 PM, Richard Henderson wrote:
??? Needs simultaneous corresponding changes to all
translators using decodetree.
---
scripts/decodetree.py | 5 ++---
1 file changed, 2 insertions
+--
7 files changed, 234 insertions(+), 241 deletions(-)
Reviewed-by: Bastian Koppelmann
Cheers,
Bastian
target/riscv/insn32.decode | 12 ++--
3 files changed, 12 insertions(+), 12 deletions(-)
Reviewed-by: Bastian Koppelmann
Cheers,
Bastian
+++-
3 files changed, 26 insertions(+), 47 deletions(-)
Pretty cool :)
Reviewed-by: Bastian Koppelmann
Cheers,
Bastian
On 10/20/18 9:14 AM, Bastian Koppelmann wrote:
@@ -338,27 +375,63 @@ static bool trans_and(DisasContext *ctx, arg_and *a,
uint32_t insn)
static bool trans_addiw(DisasContext *ctx, arg_addiw *a, uint32_t insn)
{
-gen_arith_imm(ctx, OPC_RISC_ADDIW, a->rd, a->rs1,
On 10/23/18 2:04 PM, Richard Henderson wrote:
This primarily solves the case for RVC that several insns are
completely different, decode and all, between the two. But it
also means that we need less ifdefing for RV{I,M,A,F,D}.
---
target/riscv/insn_trans/trans_rva.inc.c | 46 +---
On 10/25/18 6:58 PM, Palmer Dabbelt wrote:
Reviewed-by: Palmer Dabbelt
How do you want to go about merging these? It looks like it should be
possible to merge the patch set piecemeal, which I'd actually be happy
doing as it'll be easier to get these out for testing that way. That
way we
On 10/25/18 12:21 AM, Palmer Dabbelt wrote:
On Sat, 20 Oct 2018 00:14:22 PDT (-0700),
kbast...@mail.uni-paderborn.de wrote:
Hi,
this patchset converts the RISC-V decoder to decodetree in three
major steps:
1) Convert 32-bit instructions to decodetree [Patch 1-14]:
Many of the gen_* fun
On 10/26/18 3:58 PM, Richard Henderson wrote:
On 10/26/18 11:49 AM, Bastian Koppelmann wrote:
I think you can pick up everything up to the RVC conversion which still needs
the work suggested by Richard. Thanks, for picking it up :)
Even then I thought we were talking about splitting the RV64
On 10/20/18 9:14 AM, Bastian Koppelmann wrote:
[...]
+static bool trans_fclass_d(DisasContext *ctx, arg_fclass_d *a, uint32_t insn)
+{
+#if defined(TARGET_RISCV64)
+REQUIRE_FPU;
+
+TCGv t0 = tcg_temp_new();
+gen_helper_fclass_d(t0, cpu_fpr[a->rs1]);
+gen_set_gpr(a->
On 10/31/18 11:44 AM, Bastian Koppelmann wrote:
On 10/20/18 9:14 AM, Bastian Koppelmann wrote:
[...]
+static bool trans_fclass_d(DisasContext *ctx, arg_fclass_d *a,
uint32_t insn)
+{
+#if defined(TARGET_RISCV64)
+ REQUIRE_FPU;
+
+ TCGv t0 = tcg_temp_new();
+ gen_helper_fclass_d(t0
Reviewed-by: Richard Henderson
Signed-off-by: Bastian Koppelmann
Signed-off-by: Peer Adelt
---
v2 -> v3:
- moved 64-bit only insn to insn64.decode
- dropped insn argument of trans_foo functions
target/riscv/insn32.decode | 10 +++
target/riscv/insn64.dec
Signed-off-by: Bastian Koppelmann
Signed-off-by: Peer Adelt
---
v2 -> v3:
- split into two patches for RV32 and RV64
- dropped insn argument of trans_foo functions
target/riscv/insn32.decode | 10
target/riscv/insn_trans/trans_rvi.inc.c |
Reviewed-by: Richard Henderson
Signed-off-by: Bastian Koppelmann
Signed-off-by: Peer Adelt
---
v2 -> v3:
- removed %pred/%succ
- dropped insn argument of trans_foo functions
target/riscv/insn32.decode | 2 ++
target/riscv/insn_trans/trans_rvi.inc.c |
Reviewed-by: Richard Henderson
Signed-off-by: Bastian Koppelmann
Signed-off-by: Peer Adelt
---
v2 -> v3:
- dropped insn argument of trans_foo functions
target/riscv/insn32.decode | 35 +++
target/riscv/insn_trans/trans_rvf.inc.c | 334
target/ri
this splits the 64-bit only instructions into its own decode file such
that we generate the decoder for these instructions only for the RISC-V
64 bit target.
Signed-off-by: Bastian Koppelmann
Signed-off-by: Peer Adelt
---
target/riscv/Makefile.objs | 8 +---
target/riscv
we cannot remove the call to gen_arith() in decode_RV32_64G() since it
is used to translate multiply instructions.
Signed-off-by: Bastian Koppelmann
Signed-off-by: Peer Adelt
---
v2 -> v3:
- moved 64-bit only insn to insn64.decode
- dropped insn argument of trans_foo functions
tar
Reviewed-by: Richard Henderson
Signed-off-by: Bastian Koppelmann
Signed-off-by: Peer Adelt
---
v2 -> v3:
- dropped insn argument of trans_foo functions
target/riscv/insn32.decode | 17 +++
target/riscv/insn_trans/trans_rva.inc.c | 145
target/ri
only a translate functions of rvc need to handle special cases. For
the other rvc instruction we can remove the extra layer of indirection.
Signed-off-by: Bastian Koppelmann
---
target/riscv/insn16.decode | 37 +--
target/riscv/insn_trans/trans_rvc.inc.c | 48
Reviewed-by: Richard Henderson
Signed-off-by: Bastian Koppelmann
Signed-off-by: Peer Adelt
---
v2 -> v3:
- dropped insn argument of trans_foo functions
target/riscv/insn32.decode | 8 +++
target/riscv/insn_trans/trans_rvi.inc.c | 79 +
target/ri
Reviewed-by: Palmer Dabbelt
Reviewed-by: Richard Henderson
Signed-off-by: Bastian Koppelmann
Signed-off-by: Peer Adelt
---
v2 -> v3:
- dropped insn argument of trans_foo functions
- removal of AUIPC moved to 0002
- &branch -> &b
target/riscv/insn32.decode
Reviewed-by: Richard Henderson
Signed-off-by: Bastian Koppelmann
Signed-off-by: Peer Adelt
---
v2 -> v3:
- moved 64-bit only insn to insn64.decode
- dropped insn argument of trans_foo functions
target/riscv/insn64.decode | 13 +++
target/riscv/insn_trans/trans_rva.in
CPURISCVState is rarely used, so there is no need to pass it to every
translate function. This paves the way for decodetree which only passes
DisasContext to translate functions.
Reviewed-by: Palmer Dabbelt
Signed-off-by: Bastian Koppelmann
---
target/riscv/translate.c | 15 ---
1
Reviewed-by: Richard Henderson
Signed-off-by: Bastian Koppelmann
Signed-off-by: Peer Adelt
---
target/riscv/insn_trans/trans_rvi.inc.c | 78 +
target/riscv/translate.c| 59 ++-
2 files changed, 85 insertions(+), 52 deletions(-)
diff
it splices flwsp_ldsp, fswsp_sdsp, and jal_addiw and makes each of them
reuse the code generator used for the non compressed insns.
Signed-off-by: Bastian Koppelmann
---
target/riscv/insn16-32.decode | 7 +
target/riscv/insn16-64.decode | 5
target/riscv/insn16
manual decoding in gen_arith() is not necessary with decodetree. For now
the function is called trans_arith as the original gen_arith still
exists. The former will be renamed to gen_arith as soon as the old
gen_arith can be removed.
Reviewed-by: Richard Henderson
Signed-off-by: Bastian
for now only LUI & AUIPC are decoded and translated. If decodetree fails, we
fall back to the old decoder.
Reviewed-by: Richard Henderson
Signed-off-by: Bastian Koppelmann
Signed-off-by: Peer Adelt
---
v2 -> v3:
- ex_shift_amount returns int
- dropped insn argument of tr
We now utilizes argument-sets of decodetree such that no manual
decoding is necessary.
Reviewed-by: Richard Henderson
Signed-off-by: Bastian Koppelmann
Signed-off-by: Peer Adelt
---
target/riscv/insn_trans/trans_rvi.inc.c | 46 +---
target/riscv/translate.c
These all expand simply to R format instructions.
Signed-off-by: Bastian Koppelmann
---
target/riscv/Makefile.objs | 10 +++---
target/riscv/insn16-64.decode | 24 ++
target/riscv/insn16.decode | 15 +
target/riscv/insn_trans
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