[PULL 18/20] target/tricore: Implement privilege level for all insns

Reviewed-by: Richard Henderson Signed-off-by: Bastian Koppelmann Message-Id: <20230621142302.1648383-7-kbast...@mail.uni-paderborn.de> --- target/tricore/translate.c | 43 +- 1 file changed, 33 insertions(+), 10 deletions(-) diff --git a/target/t

Re: [PULL 09/20] target/tricore: Fix out-of-bounds index in imask instruction

On Thu, Jun 22, 2023 at 10:43:16AM +0300, Michael Tokarev wrote: > 21.06.2023 19:14, Bastian Koppelmann wrote: > > From: Siqi Chen > > > > When translating "imask" instruction of Tricore architecture, QEMU did not > > check whether the register in

Re: [PULL 09/20] target/tricore: Fix out-of-bounds index in imask instruction

Hi Michael, On Fri, Jun 23, 2023 at 09:54:54AM +0300, Michael Tokarev wrote: > 22.06.2023 17:51, Bastian Koppelmann wrote: > .. > > > Is it a -stable material? > > > > Yes. If you pick this up, make sure you also pick up > > https://lore.kernel.org/qemu-dev

Re: [PULL 09/20] target/tricore: Fix out-of-bounds index in imask instruction

On Fri, Jun 23, 2023 at 01:29:23PM +0300, Michael Tokarev wrote: > 23.06.2023 12:51, Bastian Koppelmann wrote: > > Here we go: > https://www.qemu.org/docs/master/devel/stable-process.html > > Basically, any bugfix you, as a subsystem maintainer, think is good for > stable,

[PULL 0/6] tricore queue

A versions - Add simple tests written in C -------- Bastian Koppelmann (6): tests/tcg/tricore: Move asm tests into 'asm' directory tests/tcg/tricore: Uses label for memory addresses tests/tcg/tricore: Add first C

[PULL 2/6] tests/tcg/tricore: Uses label for memory addresses

the linker might rearrange sections, so lets reference memory by label name instead of addr + off. Signed-off-by: Bastian Koppelmann Message-Id: <20230526061946.54514-3-kbast...@mail.uni-paderborn.de> --- tests/tcg/tricore/asm/macros.h | 1 - tests/tcg/tricore/asm/test_ld_bu

[PULL 1/6] tests/tcg/tricore: Move asm tests into 'asm' directory

this seperates these tests from the upcoming tests written in C. Also rename the compiled test to 'test_.asm.tst'. Signed-off-by: Bastian Koppelmann Message-Id: <20230526061946.54514-2-kbast...@mail.uni-paderborn.de> --- tests/tcg/tricore/Makefile.sof

[PULL 4/6] target/tricore: Refactor PCXI/ICR register fields

starting from ISA version 1.6.1 (previously known as 1.6P/E), some bitfields in PCXI and ICR have changed. We also refactor these registers using the register fields API. Signed-off-by: Bastian Koppelmann Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1453 Message-Id

[PULL 3/6] tests/tcg/tricore: Add first C program

this allows us to exercise the startup code used by GCC to call main(). Signed-off-by: Bastian Koppelmann Message-Id: <20230526061946.54514-4-kbast...@mail.uni-paderborn.de> --- configure | 1 + tests/tcg/tricore/Makefile.softmmu-target | 13 + tes

[PULL 5/6] target/tricore: Fix wrong PSW for call insns

we were copying PSW into a local variable, updated PSW.CDE in the local and never wrote it back. So when we called save_context_upper() we were using the non-local version of PSW which did not contain the updated PSW.CDE. Signed-off-by: Bastian Koppelmann Message-Id: <20230526061946.5451

[PULL 6/6] tests/tcg/tricore: Add recursion test for CSAs

Signed-off-by: Bastian Koppelmann Message-Id: <20230526061946.54514-7-kbast...@mail.uni-paderborn.de> --- tests/tcg/tricore/Makefile.softmmu-target | 3 ++- tests/tcg/tricore/c/test_context_save_areas.c | 15 +++ 2 files changed, 17 insertions(+), 1 deletion(-) creat

Re: [PATCH v2 06/22] target/tricore: Clean up local variable shadowing

tant_i32(const9); > | ^~~~ > target/tricore/translate.c:4958:10: note: shadowed declaration is here >4958 | TCGv temp; > | ^~~~ > > Signed-off-by: Philippe Mathieu-Daudé > --- > target/tricore/translate.c | 6 +++--- > 1 file changed, 3 insertion

Re: [PATCH v3 17/32] target/tricore: Use generic helper to show CPU model names

tricore/helper.c | 13 + > 2 files changed, 10 insertions(+), 12 deletions(-) Reviewed-by: Bastian Koppelmann Cheers, Bastian

[PATCH 06/10] tests/tcg/tricore: Add from dextr to lt

Signed-off-by: Bastian Koppelmann --- tests/tcg/tricore/asm/macros.h | 51 ++-- tests/tcg/tricore/asm/test_arith.S | 53 ++ 2 files changed, 102 insertions(+), 2 deletions(-) diff --git a/tests/tcg/tricore/asm/macros.h b/tests/tcg/tricore

[PATCH 02/10] hw/tricore: Log failing test in testdevice

Signed-off-by: Bastian Koppelmann --- hw/tricore/tricore_testdevice.c | 4 1 file changed, 4 insertions(+) diff --git a/hw/tricore/tricore_testdevice.c b/hw/tricore/tricore_testdevice.c index a1563aa568..d0f8db9089 100644 --- a/hw/tricore/tricore_testdevice.c +++ b/hw/tricore

[PATCH 08/10] tests/tcg/tricore: Add test from 'shuffle' to 'xor.t'

Signed-off-by: Bastian Koppelmann --- tests/tcg/tricore/asm/test_arith.S | 34 ++ 1 file changed, 34 insertions(+) diff --git a/tests/tcg/tricore/asm/test_arith.S b/tests/tcg/tricore/asm/test_arith.S index 728509cfa9..02637f89f9 100644 --- a/tests/tcg/tricore/asm

[PATCH 09/10] target/tricore: Remove CSFRs from cpu.h

these are already defined in 'csfr.h.inc'. We don't need to duplicate these registers. Signed-off-by: Bastian Koppelmann --- target/tricore/cpu.h | 143 +++ 1 file changed, 9 insertions(+), 134 deletions(-) diff --git a/target/tricore

[PATCH 05/10] tests/tcg/tricore: Add test for and to csub

Signed-off-by: Bastian Koppelmann --- tests/tcg/tricore/asm/macros.h | 11 +++ tests/tcg/tricore/asm/test_arith.S | 47 ++ 2 files changed, 58 insertions(+) diff --git a/tests/tcg/tricore/asm/macros.h b/tests/tcg/tricore/asm/macros.h index 8ed2249b0d

[PATCH 03/10] tests/tcg: Reset result register after each test

some insns use the result register implicitly as an input. Thus, we could end up with data from the previous insn spilling over. Signed-off-by: Bastian Koppelmann --- tests/tcg/tricore/asm/macros.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/tests/tcg/tricore/asm

[PATCH 04/10] tests/tcg/tricore: Add test for all arith insns up to addx

Signed-off-by: Bastian Koppelmann --- tests/tcg/tricore/Makefile.softmmu-target | 3 +- tests/tcg/tricore/asm/macros.h| 50 +++ tests/tcg/tricore/asm/test_arith.S| 41 +++ 3 files changed, 93 insertions(+), 1 deletion(-) create mode

[PATCH 01/10] tests/tcg/tricore: Extended and non-extened regs now match

RSx for d regs and e regs now use the same numbering. This makes sure that mixing d and e registers in an insn test will not overwrite data between registers. Signed-off-by: Bastian Koppelmann --- tests/tcg/tricore/asm/macros.h | 38 +- 1 file changed, 19

[PATCH 07/10] tests/tcg/tricore: Add test from 'max' to 'shas'

Signed-off-by: Bastian Koppelmann --- tests/tcg/tricore/asm/macros.h | 13 tests/tcg/tricore/asm/test_arith.S | 105 + 2 files changed, 118 insertions(+) diff --git a/tests/tcg/tricore/asm/macros.h b/tests/tcg/tricore/asm/macros.h index 92f0f7b22b

[PATCH 10/10] target/tricore: Change effective address (ea) to target_ulong

as this is an effective address and those cannot be signed, it should not be a signed integed. Signed-off-by: Bastian Koppelmann --- target/tricore/op_helper.c | 16 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/target/tricore/op_helper.c b/target/tricore

[PATCH 00/10] TriCore tests and cleanups

already defined in csfr.h.inc, so I use this definition. I also changed the types of the effective address (ea) in op_helper.c to target_ulong, as it cannot be sign extened. Cheers, Bastian Bastian Koppelmann (10): tests/tcg/tricore: Extended and non-extened regs now match hw/tricore: Log failing

Re: [PATCH 6/7] target/tricore: Use tcg_gen_*extract_tl

On Thu, Oct 19, 2023 at 11:29:20AM -0700, Richard Henderson wrote: > The EXTR instructions can use the extract opcodes. > > Signed-off-by: Richard Henderson > --- > target/tricore/translate.c | 20 > 1 file changed, 4 insertions(+), 16 deletions(-) Re

Re: [RFC PATCH v3 34/78] target/tricore: add fallthrough pseudo-keyword

On Fri, Oct 13, 2023 at 11:46:02AM +0300, Emmanouil Pitsidianakis wrote: > In preparation of raising -Wimplicit-fallthrough to 5, replace all > fall-through comments with the fallthrough attribute pseudo-keyword. > > Signed-off-by: Emmanouil Pitsidianakis > --- Reviewed-by: Bas

[PATCH 1/6] target/tricore: Add semihosting stub

Signed-off-by: Bastian Koppelmann --- target/tricore/helper.h | 1 + target/tricore/meson.build| 1 + target/tricore/tricore-semi.c | 197 ++ 3 files changed, 199 insertions(+) create mode 100644 target/tricore/tricore-semi.c diff --git a/target

[PATCH 4/6] target/tricore: Add close semihosting call

Signed-off-by: Bastian Koppelmann --- target/tricore/tricore-semi.c | 16 1 file changed, 16 insertions(+) diff --git a/target/tricore/tricore-semi.c b/target/tricore/tricore-semi.c index 6f321391ef..2188ceeed0 100644 --- a/target/tricore/tricore-semi.c +++ b/target/tricore

[PATCH 6/6] target/tricore: Enable semihosting

Signed-off-by: Bastian Koppelmann --- configs/devices/tricore-softmmu/default.mak | 1 + docs/about/emulation.rst| 3 +++ qemu-options.hx | 3 ++- target/tricore/translate.c | 13 +++-- 4 files changed, 17 insertions

[PATCH 3/6] target/tricore: Add lseek semihosting call

Signed-off-by: Bastian Koppelmann --- target/tricore/tricore-semi.c | 14 ++ 1 file changed, 14 insertions(+) diff --git a/target/tricore/tricore-semi.c b/target/tricore/tricore-semi.c index ccbeae4bc0..6f321391ef 100644 --- a/target/tricore/tricore-semi.c +++ b/target/tricore

[PATCH 0/6] TriCore Semihosting

test.elf Cheers, Bastian [1] https://github.com/bkoppelmann/package_940/tree/main/newlib/libgloss/tricore Bastian Koppelmann (6): target/tricore: Add semihosting stub target/tricore: Add read and write semihosting calls target/tricore: Add lseek semihosting call target/tricore: Add c

[PATCH 2/6] target/tricore: Add read and write semihosting calls

Signed-off-by: Bastian Koppelmann --- target/tricore/tricore-semi.c | 52 +++ 1 file changed, 52 insertions(+) diff --git a/target/tricore/tricore-semi.c b/target/tricore/tricore-semi.c index 27e1bdc59d..ccbeae4bc0 100644 --- a/target/tricore/tricore-semi.c +++ b

[PATCH 5/6] target/tricore: Add open and creat semihosting calls

Signed-off-by: Bastian Koppelmann --- target/tricore/tricore-semi.c | 101 ++ 1 file changed, 101 insertions(+) diff --git a/target/tricore/tricore-semi.c b/target/tricore/tricore-semi.c index 2188ceeed0..34e546c3bf 100644 --- a/target/tricore/tricore-semi.c

[PATCH 08/10] target/tricore: Swap src and dst reg for RCRR_INSERT

Signed-off-by: Bastian Koppelmann --- target/tricore/translate.c | 8 tests/tcg/tricore/asm/macros.h | 9 + tests/tcg/tricore/asm/test_insert.S | 5 + 3 files changed, 18 insertions(+), 4 deletions(-) diff --git a/target/tricore/translate.c b/target/tricore

[PATCH 10/10] target/tricore: Fix FTOUZ being ISA v1.3.1 up

Signed-off-by: Bastian Koppelmann --- target/tricore/translate.c | 6 +- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/target/tricore/translate.c b/target/tricore/translate.c index 89ed48c951..a7865db75c 100644 --- a/target/tricore/translate.c +++ b/target/tricore/translate.c

[PATCH 07/10] target/tricore: Fix RCPW/RRPW_INSERT insns for width = 0

we would crash if width was 0 for these insns, as tcg_gen_deposit() is undefined for that case. For TriCore, width = 0 is a mov from the src reg to the dst reg, so we special case this here. Signed-off-by: Bastian Koppelmann --- target/tricore/translate.c | 10 -- tests/tcg

[PATCH 09/10] target/tricore: Replace cpu_*_code with translator_*

Signed-off-by: Bastian Koppelmann --- target/tricore/translate.c | 7 --- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/target/tricore/translate.c b/target/tricore/translate.c index a68660b326..89ed48c951 100644 --- a/target/tricore/translate.c +++ b/target/tricore

[PATCH 05/10] target/tricore: Implement ftohp insn

reported in https://gitlab.com/qemu-project/qemu/-/issues/1667 Signed-off-by: Bastian Koppelmann --- target/tricore/fpu_helper.c | 41 +++ target/tricore/helper.c | 1 + target/tricore/helper.h | 1 + target/tricore

[PATCH 00/10] TriCore 1.6.2 insn and bugfixes

Hi, this series implements the insns reported in [1], as well as ftou. Also I fixed two bugs in the insert insn which I came across during testing. Cheers, Bastian [1] https://gitlab.com/qemu-project/qemu/-/issues/1667 Bastian Koppelmann (10): tests/tcg/tricore: Bump cpu to tc37x target

[PATCH 06/10] target/tricore: Implement hptof insn

Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1667 Signed-off-by: Bastian Koppelmann --- target/tricore/fpu_helper.c | 39 +++ target/tricore/helper.h | 1 + target/tricore/translate.c| 7 target/tricore/tricore

[PATCH 01/10] tests/tcg/tricore: Bump cpu to tc37x

we don't want to exclude ISA v1.6.2 insns from our tests. Signed-off-by: Bastian Koppelmann --- tests/tcg/tricore/Makefile.softmmu-target | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tests/tcg/tricore/Makefile.softmmu-target b/tests/tcg/tricore/Makefile.softmmu-t

[PATCH 03/10] target/tricore: Correctly handle FPU RM from PSW

ore is not the one used by softfloat. Signed-off-by: Bastian Koppelmann --- target/tricore/helper.c | 18 -- 1 file changed, 16 insertions(+), 2 deletions(-) diff --git a/target/tricore/helper.c b/target/tricore/helper.c index 6d076ac36f..e615c3d6d4 100644 --- a/target/tricore/he

[PATCH 04/10] target/tricore: Implement FTOU insn

Signed-off-by: Bastian Koppelmann --- target/tricore/fpu_helper.c | 25 +++ target/tricore/helper.h | 1 + target/tricore/translate.c| 3 +++ tests/tcg/tricore/Makefile.softmmu-target | 1 + tests/tcg/tricore/asm/test_ftou.S

[PATCH 02/10] target/tricore: Implement CRCN insn

reported in https://gitlab.com/qemu-project/qemu/-/issues/1667 Signed-off-by: Bastian Koppelmann --- target/tricore/helper.h | 1 + target/tricore/op_helper.c| 66 +++ target/tricore/translate.c| 6 +++ target/tricore

Re: [PATCH 05/10] target/tricore: Implement ftohp insn

On Sat, Aug 26, 2023 at 09:55:05PM -0700, Richard Henderson wrote: > On 8/26/23 09:02, Bastian Koppelmann wrote: > > +uint32_t helper_ftohp(CPUTriCoreState *env, uint32_t arg) > > +{ > > +float32 f_arg = make_float32(arg); > > +uint32_t result = 0;

Re: [PATCH 08/10] target/tricore: Swap src and dst reg for RCRR_INSERT

On Sat, Aug 26, 2023 at 10:06:22PM -0700, Richard Henderson wrote: > On 8/26/23 09:02, Bastian Koppelmann wrote: > > Signed-off-by: Bastian Koppelmann > > --- > > target/tricore/translate.c | 8 > > tests/tcg/tricore/asm/macros.h | 9 +

Re: [PATCH 04/10] target/tricore: Implement FTOU insn

On Sat, Aug 26, 2023 at 09:50:51PM -0700, Richard Henderson wrote: > On 8/26/23 09:02, Bastian Koppelmann wrote: > > +uint32_t helper_ftou(CPUTriCoreState *env, uint32_t arg) > > +{ > > +float32 f_arg = make_float32(arg); > > +uint32_t result; > > +int

Re: [PATCH 04/10] target/tricore: Implement FTOU insn

On Sun, Aug 27, 2023 at 07:49:52AM -0700, Richard Henderson wrote: > On 8/27/23 04:07, Bastian Koppelmann wrote: > > On Sat, Aug 26, 2023 at 09:50:51PM -0700, Richard Henderson wrote: > > > On 8/26/23 09:02, Bastian Koppelmann wrote: > > > > +uint32_t helper_ftou(CPUT

Re: [PATCH 04/10] target/tricore: Implement FTOU insn

On Sun, Aug 27, 2023 at 11:32:03AM -0700, Richard Henderson wrote: > On 8/27/23 09:36, Bastian Koppelmann wrote: > > On Sun, Aug 27, 2023 at 07:49:52AM -0700, Richard Henderson wrote: > > > On 8/27/23 04:07, Bastian Koppelmann wrote: > > > > On Sat, Aug 26, 202

[PATCH v2 04/11] target/tricore: Implement FTOU insn

Signed-off-by: Bastian Koppelmann --- v1 -> v2: - Remove special case for NAN input - Clarified, why we need arg < 0.0 special case target/tricore/fpu_helper.c | 32 +++ target/tricore/helper.h | 1 + target/tricore/trans

[PATCH v2 02/11] target/tricore: Implement CRCN insn

reported in https://gitlab.com/qemu-project/qemu/-/issues/1667 Signed-off-by: Bastian Koppelmann --- v1 -> v2: - Removed useless deposits in crc_div() - Replaced final deposit() with extract() in helper_crcn() - Add trap for CRCN insn if not feature_162 target/tricore/helpe

[PATCH v2 11/11] target/tricore: Fix FTOUZ being ISA v1.3.1 up

Reviewed-by: Richard Henderson Signed-off-by: Bastian Koppelmann --- target/tricore/translate.c | 6 +- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/target/tricore/translate.c b/target/tricore/translate.c index cc2030be14..9770839749 100644 --- a/target/tricore/translate.c

[PATCH v2 03/11] target/tricore: Correctly handle FPU RM from PSW

ore is not the one used by softfloat. Reviewed-by: Richard Henderson Signed-off-by: Bastian Koppelmann --- target/tricore/helper.c | 18 -- 1 file changed, 16 insertions(+), 2 deletions(-) diff --git a/target/tricore/helper.c b/target/tricore/helper.c index 6d076ac36f..e615

[PATCH v2 01/11] tests/tcg/tricore: Bump cpu to tc37x

we don't want to exclude ISA v1.6.2 insns from our tests. Acked-by: Richard Henderson Signed-off-by: Bastian Koppelmann --- tests/tcg/tricore/Makefile.softmmu-target | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tests/tcg/tricore/Makefile.softmmu-target b/test

[PATCH v2 00/11] TriCore 1.6.2 insn and bugfixes

need a special case for arg being NAN (ftohp, hptof) Bastian Koppelmann (11): tests/tcg/tricore: Bump cpu to tc37x target/tricore: Implement CRCN insn target/tricore: Correctly handle FPU RM from PSW target/tricore: Implement FTOU insn target/tricore: Clarify special case for FTOUZ insn

[PATCH v2 07/11] target/tricore: Implement hptof insn

Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1667 Signed-off-by: Bastian Koppelmann --- v1 -> v2: - Removed special case for f_arg being infinity - Clarified, why we need a special case for arg being NAN target/tricore/fpu_helper.c |

[PATCH v2 06/11] target/tricore: Implement ftohp insn

reported in https://gitlab.com/qemu-project/qemu/-/issues/1667 Signed-off-by: Bastian Koppelmann --- v1 -> v2: - Removed special case for f_arg being infinity - Clarified, why we need a special case for arg being NAN target/tricore/fpu_helper.c |

[PATCH v2 10/11] target/tricore: Replace cpu_*_code with translator_*

Reviewed-by: Richard Henderson Signed-off-by: Bastian Koppelmann --- target/tricore/translate.c | 7 --- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/target/tricore/translate.c b/target/tricore/translate.c index 403533c564..cc2030be14 100644 --- a/target/tricore/translate.c

[PATCH v2 09/11] target/tricore: Swap src and dst reg for RCRR_INSERT

Signed-off-by: Bastian Koppelmann --- target/tricore/translate.c | 8 tests/tcg/tricore/asm/macros.h | 9 + tests/tcg/tricore/asm/test_insert.S | 5 + 3 files changed, 18 insertions(+), 4 deletions(-) diff --git a/target/tricore/translate.c b/target/tricore

[PATCH v2 08/11] target/tricore: Fix RCPW/RRPW_INSERT insns for width = 0

we would crash if width was 0 for these insns, as tcg_gen_deposit() is undefined for that case. For TriCore, width = 0 is a mov from the src reg to the dst reg, so we special case this here. Reviewed-by: Richard Henderson Signed-off-by: Bastian Koppelmann --- target/tricore/translate.c

[PATCH v2 05/11] target/tricore: Clarify special case for FTOUZ insn

this is not something other ISAs do, so clarify it with a comment. Signed-off-by: Bastian Koppelmann --- target/tricore/fpu_helper.c | 5 + 1 file changed, 5 insertions(+) diff --git a/target/tricore/fpu_helper.c b/target/tricore/fpu_helper.c index 3aefeb776e..d0c474c5f3 100644 --- a

Re: [PATCH v2 00/48] tcg patch queue

On Mon, Aug 28, 2023 at 06:52:42PM -0400, Stefan Hajnoczi wrote: > On Thu, 24 Aug 2023 at 14:29, Richard Henderson > wrote: > > > > The following changes since commit 50e7a40af372ee5931c99ef7390f5d3d6fbf6ec4: > > > > Merge tag 'pull-target-arm-20230824' of > > https://git.linaro.org/people/pmay

Re: [Qemu-devel] [PATCH] MAINTAINERS: Add include/hw/tricore/ to TriCore section

INERS b/MAINTAINERS > index 7196dba..dad82e7 100644 > --- a/MAINTAINERS > +++ b/MAINTAINERS > @@ -228,6 +228,7 @@ M: Bastian Koppelmann > S: Maintained > F: target-tricore/ > F: hw/tricore/ > +F: include/hw/tricore/ > > Guest CPU Cores (KVM): > -

Re: [Qemu-devel] [PATCH v4 35/64] target-tricore: Use clz opcode

Reviewed-by: Bastian Koppelmann Tested-by: Bastian Koppelmann Cheers, Bastian

Re: [Qemu-devel] [PATCH v4 52/64] target-tricore: Use clrsb helper

On 11/23/2016 02:01 PM, Richard Henderson wrote: > Signed-off-by: Richard Henderson > --- > target-tricore/helper.h| 1 - > target-tricore/op_helper.c | 5 - > target-tricore/translate.c | 2 +- > 3 files changed, 1 insertion(+), 7 deletions(-) > Reviewed-by: Basti

[Qemu-devel] [PATCH v2 0/5]

omments on that? Additionally this patch set adds the UPDFL instructions. Cheers, Bastian [1] http://lists.nongnu.org/archive/html/qemu-devel/2016-06/msg01936.html v1 -> v2: - ftouz: Correctly convert the result from uint32 to f32 Bastian Koppelmann (3): target-tricore: Added FTOU

[Qemu-devel] [PATCH v2 3/5] target-tricore: Added new MOV instruction variant

From: Peer Adelt Puts the content of data register D[a] into E[c][63:32] and the content of data register D[b] into E[c][31:0]. [BK: fix style error] Signed-off-by: Peer Adelt Message-Id: <1465314555-11501-4-git-send-email-peer.ad...@c-lab.de> --- target-tricore/translate.c | 15

[Qemu-devel] [PATCH v2 4/5] target-tricore: Added new JNE instruction variant

From: Peer Adelt If D[15] is != sign_ext(const4) then PC will be set to (PC + zero_ext(disp4 + 16)). [BK: fixed style errors] Signed-off-by: Peer Adelt Message-Id: <1465314555-11501-5-git-send-email-peer.ad...@c-lab.de> --- target-tricore/translate.c | 18 ++ target-trico

[Qemu-devel] [PATCH v2 5/5] target-tricore: Add updfl instruction

Signed-off-by: Bastian Koppelmann --- target-tricore/fpu_helper.c | 12 target-tricore/helper.h | 1 + target-tricore/translate.c | 3 +++ 3 files changed, 16 insertions(+) diff --git a/target-tricore/fpu_helper.c b/target-tricore/fpu_helper.c index d530a0b..89de0ea 100644

[Qemu-devel] [PATCH v2 1/5] target-tricore: Added FTOUZ instruction

Converts a 32-bit floating point number to an unsigned int. The result is rounded towards zero. Signed-off-by: Bastian Koppelmann --- v1 -> v2: - ftouz: Correctly convert the result from uint32 to f32 target-tricore/fpu_helper.c | 43 +++ tar

[Qemu-devel] [PATCH v2 2/5] target-tricore: Added MADD.F and MSUB.F instructions

Multiplies D[a] and D[b] and adds/subtracts the result to/from D[d]. The result is put in D[c]. All operands are floating-point numbers. Signed-off-by: Bastian Koppelmann --- target-tricore/fpu_helper.c | 93 - target-tricore/helper.h | 2

Re: [Qemu-devel] [PATCH v2 1/5] target-tricore: Added FTOUZ instruction

On 11/08/2016 12:36 PM, Richard Henderson wrote: > On 11/07/2016 03:44 PM, Bastian Koppelmann wrote: >> Converts a 32-bit floating point number to an unsigned int. The >> result is rounded towards zero. >> >> Signed-off-by: Bastian Koppelmann >> --- >> v1 -

Re: [Qemu-devel] [PATCH v2 1/5] target-tricore: Added FTOUZ instruction

On 11/08/2016 04:06 PM, Richard Henderson wrote: > On 11/08/2016 02:37 PM, Bastian Koppelmann wrote: >> Consider 0x836d4e86 as an input which is clearly negative, however >> float_flag_invalid is not set. The hardware on the other hand does set >> it. > > Hmm

Re: [Qemu-devel] [PATCH v2 2/5] target-tricore: Added MADD.F and MSUB.F instructions

On 11/08/2016 12:42 PM, Richard Henderson wrote: > On 11/07/2016 03:44 PM, Bastian Koppelmann wrote: >> Multiplies D[a] and D[b] and adds/subtracts the result to/from D[d]. >> The result is put in D[c]. All operands are floating-point numbers. >> >> Signed

Re: [Qemu-devel] [PATCH v2 1/5] target-tricore: Added FTOUZ instruction

On 11/08/2016 04:25 PM, Richard Henderson wrote: > On 11/08/2016 04:12 PM, Bastian Koppelmann wrote: >> On 11/08/2016 04:06 PM, Richard Henderson wrote: >>> On 11/08/2016 02:37 PM, Bastian Koppelmann wrote: >>>> Consider 0x836d4e86 as an input whic

[Qemu-devel] [PATCH v3 4/5] target-tricore: Added new JNE instruction variant

From: Peer Adelt If D[15] is != sign_ext(const4) then PC will be set to (PC + zero_ext(disp4 + 16)). [BK: fixed style errors] Signed-off-by: Peer Adelt Message-Id: <1465314555-11501-5-git-send-email-peer.ad...@c-lab.de> --- target-tricore/translate.c | 18 ++ target-trico

[Qemu-devel] [PATCH v3 0/5] Added 7 instructions to the tricore target

eded. [05/05] Add fpu_set_state() to update softfloats rounding mode [05/05] Move generation of the updfl helper to decode_rr_divide() v1 -> v2: [01/05] ftouz: Correctly convert the result from uint32 to f32 Bastian Koppelmann (3): target-tricore: Added FTOUZ instruction targe

[Qemu-devel] [PATCH v3 3/5] target-tricore: Added new MOV instruction variant

From: Peer Adelt Puts the content of data register D[a] into E[c][63:32] and the content of data register D[b] into E[c][31:0]. [BK: fix style error] [BK: Allocate temporaries only when needed] Signed-off-by: Peer Adelt Message-Id: <1465314555-11501-4-git-send-email-peer.ad...@c-lab.de> --- v2

[Qemu-devel] [PATCH v3 2/5] target-tricore: Added MADD.F and MSUB.F instructions

Multiplies D[a] and D[b] and adds/subtracts the result to/from D[d]. The result is put in D[c]. All operands are floating-point numbers. Signed-off-by: Bastian Koppelmann --- v2 -> v3: - f_maddsub_nan_result() now gets a boolean value indicating whether the muladd_negate_c flag is

[Qemu-devel] [PATCH v3 1/5] target-tricore: Added FTOUZ instruction

Converts a 32-bit floating point number to an unsigned int. The result is rounded towards zero. Signed-off-by: Bastian Koppelmann --- v2 -> v3: - simplified exception flag fixup in ftouz() target-tricore/fpu_helper.c | 27 +++ target-tricore/helper.h |

[Qemu-devel] [PATCH v3 5/5] target-tricore: Add updfl instruction

Signed-off-by: Bastian Koppelmann --- v2 -> v3: - Add fpu_set_state() to update softfloats rounding mode - Move generation of the updfl helper to decode_rr_divide() target-tricore/fpu_helper.c | 14 ++ target-tricore/helper.h | 1 + target-tricore/translate.c |

Re: [Qemu-devel] More platforms for the wiki

On 11/11/2016 06:04 AM, G 3 wrote: > http://fossboss.com/2016/08/13/use-qemu-test-operating-systems-distributions/ > > > On this page I found a huge list of QEMU emulators. I haven't heard of > most of them, but some of them are not on the platforms page. Do you > think we should add the missing

Re: [Qemu-devel] More platforms for the wiki

On 11/11/2016 04:18 PM, G 3 wrote: > > On Nov 11, 2016, at 10:16 AM, Bastian Koppelmann wrote: > >> On 11/11/2016 06:04 AM, G 3 wrote: >>> http://fossboss.com/2016/08/13/use-qemu-test-operating-systems-distributions/ >>> >>> >>> >>> O

Re: [Qemu-devel] [PATCH 10/25] target-tricore: Use clz opcode

On 11/16/2016 08:25 PM, Richard Henderson wrote: > diff --git a/target-tricore/translate.c b/target-tricore/translate.c > index 36f734a..69cdfb9 100644 > --- a/target-tricore/translate.c > +++ b/target-tricore/translate.c > @@ -6367,7 +6367,8 @@ static void decode_rr_logical_shift(CPUTriCoreState

Re: [Qemu-devel] [PATCH 10/25] target-tricore: Use clz opcode

On 11/17/2016 03:42 PM, Bastian Koppelmann wrote: > On 11/16/2016 08:25 PM, Richard Henderson wrote: >> diff --git a/target-tricore/translate.c b/target-tricore/translate.c >> index 36f734a..69cdfb9 100644 >> --- a/target-tricore/translate.c >> +++ b/target-tricor

Re: [Qemu-devel] [PATCH 16/25] tcg/i386: Handle ctz and clz opcodes

On 11/16/2016 08:25 PM, Richard Henderson wrote: > + > +OP_32_64(clz): > +if (const_args[2]) { > +tcg_debug_assert(have_bmi1); > +tcg_debug_assert(args[2] == (rexw ? 64 : 32)); > +tcg_out_modrm(s, OPC_LZCNT + rexw, args[0], args[1]); > +} else

Re: [Qemu-devel] [PATCH 16/25] tcg/i386: Handle ctz and clz opcodes

On 11/17/2016 08:59 PM, Richard Henderson wrote: > On 11/17/2016 08:53 PM, Richard Henderson wrote: >> On 11/17/2016 05:50 PM, Bastian Koppelmann wrote: >>> On 11/16/2016 08:25 PM, Richard Henderson wrote: >>>> + >>>> +OP_

Re: [Qemu-devel] [PATCH 16/25] tcg/i386: Handle ctz and clz opcodes

On 11/18/2016 12:03 AM, Richard Henderson wrote: > On 11/17/2016 11:09 PM, Bastian Koppelmann wrote: >> On 11/17/2016 08:59 PM, Richard Henderson wrote: >>> On 11/17/2016 08:53 PM, Richard Henderson wrote: >>>> On 11/17/2016 05:50 PM, Bastian Koppelmann wrote: >>

Re: [Qemu-devel] gen_helper_compute_fprf() definition

On 10/05/2016 05:33 PM, Programmingkid wrote: > Where is the definition for gen_helper_compute_fprf()? This function is used > in fp-impl.inc.c. > Depends on what you're looking for. The function to be called from binary translated code, would be called "helper_compute_fprf" and can be found in

[Qemu-devel] [PATCH 5/5] target-tricore: Add updfl instruction

Signed-off-by: Bastian Koppelmann --- target-tricore/fpu_helper.c | 12 target-tricore/helper.h | 1 + target-tricore/translate.c | 3 +++ 3 files changed, 16 insertions(+) diff --git a/target-tricore/fpu_helper.c b/target-tricore/fpu_helper.c index 32055f3..9720cb8 100644

[Qemu-devel] [PATCH 2/5] target-tricore: Added MADD.F and MSUB.F instructions

Multiplies D[a] and D[b] and adds/subtracts the result to/from D[d]. The result is put in D[c]. All operands are floating-point numbers. Signed-off-by: Bastian Koppelmann --- target-tricore/fpu_helper.c | 93 - target-tricore/helper.h | 2

[Qemu-devel] [PATCH 3/5] target-tricore: Added new MOV instruction variant

From: Peer Adelt Puts the content of data register D[a] into E[c][63:32] and the content of data register D[b] into E[c][31:0]. [BK: fix style error] Signed-off-by: Peer Adelt Message-Id: <1465314555-11501-4-git-send-email-peer.ad...@c-lab.de> --- target-tricore/translate.c | 15

[Qemu-devel] [PATCH 4/5] target-tricore: Added new JNE instruction variant

From: Peer Adelt If D[15] is != sign_ext(const4) then PC will be set to (PC + zero_ext(disp4 + 16)). [BK: fixed style errors] Signed-off-by: Peer Adelt Message-Id: <1465314555-11501-5-git-send-email-peer.ad...@c-lab.de> --- target-tricore/translate.c | 18 ++ target-trico

[Qemu-devel] [PATCH 0/5] Added 7 instructions to the tricore target

ditionally this patch set adds the UPDFL instructions. Cheers, Bastian [1] http://lists.nongnu.org/archive/html/qemu-devel/2016-06/msg01936.html Bastian Koppelmann (3): target-tricore: Added FTOUZ instruction target-tricore: Added MADD.F and MSUB.F instructions target-tricore:

[Qemu-devel] [PATCH 1/5] target-tricore: Added FTOUZ instruction

Converts a 32-bit floating point number to an unsigned int. The result is rounded towards zero. Signed-off-by: Bastian Koppelmann --- target-tricore/fpu_helper.c | 42 ++ target-tricore/helper.h | 1 + target-tricore/translate.c | 3 +++ 3 files

[Qemu-devel] RFC: QEMU RISC-V modular ISA decoding

Hi QEMU devs, hi risc-v-sw devs, I'm posting this cross mailing list since I'd like to get feedback from the both sides. Right now the RISC-V port for QEMU uses the classic decoding scheme of one function decoding the first opcode (and prefixes) and then branches to different functions for decodi

Re: [Qemu-devel] [sw-dev] RFC: QEMU RISC-V modular ISA decoding

On 07/25/2017 06:37 PM, Bruce Hoult wrote: > Do you have any good estimates for how much of the execution time is > typically spent in instruction decode? > > RISC-V qemu is twice as fast as ARM or Aarch64 qemu, so it's doing > something right! > > (I suspect it's probably mostly the lack of need

Re: [Qemu-devel] [sw-dev] RFC: QEMU RISC-V modular ISA decoding

ide to take might well work and satisfy > extensibility requirements, but it'll likely take a performance hit as > well. > > On Tue, Jul 25, 2017 at 6:04 AM, Bastian Koppelmann > wrote: >> Hi QEMU devs, hi risc-v-sw devs, >> >> I'm posting this cross maili

Re: [Qemu-devel] qemu-system-tricore: segfault when entering "x 0" on the monitor

On 07/28/2017 01:19 PM, Michael Tokarev wrote: > 27.07.2017 17:30, Eduardo Otubo wrote: >> Starting Qemu with "qemu-system-tricore -nographic -M tricore_testboard -S" >> and entering "x 0" at the monitor prompt leads to Segmentation fault. This >> happens >> because tricore_cpu_get_phys_page_debug

Re: [Qemu-devel] [PATCH v3 18/25] tricore: cpu: add CPU_RESOLVING_TYPE macro

would ensure that null-mchine usecase still works. > > Signed-off-by: Igor Mammedov Acked-by: Bastian Koppelmann Cheers, Bastian

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