Hi, this series implements the insns reported in [1], as well as ftou. Also I fixed two bugs in the insert insn which I came across during testing.
Cheers, Bastian [1] https://gitlab.com/qemu-project/qemu/-/issues/1667 v1 -> v2: - Removed useless deposits in crc_div() - Replaced final deposit() with extract() in helper_crcn() - Add trap if not feature_162 (CRCN) - Removed special case for NAN input (FTOU) - Clarified why we need arg < 0.0 special case (FTOU, FTOUZ) - Removed special case for f_arg being infinity (ftohp, hptof) - Clarified, why we need a special case for arg being NAN (ftohp, hptof) Bastian Koppelmann (11): tests/tcg/tricore: Bump cpu to tc37x target/tricore: Implement CRCN insn target/tricore: Correctly handle FPU RM from PSW target/tricore: Implement FTOU insn target/tricore: Clarify special case for FTOUZ insn target/tricore: Implement ftohp insn target/tricore: Implement hptof insn target/tricore: Fix RCPW/RRPW_INSERT insns for width = 0 target/tricore: Swap src and dst reg for RCRR_INSERT target/tricore: Replace cpu_*_code with translator_* target/tricore: Fix FTOUZ being ISA v1.3.1 up target/tricore/fpu_helper.c | 111 ++++++++++++++++++++++ target/tricore/helper.c | 19 +++- target/tricore/helper.h | 4 + target/tricore/op_helper.c | 63 ++++++++++++ target/tricore/translate.c | 56 +++++++++-- target/tricore/tricore-opcodes.h | 3 + tests/tcg/tricore/Makefile.softmmu-target | 6 +- tests/tcg/tricore/asm/macros.h | 24 +++++ tests/tcg/tricore/asm/test_crcn.S | 9 ++ tests/tcg/tricore/asm/test_ftohp.S | 14 +++ tests/tcg/tricore/asm/test_ftou.S | 12 +++ tests/tcg/tricore/asm/test_hptof.S | 12 +++ tests/tcg/tricore/asm/test_insert.S | 14 +++ 13 files changed, 334 insertions(+), 13 deletions(-) create mode 100644 tests/tcg/tricore/asm/test_crcn.S create mode 100644 tests/tcg/tricore/asm/test_ftohp.S create mode 100644 tests/tcg/tricore/asm/test_ftou.S create mode 100644 tests/tcg/tricore/asm/test_hptof.S -- 2.41.0
