; (aka 'unsigned int')
has no effect [-Wabsolute-value]
target-tricore/op_helper.c:1299:19: warning:
taking the absolute value of unsigned type 'uint32_t' (aka 'unsigned int')
has no effect [-Wabsolute-value]
Fix also the divisor which was taken from the wrong
RRPW_DEXTR used r1 for the low part and r2 for the high part. It should be the
other way round. This also fixes that the result of the first shift was not
saved in a temp and could overwrite registers that were needed for the second
shift.
Signed-off-by: Bastian Koppelmann
---
target-tricore
The TriCore documentation was wrong on how to calculate ovf bits for those two
instructions, which I confirmed with real hardware (TC1796 chip). An ovf
actually happens, if the result (without remainder) does not fit into 8/16 bits.
Signed-off-by: Bastian Koppelmann
---
target-tricore
Hi Stefan,
On 03/23/2015 03:41 PM, Bastian Koppelmann wrote:
[snip]
The code for dvinit.b and dvinit.h is not correctly calculating the
overflow bit, but I can't figure out why, since the documentation of
the real hardware seems to be wrong. I will take your patch for now,
so the warni
ffect [-Wabsolute-value]
target-tricore/op_helper.c:1299:19: warning:
taking the absolute value of unsigned type 'uint32_t' (aka 'unsigned int')
has no effect [-Wabsolute-value]
Fix also the divisor which was taken from the wrong register
(thanks to Peter Maydell for this
The TriCore documentation was wrong on how to calculate ovf bits for those two
instructions, which I confirmed with real hardware (TC1796 chip). An ovf
actually happens, if the result (without remainder) does not fit into 8/16 bits.
Signed-off-by: Bastian Koppelmann
---
target-tricore
dvinit_hu/bu for ISA v1.3 calculate the higher part of the result, that is
needed
for the overflow bits, after calculating the overflow bits.
Signed-off-by: Bastian Koppelmann
---
target-tricore/translate.c | 30 ++
1 file changed, 18 insertions(+), 12 deletions
or 2.3-rc1
--------
Bastian Koppelmann (3):
target-tricore: fix DVINIT_HU/BU calculating overflow before result
target-tricore: fix RRPW_DEXTR using wrong reg
target-tricore: properly fix dvinit_b/h_13
Stefan Weil (1):
target-tricore: Fix two helper
RRPW_DEXTR used r1 for the low part and r2 for the high part. It should be the
other way round. This also fixes that the result of the first shift was not
saved in a temp and could overwrite registers that were needed for the second
shift.
Signed-off-by: Bastian Koppelmann
---
target-tricore
Hi mjt,
On 03/21/2015 02:44 PM, Stefan Weil wrote:
With a mask value of 0x0040, the result will never be 1.
This fixes a Coverity warning.
Signed-off-by: Stefan Weil
---
target-tricore/op_helper.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target-tricore/op_help
On 03/25/2015 04:20 PM, Michael Tokarev wrote:
21.03.2015 16:44, Stefan Weil wrote:
With a mask value of 0x0040, the result will never be 1.
This fixes a Coverity warning.
Might be a bit risky if the whole thing wasn't a complete no-op.
I wonder maybe the whole this if statement should be
..for address calculation instead address registers.
Signed-off-by: Bastian Koppelmann
---
target-tricore/translate.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/target-tricore/translate.c b/target-tricore/translate.c
index bbcfee9..54a48cd 100644
--- a/target
On 03/27/2015 05:42 PM, Peter Maydell wrote:
This is the set of things I have on the list for "should ideally
get into rc2":
* AArch64 migration fixes
* VNC patches to fix CVEs
* recent exec.c changes broke ppc OSX/OpenBIOS boot
Anything else?
Hi Peter,
I have one more TriCore fix
(ht
e bugfixes
--------
Bastian Koppelmann (1):
target-tricore: fix CACHEA/I_POSTINC/PREINC using data register..
target-tricore/translate.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
--
2.3.4
..for address calculation instead address registers.
Signed-off-by: Bastian Koppelmann
---
target-tricore/translate.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/target-tricore/translate.c b/target-tricore/translate.c
index bbcfee9..54a48cd 100644
--- a/target
On 03/30/2015 06:34 PM, Andreas Färber wrote:
Hi Bastian,
Am 30.03.2015 um 13:46 schrieb Bastian Koppelmann:
Bastian Koppelmann (1):
target-tricore: fix CACHEA/I_POSTINC/PREINC using data register..
FYI git-format-patch has a --numbered option that forces [PULL 1/1].
Thanks. I&#x
** Changed in: qemu
Status: Confirmed => Fix Committed
--
You received this bug notification because you are a member of qemu-
devel-ml, which is subscribed to QEMU.
https://bugs.launchpad.net/bugs/1402802
Title:
target-tricore/translate.c:3812: possible bad expression ?
Status in QEMU
On 12/23/2014 10:24 PM, Peter Maydell wrote:
Add a missing ULL suffix to a 64 bit constant: this suppresses a
compiler warning from mingw32 gcc.
Signed-off-by: Peter Maydell
---
target-tricore/op_helper.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
Thanks, applied it to my trico
The documentation for the tcg-ops subfi, extr_i64_i32 and extr32_i64 was still
missing.
Signed-off-by: Bastian Koppelmann
---
tcg/README | 12
1 file changed, 12 insertions(+)
diff --git a/tcg/README b/tcg/README
index a550ff1..ba40023 100644
--- a/tcg/README
+++ b/tcg/README
Sorry ..., I did not use reply all ...
On 01/10/2015 07:37 PM, Richard Henderson wrote:
On 01/10/2015 08:51 AM, Bastian Koppelmann wrote:
The documentation for the tcg-ops subfi, extr_i64_i32 and extr32_i64 was still
missing.
No, there are no such tcg ops.
There are *functions* by these
l the immediate variants are also
documented by simply refering to the non immediate version. However I'm willing
to drop that.
Any comments?
Signed-off-by: Bastian Koppelmann
---
tcg/tcg-op.h | 477 ++-
1 file changed, 436 inserti
On 01/14/2015 03:36 PM, Lluís Vilanova wrote:
Bastian Koppelmann writes:
There is no overview, that shows all the frontend operation one can use, as
found on the wiki. Unfortunatly the wiki is out of date, so let's try to move
this documentation to the source files, which has the be
On 01/14/2015 04:55 PM, Thomas Huth wrote:
On Wed, 14 Jan 2015 16:36:26 +0100
Lluís Vilanova wrote:
...
Also, AFAIR it was decided to use gtk-doc instead of doxygen.
If there's a consensus about which source code documentation style
should be used for QEMU, could you (or somebody else) maybe
On 01/14/2015 03:51 PM, Bastian Koppelmann wrote:
There is no overview, that shows all the frontend operation one can use, as
found on the wiki. Unfortunatly the wiki is out of date, so let's try to move
this documentation to the source files, which has the benefit, that it is easy
to u
On 01/19/2015 03:21 PM, Peter Maydell wrote:
On 24 December 2014 at 00:03, Bastian Koppelmann
wrote:
On 12/23/2014 10:24 PM, Peter Maydell wrote:
Add a missing ULL suffix to a 64 bit constant: this suppresses a
compiler warning from mingw32 gcc.
Signed-off-by: Peter Maydell
---
target
Hi Markus,
On 01/20/2015 09:23 AM, Markus Armbruster wrote:
Coverity[*] points out:
*** CID 1264337: Logically dead code (DEADCODE)
/target-tricore/translate.c: 348 in gen_mtcr()
342 #define E(ADDRESS, REG, FEATURE) A(ADDRESS, REG, FEATURE)
343 static inline void gen_mt
64 bit mac instructions calculated the av bits after the saturation, which
resulted in a wrong PSW. This moves the av bit calculation before the
saturation.
Signed-off-by: Bastian Koppelmann
---
target-tricore/op_helper.c | 28
1 file changed, 16 insertions(+), 12
Hi,
this patchset only contains bugfixes, like the ones found by coverity, and some
minor corner cases in some instructions.
Cheers,
Bastian
Bastian Koppelmann (4):
target-tricore: Several translator and cpu model fixes
target-tricore: calculate av bits before saturation
target-tricore
ns for suov32 up into two functions
(suov32_pos, suov32_neg) for each case.
Signed-off-by: Bastian Koppelmann
---
target-tricore/op_helper.c | 41 ++---
1 file changed, 26 insertions(+), 15 deletions(-)
diff --git a/target-tricore/op_helper.c b/target-t
comment to avoid
the false positive in the future.
Reported-by: Markus Armbruster
Signed-off-by: Bastian Koppelmann
---
target-tricore/cpu.h | 1 +
target-tricore/translate.c | 3 ++-
2 files changed, 3 insertions(+), 1 deletion(-)
diff --git a/target-tricore/cpu.h b/target-tricore/cpu.h
Fix tc1796 cpu model using wrong ISA version.
Fix cond_add sometimes writing back wrong result.
Fix RCR_SEL and RCR_SELN using wrong registers for result and cond.
Signed-off-by: Bastian Koppelmann
---
target-tricore/cpu.c | 2 +-
target-tricore/op_helper.c | 1 +
target-tricore
Signed-off-by: Bastian Koppelmann
---
target-tricore/translate.c | 37 +
1 file changed, 37 insertions(+)
diff --git a/target-tricore/translate.c b/target-tricore/translate.c
index da8ecbc..4af31c2 100644
--- a/target-tricore/translate.c
+++ b/target-tricore
Signed-off-by: Bastian Koppelmann
---
target-tricore/translate.c | 276 +
1 file changed, 276 insertions(+)
diff --git a/target-tricore/translate.c b/target-tricore/translate.c
index def7f4a..da8ecbc 100644
--- a/target-tricore/translate.c
+++ b
Hi,
this is a rather short patchset, that only implements instructions of four
formats. There will be another patchset, which has a few bugfixes.
Cheers,
Bastian
Bastian Koppelmann (4):
target-tricore: target-tricore: Add instructions of RR1 opcode format,
that have 0x93 as first opcode
number.
* dvadj: divide-adjust the result after dvstep instructions.
* dvstep: divide a reg by a divisor, producing 8-bits of quotient at a time.
OPCM_32_RRR_FLOAT -> OPCM_32_RRR_DIVIDE
Signed-off-by: Bastian Koppelmann
---
Richard,
the dvadj instruction gave a lot of headaches. The pseudoc
On 01/14/2015 03:51 PM, Bastian Koppelmann wrote:
There is no overview, that shows all the frontend operation one can use, as
found on the wiki. Unfortunatly the wiki is out of date, so let's try to move
this documentation to the source files, which has the benefit, that it is easy
to u
Signed-off-by: Bastian Koppelmann
---
target-tricore/translate.c | 63 ++
1 file changed, 63 insertions(+)
diff --git a/target-tricore/translate.c b/target-tricore/translate.c
index 4af31c2..73d8d7d 100644
--- a/target-tricore/translate.c
+++ b/target
On 01/21/2015 06:16 PM, Richard Henderson wrote:
On 01/21/2015 10:04 AM, Bastian Koppelmann wrote:
+case OPC2_32_RR2_MUL_32:
+gen_mul_i32s(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
+break;
+case OPC2_32_RR2_MUL_64:
+gen_mul_i64s(cpu_gpr_d[r3], cpu_gpr_d[r3+1
Hi Alex,
I'm not really happy with that. A brief look into the instruction manual
shows, that modal instructions have different outputs depending on the
addressing mode. On the long run it would be better to implement this.
That said I'm not an expert on s390x and there is a reason we're only
xtint(uint32_t parm)
kvm_s390_service_interrupt(parm);
} else {
S390CPU *dummy_cpu = s390_cpu_addr2state(0);
-CPUS390XState *env = &dummy_cpu->env;
-env->psw.addr += 4;
cpu_inject_ext(dummy_cpu, EXT_SERVICE, parm, 0);
}
}
Revie
On 11/04/2014 08:19 PM, Alexander Graf wrote:
+static ExitStatus op_sam(DisasContext *s, DisasOps *o)
+{
+int sam = s->insn->data;
+TCGv_i64 tsam = tcg_const_i64(sam);
+
+/* Overwrite PSW_MASK_64 and PSW_MASK_32 */
+tcg_gen_deposit_i64(psw_mask, psw_mask, tsam, 31, 2);
+
+tcg
tic ExitStatus op_sar(DisasContext *s, DisasOps *o)
{
int r1 = get_field(s->fields, r1);
Reviewed-by: Bastian Koppelmann
, when instructions are available.
Thanks,
Bastian
Bastian Koppelmann (4):
target-tricore: Make TRICORE_FEATURES implying others.
target-tricore: Add instructions of RCPW, RCRR and RCRW opcode format
target-tricore: Add instructions of RLC opcode format
target-tricore: Add instructions of
Add instructions of RLC opcode format.
Add helper psw_write/read.
Add microcode generator gen_mtcr/mfcr, which loads/stores a value to a core
special function register, which are defined in csfr.def
Signed-off-by: Bastian Koppelmann
---
target-tricore/csfr.def | 124
Since all the TriCore instructionsets are subsets of each other (1.3 C 1.3.1 C
1.6),
make the features implying each other, e.g 1.6 also has 1.3.1 and 1.3. This way
we only need to check our features for the instructionset, where a instruction
was first introduced.
Signed-off-by: Bastian
Add instructions of RCPW, RCRR and RCRW opcode format.
Add microcode generator function gen_insert.
Signed-off-by: Bastian Koppelmann
---
target-tricore/translate.c | 132 +++--
1 file changed, 129 insertions(+), 3 deletions(-)
diff --git a/target
ned-off-by: Bastian Koppelmann
---
target-tricore/helper.h | 8 +
target-tricore/op_helper.c | 192 +++
target-tricore/translate.c | 493 +++
target-tricore/tricore-opcodes.h | 3 +-
4 files changed, 695 insertions(+), 1 delet
happy with that change, since this was really confusing, if
you were writing a guest, that uses the tcg-fronted.
Reviewed-by: Bastian Koppelmann
Cheers,
Bastian
happy with that change, since these functions make it
really clear what is happening.
Reviewed-by: Bastian Koppelmann
Cheers,
Bastian
On 11/13/2014 03:06 PM, Bastian Koppelmann wrote:
Hi,
this patch depends on the previous TriCore patches
(https://patchwork.ozlabs.org/patch/405459/) and will hopefully end up in 2.3
QEMU.
Other than adding the RCPW, RCRR, RCRW, RLC and RCR instructions, it cleans up
how ISA versions in the
, when instructions are available.
Thanks,
Bastian
v1 -> v2:
- Fixed obvious style errors, given by checkpatch.
Bastian Koppelmann (4):
target-tricore: Make TRICORE_FEATURES implying others.
target-tricore: Add instructions of RCPW, RCRR and RCRW opcode format
target-tricore:
Since all the TriCore instructionsets are subsets of each other (1.3 C 1.3.1 C
1.6),
make the features implying each other, e.g 1.6 also has 1.3.1 and 1.3. This way
we only need to check our features for the instructionset, where a instruction
was first introduced.
Signed-off-by: Bastian
Add instructions of RCPW, RCRR and RCRW opcode format.
Add microcode generator function gen_insert.
Signed-off-by: Bastian Koppelmann
---
target-tricore/translate.c | 132 +++--
1 file changed, 129 insertions(+), 3 deletions(-)
diff --git a/target
Add instructions of RLC opcode format.
Add helper psw_write/read.
Add microcode generator gen_mtcr/mfcr, which loads/stores a value to a core
special function register, which are defined in csfr.def
Signed-off-by: Bastian Koppelmann
---
target-tricore/csfr.def | 124
ned-off-by: Bastian Koppelmann
---
target-tricore/helper.h | 8 +
target-tricore/op_helper.c | 192 +++
target-tricore/translate.c | 493 +++
target-tricore/tricore-opcodes.h | 3 +-
4 files changed, 695 insertions(+), 1 delet
On 11/11/2014 04:24 PM, Richard Henderson wrote:
+static void tcg_gen_op_begin(TCGContext *ctx, TCGOpcode opc, int args)
+{
+int oi = ctx->gen_next_op_idx;
+int ni = oi + 1;
+int pi = oi - 1;
+
+tcg_debug_assert(oi < OPC_BUF_SIZE);
+ctx->gen_last_op_idx = oi;
+ctx->gen_ne
+
3 files changed, 32 insertions(+), 11 deletions(-)
Reviewed-by: Bastian Koppelmann
On 11/11/2014 04:24 PM, Richard Henderson wrote:
Rather reserving space in the op stream for optimization,
let the optimizer add ops as necessary.
Signed-off-by: Richard Henderson
---
tcg/optimize.c | 57 +++--
tcg/tcg-op.c | 16
();
-break;
Why do you remove the TODO notice for INDEX_op_discard/set_label? Is TCI
no longer maintained?
case INDEX_op_call:
t0 = tci_read_ri(&tb_ptr);
#if TCG_TARGET_REG_BITS == 32
Other than that,
Reviewed-by: Bastian Koppelmann
Cheers,
Bastian
insertions(+), 2269 deletions(-)
create mode 100644 tcg/tcg-op.c
Reviewed-by: Bastian Koppelmann
Cheers,
Bastian
, 207 insertions(+), 242 deletions(-)
Reviewed-by: Bastian Koppelmann
Cheers,
Bastian
On 11/11/2014 04:24 PM, Richard Henderson wrote:
Richard Henderson (8):
tcg: Move some opcode generation functions out of line
tcg: Reduce ifdefs in tcg-op.c
tcg: Move emit of INDEX_op_end into gen_tb_end
tcg: Introduce tcg_op_buf_count and tcg_op_buf_full
tcg: Put opcodes in a li
On 11/14/2014 01:39 PM, Richard Henderson wrote:
On 11/13/2014 06:12 PM, Bastian Koppelmann wrote:
+tcg_gen_ext_i32_i64(t3, r3);
+tcg_gen_concat_i32_i64(t2, r2_low, r2_high);
+/* extend the sign for r2 to high 64 bits */
+tcg_gen_sari_i64(t4, t2, 63);
+tcg_gen_ext_i32_i64
uov.
Bastian Koppelmann (4):
target-tricore: Make TRICORE_FEATURES implying others.
target-tricore: Add instructions of RCPW, RCRR and RCRW opcode format
target-tricore: Add instructions of RLC opcode format
target-tricore: Add instructions of RCR opcode format
target-tricore/cp
Add instructions of RLC opcode format.
Add helper psw_write/read.
Add microcode generator gen_mtcr/mfcr, which loads/stores a value to a core
special function register, which are defined in csfr.def
Signed-off-by: Bastian Koppelmann
Reviewed-by: Richard Henderson
---
target-tricore/csfr.def
ned-off-by: Bastian Koppelmann
---
v2 -> v3:
- madd/msub and maddu/msubu now use 64 bit arithmetic instead of 128 bit.
- helper madd64_ssov/suov and msub64_ssov/suov now use 64 bit arithmetic
for the mul.
- cleaned up double setting of PSW_USB_V/SV in helper_msub64_suov.
target-t
Since all the TriCore instructionsets are subsets of each other (1.3 C 1.3.1 C
1.6),
make the features implying each other, e.g 1.6 also has 1.3.1 and 1.3. This way
we only need to check our features for the instructionset, where a instruction
was first introduced.
Signed-off-by: Bastian
Add instructions of RCPW, RCRR and RCRW opcode format.
Add microcode generator function gen_insert.
Signed-off-by: Bastian Koppelmann
Reviewed-by: Richard Henderson
---
target-tricore/translate.c | 132 +++--
1 file changed, 129 insertions(+), 3
Since all the TriCore instructionsets are subsets of each other (1.3 C 1.3.1 C
1.6),
make the features implying each other, e.g 1.6 also has 1.3.1 and 1.3. This way
we only need to check our features for the instructionset, where a instruction
was first introduced.
Signed-off-by: Bastian
, when instructions are available.
Thanks,
Bastian
v3 -> v4:
- helper madd64_ssov/suov and msub64_ssov/suov now use 64 bit arithmetic
for the add. (Thanks alot, Richard!)
Bastian Koppelmann (4):
target-tricore: Make TRICORE_FEATURES implying others.
target-tricore: Add instructions
ned-off-by: Bastian Koppelmann
---
v3 -> v4:
- helper madd64_ssov/suov and msub64_ssov/suov now use 64 bit arithmetic
for the add. (Thanks alot, Richard!)
target-tricore/helper.h | 8 +
target-tricore/op_helper.c | 168 ++
target-tricore/translate.c
Add instructions of RCPW, RCRR and RCRW opcode format.
Add microcode generator function gen_insert.
Signed-off-by: Bastian Koppelmann
Reviewed-by: Richard Henderson
---
target-tricore/translate.c | 132 +++--
1 file changed, 129 insertions(+), 3
Add instructions of RLC opcode format.
Add helper psw_write/read.
Add microcode generator gen_mtcr/mfcr, which loads/stores a value to a core
special function register, which are defined in csfr.def
Signed-off-by: Bastian Koppelmann
Reviewed-by: Richard Henderson
---
target-tricore/csfr.def
, RCPW, RCRR, RCR, RLC and RCR insn added
Bastian Koppelmann (9):
target-tricore: Add instructions of BOL opcode format
target-tricore: Add instructions of BRC opcode format
target-tricore: Add instructions of BRN opcode format
Add instructions of BRR opcode format.
Add MASK_OP_BRR_DISP15_SEXT.
Signed-off-by: Bastian Koppelmann
Reviewed-by: Richard Henderson
---
target-tricore/translate.c | 90 +++-
target-tricore/tricore-opcodes.h | 1 +
2 files changed, 89 insertions(+), 2
Add instructions of BOL opcode format.
Signed-off-by: Bastian Koppelmann
Reviewed-by: Richard Henderson
---
target-tricore/translate.c | 48
target-tricore/tricore-opcodes.h | 4 +++-
2 files changed, 51 insertions(+), 1 deletion(-)
diff --git a
Add instructions of BRC opcode format.
Fixed OP2_BRC_JGE -> OP2_32_BRC_JGE
Signed-off-by: Bastian Koppelmann
Reviewed-by: Richard Henderson
---
target-tricore/translate.c | 53 +++-
target-tricore/tricore-opcodes.h | 6 +++--
2 files changed,
Add instructions of RCPW, RCRR and RCRW opcode format.
Add microcode generator function gen_insert.
Signed-off-by: Bastian Koppelmann
Reviewed-by: Richard Henderson
---
target-tricore/translate.c | 132 +++--
1 file changed, 129 insertions(+), 3
.
* gen_sh_cond, which shifts left a reg by one and writes the result of cond
into the lsb.
* gen_accumulating_cond, which ands/ors/xors the result of cond of the lsbs
with the lsb of the result.
* gen_eqany_bi/hi, which checks ever byte/hword on equality.
Signed-off-by: Bastian
Add instructions of BRN opcode format.
Add MASK_OP_BRN_DISP15_SEXT.
Signed-off-by: Bastian Koppelmann
Reviewed-by: Richard Henderson
---
target-tricore/translate.c | 26 ++
target-tricore/tricore-opcodes.h | 1 +
2 files changed, 27 insertions(+)
diff --git a
Add instructions of RLC opcode format.
Add helper psw_write/read.
Add microcode generator gen_mtcr/mfcr, which loads/stores a value to a core
special function register, which are defined in csfr.def
Signed-off-by: Bastian Koppelmann
Reviewed-by: Richard Henderson
---
target-tricore/csfr.def
ned-off-by: Bastian Koppelmann
Reviewed-by: Richard Henderson
---
target-tricore/helper.h | 8 +
target-tricore/op_helper.c | 168 ++
target-tricore/translate.c | 479 +++
target-tricore/tricore-opcodes.h | 3 +-
4 files chan
Since all the TriCore instructionsets are subsets of each other (1.3 C 1.3.1 C
1.6),
make the features implying each other, e.g 1.6 also has 1.3.1 and 1.3. This way
we only need to check our features for the instructionset, where a instruction
was first introduced.
Signed-off-by: Bastian
On 12/12/2014 10:25 AM, Alex Züpke wrote:
Fixes offset masking for BOL opcodes and a typo (LONF -> LONG)
Signed-off-by: Alex Zuepke
Hi Alex,
good catch. I wonder how that slipped through my testsuit. However you
mail seems to be malformed. The patch went somehow into your signature.
Don't
On 12/12/2014 11:25 AM, Alex Züpke wrote:
Add the missing 64-bit "MOV Ex, simm16" variant in RLC format.
Signed-off-by: Alex Zuepke
Again malformed as in your other patch. Other than that, it looks good.
Cheers,
Bastian
On 12/12/2014 02:10 PM, Alex Zuepke wrote:
Signed-off-by: Alex Zuepke
---
target-tricore/tricore-opcodes.h |2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
Reviewed-by: Bastian Koppelmann
On 12/12/2014 02:10 PM, Alex Zuepke wrote:
Signed-off-by: Alex Zuepke
---
target-tricore/translate.c |4 ++--
target-tricore/tricore-opcodes.h |2 +-
2 files changed, 3 insertions(+), 3 deletions(-)
Reviewed-by: Bastian Koppelmann
On 12/12/2014 02:10 PM, Alex Zuepke wrote:
Hi Bastian,
my previous patches again, I hope they are well-formed now:
1. fix the offset masking in BOL format
2. fix a typo in BOL format
3. add the missing 64-bit "MOV Ex, simm16" variant in RLC format
4. pretty-print register dump
Best regards
Ale
= 0xbb,
OPC1_32_RLC_MOV_H= 0x7b,
OPC1_32_RLC_MOVH_A = 0x91,
Looks good to me anyway.
Reviewed-by: Bastian Koppelmann
On 12/12/2014 02:10 PM, Alex Zuepke wrote:
Signed-off-by: Alex Zuepke
---
target-tricore/translate.c | 16 +++-
1 file changed, 11 insertions(+), 5 deletions(-)
diff --git a/target-tricore/translate.c b/target-tricore/translate.c
index e3eeedb..d1b845b 100644
--- a/target-tric
: Bastian Koppelmann
---
target-tricore/helper.h| 13 ++
target-tricore/op_helper.c | 111 +
target-tricore/translate.c | 96 +++
3 files changed, 220 insertions(+)
diff --git a/target-tricore/helper.h b/target
Fix gen_mtcr using wrong register.
Fix gen_mtcr/mfcr using sign extended offsets.
Fix B format insn using not sign extendend offsets.
Signed-off-by: Bastian Koppelmann
---
target-tricore/translate.c | 6 --
target-tricore/tricore-opcodes.h | 2 ++
2 files changed, 6 insertions(+), 2
Add instructions of RR opcode format, that have 0x1 as the first opcode.
Signed-off-by: Bastian Koppelmann
---
target-tricore/translate.c | 97 ++
1 file changed, 97 insertions(+)
diff --git a/target-tricore/translate.c b/target-tricore/translate.c
into four patches,
seperated by the first opcode all insn of one patch have. I also added missed
1.6 insns and fixed some
minor errors. The last patch adds the first half of the RR1 insn.
Cheers,
Bastian
Bastian Koppelmann (8):
target-tricore: Change SSOV/SUOV makro name to SSOV32/SUOV32
target
arithmeticly.
Signed-off-by: Bastian Koppelmann
---
target-tricore/helper.h| 12
target-tricore/op_helper.c | 160 +
target-tricore/translate.c | 78 ++
3 files changed, 250 insertions(+)
diff --git a/target-tricore/helper.h b
,
where the quotient result is guaranteed to fit into 16
bit.
OPCM_32_RR_FLOAT -> OPCM_32_RR_DIVIDE.
Signed-off-by: Bastian Koppelmann
---
target-tricore/helper.h | 11 +++
target-tricore/op_helper.c | 195 +++
target-tric
Those makros are exclusively used for 32 bit arithmetics and won't work for 16
bit with two halfwords.
So lets get rid of the len parameter and make them always use 32 bit.
Signed-off-by: Bastian Koppelmann
---
target-tricore/op_helper.c | 34 +-
1 file ch
Some of the 1.6 ISA instructions were still missing. So let's add them.
Signed-off-by: Bastian Koppelmann
---
target-tricore/translate.c | 49 +++-
target-tricore/tricore-opcodes.h | 6 +
2 files changed, 54 insertions(+), 1 deletion(-)
diff
* gen_abs: Compute absolute value for a 32 bit integer.
* gen_cond_w: Compares two 32 bit values on cond and sets result either
zero or all bits one.
OPC2_32_RR_MIN switched with OPC2_32_RR_MIN_U.
Signed-off-by: Bastian Koppelmann
---
target-tricore/helper.h | 32 +++
target
Absolutly correct. The mask should be 0x7f. I will fix that asap.
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https://bugs.launchpad.net/bugs/1402802
Title:
target-tricore/translate.c:3812: possible bad expression ?
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