Re: [Qemu-devel] [PATCH 2/4] target-tricore: Add instructions of RR2 opcode format

[Bastian Koppelmann]

On 01/21/2015 06:16 PM, Richard Henderson wrote:
On 01/21/2015 10:04 AM, Bastian Koppelmann wrote:
+    case OPC2_32_RR2_MUL_32:
+        gen_mul_i32s(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
+        break;
+    case OPC2_32_RR2_MUL_64:
+        gen_mul_i64s(cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r1],
+                     cpu_gpr_d[r2]);
+        break;
What happend to flags computation?
If you are talking about the PSW flags, they are computed in their 
respective functions: gen_mul_i32s and
gen_mul_i64s.
Cheers,
Bastian

r~