Z_4K(1 << 12)
> +#define SZ_64K (1 << 16)
> +#define SZ_2M(1 << 21)
> +#define SZ_1G (1 << 30)
>
> typedef uint8_t u8;
> typedef int8_t s8;
>
Reviewed-by: Eric Auger
Eric
RITYR + i);
> +
> + writel(GICD_INT_EN_SET_SGI, dist + GICD_ISENABLER + 0);
> + writel(GICD_ENABLE, dist + GICD_CTLR);
> +
> + writel(GICC_INT_PRI_THRESHOLD, cpu_base + GICC_PMR);
> + writel(GICC_ENABLE, cpu_base + GICC_CTLR);
> +}
> diff --git a/lib/arm64/asm/gic-v2.h b/lib/arm64/asm/gic-v2.h
> new file mode 100644
> index ..52226624a209
> --- /dev/null
> +++ b/lib/arm64/asm/gic-v2.h
> @@ -0,0 +1 @@
> +#include "../../arm/asm/gic-v2.h"
> diff --git a/lib/arm64/asm/gic.h b/lib/arm64/asm/gic.h
> new file mode 100644
> index ..e5eb302a31b4
> --- /dev/null
> +++ b/lib/arm64/asm/gic.h
> @@ -0,0 +1 @@
> +#include "../../arm/asm/gic.h"
>
Reviewed-by: Eric Auger
Eric
Hi Drew,
On 14/11/2016 22:08, Andrew Jones wrote:
> By adding support for launching with gicv3 we can break the 8 vcpu
> limit. This patch adds support to smp code and also selects the
> vgic model corresponding to the host. The vgic model may also be
> manually selected by adding e.g. -machine gi
/arm64/asm/sysreg.h
> @@ -0,0 +1,44 @@
> +/*
> + * Ripped off from arch/arm64/include/asm/sysreg.h
> + *
> + * Copyright (C) 2016, Red Hat Inc, Andrew Jones
> + *
> + * This work is licensed under the terms of the GNU LGPL, version 2.
> + */
> +#ifndef _ASMARM64_SYSREG_H_
> +#define _ASMARM64_SYSREG_H_
> +
> +#define sys_reg(op0, op1, crn, crm, op2) \
> + op0)&3)<<19)|((op1)<<16)|((crn)<<12)|((crm)<<8)|((op2)<<5))
> +
> +#ifdef __ASSEMBLY__
> + .irp
> num,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30
> + .equ.L__reg_num_x\num, \num
> + .endr
> + .equ.L__reg_num_xzr, 31
> +
> + .macro mrs_s, rt, sreg
> + .inst 0xd520|(\sreg)|(.L__reg_num_\rt)
> + .endm
> +
> + .macro msr_s, sreg, rt
> + .inst 0xd500|(\sreg)|(.L__reg_num_\rt)
> + .endm
> +#else
> +asm(
> +".irp
> num,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30\n"
> +".equ.L__reg_num_x\\num, \\num\n"
> +".endr\n"
> +".equ.L__reg_num_xzr, 31\n"
> +"\n"
> +".macro mrs_s, rt, sreg\n"
> +".inst 0xd520|(\\sreg)|(.L__reg_num_\\rt)\n"
> +".endm\n"
> +"\n"
> +".macro msr_s, sreg, rt\n"
> +".inst 0xd500|(\\sreg)|(.L__reg_num_\\rt)\n"
> +".endm\n"
> +);
> +#endif
> +
> +#endif /* _ASMARM64_SYSREG_H_ */
>
Reviewed-by: Eric Auger
Eric
Hi Drew,
On 14/11/2016 22:08, Andrew Jones wrote:
> Signed-off-by: Andrew Jones
>
> ---
> v6: move most gicv2/gicv3 wrappers to common code [Alex]
> v5:
> - fix copy+paste error in gicv3_write_eoir [drew]
> - use modern register names [Andre]
> v4:
> - heavily comment gicv3_ipi_send_tlist() [
4 @@ int main(int argc, char **argv)
> report_prefix_pop();
>
> } else if (strcmp(argv[1], "ipi") == 0) {
> + int off, i = 1;
> + long val;
>
> report_prefix_push(argv[1]);
> nr_cpu_check(2);
Hi,
On 23/11/2016 11:09, Alex Bennée wrote:
>
> Andrew Jones writes:
>
>> Andre, Alex, Eric, anybody,
>>
>> Any more comments on this? If not, I'll send a pull request
>> to Radim and Paolo to finally get this merged.
>
> Looks good to me. I successfully re-based my TCG tests on top and they
>
Hi Andre,
On 18/11/2016 14:06, Andrew Jones wrote:
> Hi Andre,
>
> I'm so pleased to see this series. Thank you!
>
> On Thu, Nov 17, 2016 at 05:57:49PM +, Andre Przywara wrote:
>> This adds an MMIO subtest to the GIC test.
>> It accesses some generic GICv2 registers and does some sanity test
On 23/11/2016 14:01, Andrew Jones wrote:
> On Wed, Nov 23, 2016 at 12:28:34PM +0100, Auger Eric wrote:
>> Hi,
>>
>> On 14/11/2016 22:08, Andrew Jones wrote:
>>> Allow user to select who sends ipis and with which irq,
>>> rather than just always sending i
Hi Andre,
On 23/11/2016 14:24, Auger Eric wrote:
> Hi,
>
> On 18/11/2016 15:20, Andrew Jones wrote:
>> On Thu, Nov 17, 2016 at 05:57:51PM +, Andre Przywara wrote:
>>> Some tests for the ITARGETS registers.
>>> Bits corresponding to non-existent CPUs must be
Hi Andre,
On 18/11/2016 15:02, Andrew Jones wrote:
> On Thu, Nov 17, 2016 at 05:57:50PM +, Andre Przywara wrote:
>> Some tests for the IPRIORITY registers. The significant number of bits
>> is IMPLEMENTATION DEFINED, but should be the same for every IRQ.
>> Also these registers must be byte-acc
Hi,
On 18/11/2016 15:20, Andrew Jones wrote:
> On Thu, Nov 17, 2016 at 05:57:51PM +, Andre Przywara wrote:
>> Some tests for the ITARGETS registers.
>> Bits corresponding to non-existent CPUs must be RAZ/WI.
>> These registers must be byte-accessible, also check that accesses beyond
>> the imp
Hi,
On 18/11/2016 15:41, Andrew Jones wrote:
> On Thu, Nov 17, 2016 at 05:57:52PM +, Andre Przywara wrote:
>> Add a simple test for the GICv3 TYPER test, which does only one basic
>> check to ensure we have actually enough interrupt IDs if we support
>> LPIs.
>> Allow a GICv3 guest to do the c
Hi Andre,
On 23/11/2016 15:13, Andre Przywara wrote:
> Hi Eric,
>
> thanks for having such a close look (as always!).
>
> On 23/11/16 13:51, Auger Eric wrote:
>> Hi Andre,
>>
>> On 23/11/2016 14:24, Auger Eric wrote:
>>> Hi,
>>>
>>>
Hi Drew,
On 23/11/2016 17:54, Andrew Jones wrote:
> Reviewed-by: Alex Bennée
> Reviewed-by: Eric Auger
> Signed-off-by: Andrew Jones
>
> ---
> v7: split lib/arm/gic.c into gic-v2/3.c [Eric]
> v6:
> - added comments [Alex]
> - added stride parameter to gicv3_set_redist_base [Andre]
> - redis
Hi Drew,
On 23/11/2016 17:54, Andrew Jones wrote:
> Signed-off-by: Andrew Jones
>
> ---
> v7:
> - add common ipi_send_single/mask (replacing ipi_send).
>Note, the arg order irq,cpu got swapped. [Eric]
> - comment rewording [Eric]
> - make enable_defaults a common op [Eric]
> - gic_enable
Hi,
On 23/11/2016 17:54, Andrew Jones wrote:
> Allow user to select who sends ipis and with which irq,
> rather than just always sending irq=0 from cpu0.
>
> Signed-off-by: Andrew Jones
Reviewed-by: Eric Auger
Tested-by: Eric Auger
Eric
>
> ---
> v7: cleanup cm
Hi Drew,
On 24/11/2016 15:11, Andrew Jones wrote:
> On Thu, Nov 24, 2016 at 10:57:01AM +0100, Auger Eric wrote:
>> Hi,
>>
>> On 23/11/2016 17:54, Andrew Jones wrote:
>>> Allow user to select who sends ipis and with which irq,
>>> rather than just always send
Hi Vijay,
On 23/11/2016 13:39, vijay.kil...@gmail.com wrote:
> From: Vijaya Kumar K
>
> This temporary patch adds kernel API definitions. Use proper header update
> procedure after these features are released.
Did you send the complete v6 series? I only see 1/4 and 4/4 of this v6
(https://lists
Hi Vijay, Christoffer,
On 23/11/2016 13:39, vijay.kil...@gmail.com wrote:
> From: Vijaya Kumar K
>
> This series introduces support for GICv3 live migration with
> new VGIC implementation in 4.7-rc3 kernel.
> In this series, patch 1 of the previous implementation
> are ported.
> https://lists.no
Hi Andre, Drew,
On 06/12/2016 10:32, Andre Przywara wrote:
> Hi,
>
> On 06/12/16 09:29, Andrew Jones wrote:
>> On Mon, Dec 05, 2016 at 10:46:36PM +0100, Eric Auger wrote:
>>> Add a new cpu_count field in gicv3_data indicating the
>>> number of redistributors. This will be useful for enumeration
>
Hi Markus,
On 12/09/2016 14:45, Markus Armbruster wrote:
> Eric Auger writes:
>
>> This patch converts VFIO PCI to realize function.
>>
>> Also original initfn errors now are propagated using QEMU
>> error objects. All errors are formatted with the same pattern:
>> "vfio: %s: the error descripti
Hi Markus,
On 12/09/2016 14:51, Markus Armbruster wrote:
> Eric Auger writes:
>
>> Let's expand the usage of QEMU Error objects to vfio_populate_device.
>>
>> Signed-off-by: Eric Auger
>> ---
>> hw/vfio/pci.c | 45 -
>> 1 file changed, 20 insertions(
Hi Markus,
On 12/09/2016 14:58, Markus Armbruster wrote:
> Eric Auger writes:
>
>> Let's expand the usage of QEMU Error objects to vfio_msix_early_setup.
>>
>> Signed-off-by: Eric Auger
>> ---
>> hw/vfio/pci.c | 28
>> 1 file changed, 16 insertions(+), 12 deletions
Hi Markus,
On 12/09/2016 17:50, Markus Armbruster wrote:
> Auger Eric writes:
>
>> Hi Markus,
>>
>> On 12/09/2016 14:51, Markus Armbruster wrote:
>>> Eric Auger writes:
>>>
>>>> Let's expand the usage of QEMU Error objects t
Hi,
On 12/09/2016 18:17, Alex Williamson wrote:
> On Mon, 12 Sep 2016 16:00:18 +0200
> Auger Eric wrote:
>
>> Hi Markus,
>>
>> On 12/09/2016 14:45, Markus Armbruster wrote:
>>> Eric Auger writes:
>>>
>>>> This patch converts VFIO PCI t
Hi,
On 12/09/2016 22:05, Alex Williamson wrote:
> On Mon, 12 Sep 2016 21:39:22 +0200
> Auger Eric wrote:
>
>> Hi,
>> On 12/09/2016 18:17, Alex Williamson wrote:
>>> On Mon, 12 Sep 2016 16:00:18 +0200
>>> Auger Eric wrote:
>>>
>>>>
Hi Markus,
On 13/09/2016 08:25, Markus Armbruster wrote:
> Alex Williamson writes:
>
>> On Mon, 12 Sep 2016 16:00:18 +0200
>> Auger Eric wrote:
>>
>>> Hi Markus,
>>>
>>> On 12/09/2016 14:45, Markus Armbruster wrote:
>>>> Eric Auger
Hi Rick,
On 21/10/2016 03:22, Rick Song wrote:
> The platform device class has become abstract. This
> patch introduces a hisilicon hnsvf device that derives
> from it.
in https://lists.gnu.org/archive/html/qemu-devel/2016-08/msg03401.html
we discussed the relevance to get the platform device non
Hi,
On 21/10/2016 03:22, Rick Song wrote:
> This patch allows the instantiation of the vfio-hisi-hnsvf device
> from the QEMU command line (-device vfio-hisi-hnsvf,host="").
> A specialized device tree node is created for the guest, containing
> compat, dma-coherent, reg and interrupts properties.
Hi,
On 16/11/2016 21:46, Kirti Wankhede wrote:
> Updated vfio_pci.c file to use vfio_set_irqs_validate_and_prepare()
>
> Signed-off-by: Kirti Wankhede
> Signed-off-by: Neo Jia
> Change-Id: I9f3daba89d8dba5cb5b01a8cff420412f30686c7
> ---
> drivers/vfio/pci/vfio_pci.c | 34 +++---
Hi,
On 16/11/2016 21:46, Kirti Wankhede wrote:
> Vendor driver using mediated device framework would use same mechnism to
> validate and prepare IRQs. Introducing this function to reduce code
> replication in multiple drivers.
>
> Signed-off-by: Kirti Wankhede
> Signed-off-by: Neo Jia
> Change-
Hi,
On 16/11/2016 21:46, Kirti Wankhede wrote:
> Updated vfio_platform_common.c file to use
> vfio_set_irqs_validate_and_prepare()
>
> Signed-off-by: Kirti Wankhede
> Signed-off-by: Neo Jia
> Change-Id: Id87cd6b78ae901610b39bf957974baa6f40cd7b0
> ---
> drivers/vfio/platform/vfio_platform_commo
vdev->region[i].subtype);
> + cap_type.type = vdev->region[i].type;
> + cap_type.subtype = vdev->region[i].subtype;
> +
> + ret = vfio_info_add_capability(&caps,
> + VFIO_REGION_INFO_CAP_TYPE,
> + &cap_type);
> if (ret)
> return ret;
> +
nit: spare empty line
Reviewed-by: Eric Auger
Eric
> + }
> }
>
> if (caps.size) {
>
ize, u16 id, u16 version);
> extern void vfio_info_cap_shift(struct vfio_info_cap *caps, size_t offset);
>
> +extern int vfio_info_add_capability(struct vfio_info_cap *caps,
> + int cap_type_id, void *cap_type);
> +
> struct pci_dev;
> #ifdef CONFIG_EEH
> extern void vfio_spapr_pci_eeh_open(struct pci_dev *pdev);
>
Reviewed-by: Eric Auger
Eric
kfree(group);
> + /*
> + * Group ownership provides privilege, if the group
> + * list is empty, the domain goes away. If it's the
> + * last domain, then all the mappings go away too.
> + */
> + if (list_empty(&domain->group_list)) {
> + if (list_is_singular(&iommu->domain_list))
> + vfio_iommu_unmap_unpin_all(iommu);
> + iommu_domain_free(domain->domain);
> + list_del(&domain->next);
> + kfree(domain);
> }
> + goto done;
> }
>
> done:
>
Reviewed-by: Eric Auger
Eric
nd noticed that later :-(
Anyway I needed (and still need) to look at it.
Thanks
Eric
>
> Thanks,
> Kirti
>
> On 11/21/2016 4:59 PM, Auger Eric wrote:
>> Hi,
>> On 16/11/2016 21:46, Kirti Wankhede wrote:
>>> Add find_iommu_group()
>>>
>>>
Hi Fam,
On 22/02/2017 03:18, Fam Zheng wrote:
> Python is no longer installed implicitly, but the QEMU build system
> requires it. List it in PACKAGES.
>
> Reported-by: Auger Eric
> Signed-off-by: Fam Zheng
Tested-by: Eric Auger
Thanks!
Eric
> ---
> tests/docker/dock
Hi Stephan,
On 22/02/2017 17:37, Stefan Hajnoczi wrote:
> v2:
> * Avoid early region cache initialization in virtio_load() with wrong ring
>addresses for VIRTIO-1 in Patch 2 [Cornelia]
>
> Bug fixes for the recently added memory region cache in virtio. This series
> fixes live migration, se
Hi,
On 17/02/2017 07:31, vijay.kil...@gmail.com wrote:
> From: Vijaya Kumar K
>
> This actually implements pre_save and post_load methods for in-kernel
> vGICv3.
>
> Signed-off-by: Pavel Fedin
> Signed-off-by: Peter Maydell
I noticed some saved/restored registers are not really emulated on
ke
Hi Peter,
On 23/02/2017 19:35, Peter Maydell wrote:
> On 23 February 2017 at 11:51, wrote:
>> From: Vijaya Kumar K
>>
>> This temporary patch adds kernel API definitions.
>> Use proper header update procedure after these features
>> are released.
>
> I can't put this patchset into QEMU with th
aque;
> +
> + /*
> +* If the sre_el1 subsection is not transferred this
> +* means SRE_EL1 is 0x7 (which might not be the same as
> +* our reset value).
> +*/
> +cs->icc_sre_el1 = 0x7;
> +return 0;
> +}
As Peter asked before I don't rea
inter
> becomes handy.
>
> Signed-off-by: Vijaya Kumar K
> Reviewed-by: Peter Maydell
Reviewed-by: Eric Auger
Eric
> ---
> hw/intc/arm_gicv3_common.c | 2 ++
> hw/intc/arm_gicv3_cpuif.c | 8
> hw/intc/gicv3_internal.h | 2 ++
> target/arm/cpu.h | 2 +
sters are reset under one single register
> reset function instead of calling resetfn for each ICC
> register.
>
> Signed-off-by: Vijaya Kumar K
Reviewed-by: Eric Auger
Eric
> ---
> hw/intc/arm_gicv3_kvm.c | 60
> +
> 1 fil
Hi Peter,
On 24/02/2017 18:57, Peter Maydell wrote:
> On 24 February 2017 at 17:53, Auger Eric wrote:
>> Hi,
>>
>> On 23/02/2017 12:51, vijay.kil...@gmail.com wrote:
>>> From: Vijaya Kumar K
>>>
>>> To Save and Restore ICC_SRE_EL1 register intro
Hi,
On 02/10/2016 22:50, Eric Auger wrote:
> Pass an error object to prepare for migration to VFIO-PCI realize.
>
> For the time being let's just simply report the error in
> vfio platform's vfio_base_device_init(). A subsequent patch will
> duly propagate the error up to vfio_platform_realize.
>
Hi,
On 06/10/2016 11:50, Eric Auger wrote:
> Introduce an helper function to retrieve the iommu type1 capability
> chain info.
>
> The first capability ready to be exploited is the msi geometry
> capability. vfio_prepare_msi_mapping allocates a MemoryRegion
> dedicated to host MSI IOVA mapping. I
Hi Markus,
On 04/10/2016 15:20, Markus Armbruster wrote:
> Eric Auger writes:
>
>> This series converts VFIO-PCI to realize. It also aims at improving
>> the error reporting in case of QMP hot-plug.
>>
>> Before the series, a device_add failure would have reported:
>> {"error": {"class": "Generi
Hi Markus,
On 04/10/2016 15:05, Markus Armbruster wrote:
> Eric Auger writes:
>
>> The returned value is not used anymore by the caller, vfio_realize,
>> since the error now is stored in the error object. So let's remove it.
>>
>> Signed-off-by: Eric Auger
>>
>> ---
>>
>> Logically we could do
Hi Markus,
On 04/10/2016 14:03, Markus Armbruster wrote:
> Eric Auger writes:
>
>> The error is currently simply reported in vfio_get_group. Don't
>> bother too much with the prefix which will be handled at upper level,
>> later on.
>>
>> Signed-off-by: Eric Auger
>> ---
>> hw/vfio/common.c |
Hi Markus
On 04/10/2016 14:58, Markus Armbruster wrote:
> Eric Auger writes:
>
>> This patch converts VFIO PCI to realize function.
>>
>> Also original initfn errors now are propagated using QEMU
>> error objects. All errors are formatted with the same pattern:
>> "vfio: %s: the error descriptio
Hi,
On 04/10/2016 14:48, Markus Armbruster wrote:
> Eric Auger writes:
>
>> In case the vfio_init_intp fails we currently do not return an
>> error value. This patch fixes the bug. The returned value is not
>> explicit but in practice the error object is the one used to
>> report the error to th
Hi,
On 07/10/2016 09:01, Markus Armbruster wrote:
> Eric Auger writes:
>
>> The error is currently simply reported in vfio_get_group. Don't
>> bother too much with the prefix which will be handled at upper level,
>> later on.
>>
>> Also return an error value in case container->error is not 0 and
Hi,
On 10/10/2016 07:34, David Gibson wrote:
> On Fri, Oct 07, 2016 at 09:36:09AM +0200, Auger Eric wrote:
>> Hi,
>>
>> On 07/10/2016 09:01, Markus Armbruster wrote:
>>> Eric Auger writes:
>>>
>>>> The error is currently simply reported in
Hi Markus,
On 10/10/2016 14:36, Markus Armbruster wrote:
> Auger Eric writes:
>
>> Hi,
>>
>> On 10/10/2016 07:34, David Gibson wrote:
>>> On Fri, Oct 07, 2016 at 09:36:09AM +0200, Auger Eric wrote:
>>>> Hi,
>>>>
>>>> O
s->base_address = cpu_to_le64(memmap[VIRT_GIC_ITS].base);
> } else {
> gic_msi = acpi_data_push(table_data, sizeof *gic_msi);
> gic_msi->type = ACPI_APIC_GENERIC_MSI_FRAME;
>
Thanks for spotting the issue
Reviewed-by: Eric Auger
Eric
.8 */
> +vmc->no_its = true;
> }
> DEFINE_VIRT_MACHINE(2, 7)
>
> diff --git a/include/hw/arm/virt-acpi-build.h
> b/include/hw/arm/virt-acpi-build.h
> index e43330ad659b..f5ec749b8fea 100644
> --- a/include/hw/arm/virt-acpi-build.h
> +++ b/include/hw/arm/virt-acpi-build.h
> @@ -33,6 +33,7 @@ typedef struct VirtGuestInfo {
> const int *irqmap;
> bool use_highmem;
> int gic_version;
> +bool no_its;
> } VirtGuestInfo;
>
>
>
Reviewed-by: Eric Auger
Eric
Hi,
On 13/10/2016 14:02, no-re...@ec2-52-6-146-230.compute-1.amazonaws.com
wrote:
> Hi,
>
> Your series failed automatic build test. Please find the testing commands and
> their output below. If you have docker installed, you can probably reproduce
> it
> locally.
That's due to the dependency on
Hi Drew,
On 13/10/2016 17:00, Andrew Jones wrote:
> On Thu, Oct 13, 2016 at 12:55:42PM +0200, Eric Auger wrote:
>> From: Prem Mallappa
>>
>> ACPI Spec 6.0 introduces IO Remapping Table Structure. This patch
>> introduces the definitions required to describe the IO relationship
>> between the PCIe
Drew,
On 13/10/2016 17:11, Andrew Jones wrote:
> On Thu, Oct 13, 2016 at 12:55:43PM +0200, Eric Auger wrote:
>> From: Prem Mallappa
>>
>> This patch builds an IORT table that features a root complex node and
>> an ITS node. This complements the ITS description in the ACPI MADT
>> table and allows
Hi Drew,
On 14/10/2016 13:30, Andrew Jones wrote:
> On Fri, Oct 14, 2016 at 10:54:54AM +0200, Eric Auger wrote:
>> From: Prem Mallappa
>>
>> ACPI Spec 6.0 introduces IO Remapping Table Structure. This patch
>> introduces the definitions required to describe the IO relationship
>> between the PCIe
Hi Drew,
On 14/10/2016 13:57, Andrew Jones wrote:
> On Fri, Oct 14, 2016 at 10:54:55AM +0200, Eric Auger wrote:
>> From: Prem Mallappa
>>
>> This patch builds an IORT table that features a root complex node and
>> an ITS node. This complements the ITS description in the ACPI MADT
>> table and all
Hi Igor, Shannon
On 14/10/2016 14:41, Igor Mammedov wrote:
> On Fri, 14 Oct 2016 10:54:55 +0200
> Eric Auger wrote:
>
>> From: Prem Mallappa
>>
>> This patch builds an IORT table that features a root complex node and
>> an ITS node. This complements the ITS description in the ACPI MADT
>> table
Hi Igor,
On 14/10/2016 15:32, Andrew Jones wrote:
> On Fri, Oct 14, 2016 at 02:42:18PM +0200, Igor Mammedov wrote:
>> On Fri, 14 Oct 2016 10:54:54 +0200
>> Eric Auger wrote:
>>
>>> From: Prem Mallappa
>>>
>>> ACPI Spec 6.0 introduces IO Remapping Table Structure. This patch
>>> introduces the de
Hi,
On 17/10/2016 22:16, no-re...@ec2-52-6-146-230.compute-1.amazonaws.com
wrote:
> Hi,
>
> Your series failed automatic build test. Please find the testing commands and
> their output below. If you have docker installed, you can probably reproduce
> it
> locally.
>
> Subject: [Qemu-devel] [RFC
Hi Fam,
On 18/10/2016 15:34, Fam Zheng wrote:
> On Mon, 10/17 22:56, Auger Eric wrote:
>>> make[1]: *** No rule to make target `../hw/core/platform-bus-stub.o',
>>> needed by `qemu-system-x86_64'. Stop.
>> I can't figure out why this rule is missing
Hi Peter,
On 29/07/2016 15:35, Peter Maydell wrote:
> On 6 July 2016 at 10:46, Eric Auger wrote:
>> +/**
>> + *
>> + * We currently do not use kvm_arm_register_device to provide
>> + * the kernel with the vITS control frame base address since the
>> + * KVM_DEV_ARM_VGIC_CTRL_INIT init MUST be call
Hi Shannon,
On 03/08/2016 02:56, Shannon Zhao wrote:
> Hi Eric,
>
> On 2016/8/3 2:07, Eric Auger wrote:
>> This patch exposes the GICv3 ITS to the ACPI guest. The ITS structure
>> is added to the MADT table.
>>
>> Signed-off-by: Eric Auger
>>
>> ---
>>
>> v5: new
>>
>> Tested with Tomasz' kernel
Hi Shannon,
On 03/08/2016 10:50, Shannon Zhao wrote:
>
>
> On 2016/8/3 15:22, Auger Eric wrote:
>> Hi Shannon,
>>
>> On 03/08/2016 02:56, Shannon Zhao wrote:
>>>> Hi Eric,
>>>>
>>>> On 2016/8/3 2:07, Eric Auger wrote:
>>>&
Hi
On 06/07/2016 11:46, Eric Auger wrote:
> Machine.c contains code related to migration. Let's move
> gicv3_class_name to kvm_arm.h instead.
>
> Signed-off-by: Eric Auger
> Suggested-by: Peter Maydell
>
> ---
>
> v4: creation
> ---
> target-arm/kvm_arm.h | 16 +++-
> target-arm/m
fio
integration yet.
Thanks
Eric
>
> Is there any other better option I am missing?
>
> Thanks
> -Bharat
>
>> -Original Message-
>> From: Auger Eric [mailto:eric.au...@redhat.com]
>> Sent: Friday, June 09, 2017 5:24 PM
>> To: Bharat Bhushan ;
>
Hi Jean-Philippe,
On 19/06/2017 12:15, Jean-Philippe Brucker wrote:
> On 19/06/17 08:54, Bharat Bhushan wrote:
>> Hi Eric,
>>
>> I started added replay in virtio-iommu and came across how MSI interrupts
>> with work with VFIO.
>> I understand that on intel this works differently but vsmmu will h
Hi Jean-Philippe,
On 26/06/2017 18:13, Jean-Philippe Brucker wrote:
> On 26/06/17 09:22, Auger Eric wrote:
>> Hi Jean-Philippe,
>>
>> On 19/06/2017 12:15, Jean-Philippe Brucker wrote:
>>> On 19/06/17 08:54, Bharat Bhushan wrote:
>>>> Hi Eric,
>>&g
Hi,
On 27/06/2017 10:46, Will Deacon wrote:
> Hi Eric,
>
> On Tue, Jun 27, 2017 at 08:38:48AM +0200, Auger Eric wrote:
>> On 26/06/2017 18:13, Jean-Philippe Brucker wrote:
>>> On 26/06/17 09:22, Auger Eric wrote:
>>>> On 19/06/2017 12:15, Jean-Philippe Br
Hi,
On 07/06/2017 17:00, no-re...@patchew.org wrote:
> Hi,
>
> This series failed automatic build test. Please find the testing commands and
> their output below. If you have docker installed, you can probably reproduce
> it
> locally.
>
> Message-id: 1496824556-1883-1-git-send-email-eric.au...
Hi Shannon,
On 19/05/2017 12:30, Shannon Zhao wrote:
>
>
> On 2017/4/14 20:46, Eric Auger wrote:
>> We change the restoration priority of both the GICv3 and ITS. The
>> GICv3 must be restored before the ITS and the ITS needs to be restored
>> before PCIe devices since it translates their MSI tran
Hi Bharat,
On 09/06/2017 08:16, Bharat Bhushan wrote:
> Hi Eric,
>
>> -Original Message-
>> From: Eric Auger [mailto:eric.au...@redhat.com]
>> Sent: Wednesday, June 07, 2017 9:31 PM
>> To: eric.auger@gmail.com; eric.au...@redhat.com;
>> peter.mayd...@linaro.org; alex.william...@redhat
Hi Bharat,
On 09/06/2017 13:30, Bharat Bhushan wrote:
> Hi Eric,
>
>> -Original Message-----
>> From: Auger Eric [mailto:eric.au...@redhat.com]
>> Sent: Friday, June 09, 2017 12:14 PM
>> To: Bharat Bhushan ;
>> eric.auger@gmail.com; peter.mayd...@linar
Hi,
On 09/06/2017 13:30, Bharat Bhushan wrote:
> Hi Eric,
>
>> -Original Message-----
>> From: Auger Eric [mailto:eric.au...@redhat.com]
>> Sent: Friday, June 09, 2017 12:14 PM
>> To: Bharat Bhushan ;
>> eric.auger@gmail.com; peter.mayd...@linaro.o
Hi Shannon,
On 09/06/2017 03:28, Shannon Zhao wrote:
>
>
> On 2017/4/14 20:46, Eric Auger wrote:
> [...]
>> @@ -43,6 +50,7 @@ struct GICv3ITSState {
>>
>> /* Registers */
>> uint32_t ctlr;
>> +uint32_t iidr;
> I think this should reset in gicv3_its_common_reset
Done.
Thanks!
E
Hi Juan,
On 12/06/2017 08:23, Juan Quintela wrote:
> Eric Auger wrote:
>> In some circumstances, we don't want to abort if the
>> kvm_device_access fails. This will be the case during ITS
>> migration, in case the ITS table save/restore fails because
>> the guest did not program the vITS correctl
Hi Dave,
On 26/01/2017 11:06, Dr. David Alan Gilbert wrote:
> * Eric Auger (eric.au...@redhat.com) wrote:
>> We change the restoration priority of both the GICv3 and ITS. The
>> GICv3 must be restored before the ITS and the ITS needs to be restored
>> before PCIe devices since it translates their
Hi Peter,
On 26/01/2017 11:41, Peter Maydell wrote:
> On 26 January 2017 at 07:58, Auger Eric wrote:
>> On 20/01/2017 16:52, Peter Maydell wrote:
>>> So this patch added a no_its flag which gets set for virt-2.7
>>> and earlier, but there's no user-facing way
Hi Vijaya,
On 27/01/2017 08:17, Vijay Kilari wrote:
> Hi Eric,
>
> On Thu, Jan 26, 2017 at 2:49 PM, Eric Auger wrote:
>> We need to handle both registers and ITS tables. While
>> register handling is standard, ITS table handling is more
>> challenging since the kernel API is devised so that the
Hi Vijaya,
On 27/01/2017 08:02, Vijay Kilari wrote:
> Hi Eric,
>
> On Thu, Jan 26, 2017 at 2:49 PM, Eric Auger wrote:
>> Rename KVM_DEV_ARM_VGIC_GRP_CPU_SYSREGS into KVM_DEV_ARM_VGIC_CPU_SYSREGS
>> as exposed in the kernel user API and pulled by update-linux-headers.sh.
>
> I will fix it in my
Hi Juan,
On 30/01/2017 10:15, Juan Quintela wrote:
> Eric Auger wrote:
>> We need to handle both registers and ITS tables. While
>> register handling is standard, ITS table handling is more
>> challenging since the kernel API is devised so that the
>> tables are flushed into guest RAM and not in
Hi Thomas,
On 31/01/2017 19:51, Thomas Huth wrote:
> On 31.01.2017 18:30, Alex Williamson wrote:
>> On Tue, 31 Jan 2017 17:36:35 +0100
>> Thomas Huth wrote:
>>
>>> Both devices seem to be specific to the ARM platform. It's confusing
>>> for the users if they show up on other target architectures,
Hi Vijay,
On 31/01/2017 17:23, vijay.kil...@gmail.com wrote:
> From: Vijaya Kumar K
>
> This actually implements pre_save and post_load methods for in-kernel
> vGICv3.
>
> Signed-off-by: Pavel Fedin
> Signed-off-by: Peter Maydell
> [PMM:
> * use decimal, not 0bnnn
> * fixed typo in names of
Hi,
On 05/05/2017 04:03, Dong Jia Shi wrote:
> From: Xiao Feng Ren
>
> We use the IOMMU_TYPE1 of VFIO to realize the subchannels
> passthrough, implement a vfio based subchannels passthrough
> driver called "vfio-ccw".
>
> Support qemu parameters in the style of:
> "-device vfio-ccw,sysfsdev=$m
Hi
On 05/05/2017 04:03, Dong Jia Shi wrote:
> In order to support subchannels pass-through, we introduce a s390
> subchannel device called "s390-ccw" to hold the real subchannel info.
> The s390-ccw devices inherit from the abstract CcwDevice which connect
> to the existing virtual-css-bus.
>
> S
Hi,
On 05/05/2017 04:03, Dong Jia Shi wrote:
> vfio-ccw provides an MMIO region for I/O operations. We fetch its
> information via ioctls here, then we can use it performing I/O
> instructions and retrieving I/O results later on.
>
> Signed-off-by: Dong Jia Shi
Reviewed-by: Eric Auger
Thanks
Hi,
On 05/05/2017 04:03, Dong Jia Shi wrote:
> vfio-ccw resorts to the eventfd mechanism to communicate with userspace.
> We fetch the irqs info via the ioctl VFIO_DEVICE_GET_IRQ_INFO,
> register a event notifier to get the eventfd fd which is sent
> to kernel via the ioctl VFIO_DEVICE_SET_IRQS, t
Hi Peter, all,
On 07/02/2017 15:36, Peter Maydell wrote:
> On 26 January 2017 at 09:19, Eric Auger wrote:
>> This series allows ITS save/restore and migration use cases.
>> It relies on not upstreamed kernel series ([1] & [2]) and
>> QEMU not upstreamed series [3].
>>
>> ITS tables are flushed in
Hi,
On 17/02/2017 07:31, vijay.kil...@gmail.com wrote:
> From: Vijaya Kumar K
>
> To Save and Restore ICC_SRE_EL1 register introduce vmstate
> subsection and load only if non-zero.
> Also initialize icc_sre_el1 with to 0x7 in pre_load
> function.
>
> Signed-off-by: Vijaya Kumar K
> ---
> hw/i
Hi Vijaya,
On 13/02/2017 13:17, Vijay Kilari wrote:
> On Tue, Feb 7, 2017 at 8:09 PM, Peter Maydell
> wrote:
>> On 31 January 2017 at 16:22, wrote:
>>> From: Vijaya Kumar K
>>>
>>> To Save and Restore ICC_SRE_EL1 register Add ICC_SRE_EL1 register
>>> to vmstate and GICv3CPUState struct.
>>>
>
Hi Sinan,
On 21/02/2017 15:45, Sinan Kaya wrote:
> Hi Eric,
> Thanks for the long anticipated patch.
>
> On 2/21/2017 8:18 AM, Eric Auger wrote:
>> +DEFINE_PROP_STRING("manufacturer", VFIOPlatformDevice, manufacturer),
>> +DEFINE_PROP_STRING("model", VFIOPlatformDevice, model),
>
> The OF
Hi Sinan,
On 21/02/2017 16:10, Sinan Kaya wrote:
> On 2/21/2017 9:59 AM, Auger Eric wrote:
>> Hi Sinan,
>> On 21/02/2017 15:45, Sinan Kaya wrote:
>>> Hi Eric,
>>> Thanks for the long anticipated patch.
>>>
>>> On 2/21/2017 8:18 AM, Eric Auge
Hi Sinan,
On 21/02/2017 16:34, Sinan Kaya wrote:
> On 2/21/2017 10:23 AM, Auger Eric wrote:
>>> Note that the goal is to be able to instantiate any platform device by just
>>> passing a compatible string and the object from the host. We don't want
>>> to make
Hi Alex,
On 21/02/2017 20:10, Alex Williamson wrote:
> Currently we ignore this error, report it with error_reportf_err()
>
> Signed-off-by: Alex Williamson
Reviewed-by: Eric Auger
Eric
> ---
> hw/vfio/pci.c |6 +-
> 1 file changed, 5 insertions(+), 1 deletion(-)
Hi,
On 22/08/2016 18:17, Prem Mallappa wrote:
> v1 -> v2:
> - Adopted review comments from Eric Auger
> - Make SMMU_DPRINTF to internally call qemu_log
> (since translation requests are too many, we need control
>on the type of log we want)
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